Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	1	30	96.77	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1926

1

T1

13

T2

16

T3

2

auto[1]

666

1

T1

2

T3

4

T6

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1868

1

T2

16

T3

3

T6

18

auto[1]

724

1

T1

15

T3

3

T6

10

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1936

1

T1

15

T2

16

T3

4

auto[1]

656

1

T3

2

T6

8

T12

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1933

1

T1

13

T2

16

T3

4

auto[1]

659

1

T1

2

T3

2

T7

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T1

15

T2

12

T3

6

auto[1]

211

1

T2

4

T6

7

T28

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2408

1

T1

15

T2

16

T3

6

auto[1]

184

1

T6

3

T7

4

T12

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2345

1

T1

15

T2

12

T3

6

auto[1]

247

1

T2

4

T6

4

T7

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2384

1

T1

15

T2

12

T3

6

auto[1]

208

1

T2

4

T6

6

T12

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2354

1

T1

15

T2

16

T3

6

auto[1]

238

1

T6

1

T28

4

T69

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1918

1

T1

15

T2

12

T3

2

auto[1]

674

1

T2

4

T3

4

T6

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	875	1			T1	15		T3	6		T41	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	57	1			T215	18		T298	1		T194	13
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	110	1			T69	1		T217	17		T92	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	9	1			T198	1		T307	6		T312	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	97	1			T6	3		T12	6		T217	17
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	14	1			T216	10		T313	3		T314	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	16	1			T6	1		T92	2		T307	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	104	1			T28	1		T141	1		T212	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	24	1			T6	3		T217	9		T315	8
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	32	1			T194	12		T316	5		T315	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T307	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T216	4		T317	7		T306	6
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T2	4		T318	1		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	10	1			T217	8		T319	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	4	1			T215	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	52	1			T12	5		T69	2		T212	7
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	56	1			T6	2		T216	26		T194	8
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	11	1			T320	2		T321	1		T322	8
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T212	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	16	1			T304	1		T323	4		T204	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T324	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	18	1			T7	4		T317	3		T325	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	6	1			T318	2		T218	2		T204	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T318	1		T326	4		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T218	3		T327	2		T311	2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	1	30	96.77	1
Automatically Generated Cross Bins	31	1	30	96.77	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

107

1

T64

12

T31

9

T159

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

133

1

T2

4

T28

1

T228

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T3

3

T64

7

T110

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

71

1

T217

9

T194

8

T198

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T128

1

T194

12

T328

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T7

4

T128

9

T212

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T80

1

T317

3

T297

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

94

1

T30

8

T69

2

T233

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

60

1

T185

5

T92

2

T324

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

93

1

T6

2

T29

4

T30

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

47

1

T64

5

T233

5

T128

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T216

13

T138

5

T320

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T12

5

T321

1

T221

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

28

1

T216

13

T220

2

T315

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T76

1

T81

1

T302

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

158

1

T1

13

T6

4

T215

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

50

1

T69

1

T217

8

T192

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T31

3

T34

1

T220

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T3

1

T97

2

T300

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T80

1

T159

1

T298

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

88

1

T1

2

T31

1

T141

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T233

3

T192

4

T220

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T80

1

T303

1

T301

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T215

9

T80

2

T329

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T76

3

T228

4

T138

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T12

3

T31

2

T87

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T6

3

T12

3

T317

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T3

2

T41

1

T92

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T330

3

T211

1

T331

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T128

2

T81

1

T309

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded