Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T17

8

T18

9

T54

11

auto[1]

1095

1

T17

12

T18

11

T54

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T17

4

T18

4

T54

6

from_0to1

535

1

T17

4

T18

4

T54

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T17

11

T18

13

T54

12

auto[1]

1096

1

T17

9

T18

7

T54

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T17

7

T18

14

T54

12

auto[1]

1108

1

T17

13

T18

6

T54

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T17

2

T18

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T54

1

T67

1

T25

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T54

1

T270

2

T61

3

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T18

1

T67

2

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T17

1

T18

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T54

1

T67

1

T184

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T18

1

T270

1

T184

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T54

2

T61

1

T45

3

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T18

1

T54

3

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T17

1

T270

1

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T17

1

T18

1

T270

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T67

2

T186

1

T45

3

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T17

1

T18

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T17

1

T18

1

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T17

1

T54

1

T270

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T54

1

T67

1

T186

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T17

8

T18

12

T54

10

auto[1]

1066

1

T17

12

T18

8

T54

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T17

5

T18

5

T54

5

from_0to1

521

1

T17

4

T18

5

T54

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T17

8

T18

8

T54

10

auto[1]

1065

1

T17

12

T18

12

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T17

12

T18

11

T54

11

auto[1]

1110

1

T17

8

T18

9

T54

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T17

1

T54

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T17

1

T18

1

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T17

1

T18

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T18

1

T67

1

T186

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T54

1

T67

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T18

1

T270

1

T61

2

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T54

1

T25

1

T184

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T18

1

T184

1

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T18

1

T54

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T67

1

T25

1

T184

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T17

2

T18

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T270

2

T61

1

T25

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T17

2

T18

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T17

1

T18

1

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T17

1

T67

1

T270

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T18

1

T54

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T17

9

T18

12

T54

11

auto[1]

1079

1

T17

11

T18

8

T54

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T17

4

T18

5

T54

6

from_0to1

524

1

T17

5

T18

6

T54

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T17

13

T18

9

T54

10

auto[1]

1113

1

T17

7

T18

11

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T17

11

T18

12

T54

11

auto[1]

1094

1

T17

9

T18

8

T54

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T54

1

T67

1

T270

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T18

1

T54

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T18

1

T54

1

T67

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T54

1

T61

1

T25

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T17

1

T18

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T18

1

T54

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T17

1

T18

1

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T61

1

T25

1

T45

4

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T17

2

T18

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T17

1

T67

1

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T18

1

T67

1

T61

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T17

1

T18

1

T54

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T17

2

T54

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T54

1

T270

3

T25

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T18

2

T54

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T17

1

T18

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T17

10

T18

8

T54

11

auto[1]

1108

1

T17

10

T18

12

T54

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

547

1

T17

5

T18

3

T54

4

from_0to1

533

1

T17

5

T18

3

T54

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T17

13

T18

10

T54

9

auto[1]

1093

1

T17

7

T18

10

T54

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T17

13

T18

11

T54

8

auto[1]

1106

1

T17

7

T18

9

T54

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T17

1

T54

1

T184

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T270

1

T25

1

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T17

1

T18

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T17

1

T54

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T17

2

T67

2

T270

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T270

1

T25

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T67

1

T25

1

T186

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T17

1

T18

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T17

1

T67

1

T270

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T18

1

T67

1

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T17

1

T67

1

T270

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T18

1

T54

1

T61

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T17

1

T18

2

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T17

1

T54

1

T270

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T54

1

T25

1

T184

2

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T54

1

T67

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T17

4

T18

8

T54

8

auto[1]

1109

1

T17

16

T18

12

T54

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

513

1

T17

5

T18

5

T54

4

from_0to1

509

1

T17

4

T18

4

T54

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T17

9

T18

8

T54

11

auto[1]

1105

1

T17

11

T18

12

T54

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T17

11

T18

7

T54

11

auto[1]

1090

1

T17

9

T18

13

T54

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T67

2

T270

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T270

1

T184

1

T186

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T17

1

T54

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T18

1

T270

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T54

1

T270

1

T184

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T270

1

T61

2

T184

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T17

1

T18

2

T25

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T25

2

T184

2

T45

2

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T18

1

T54

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T17

1

T54

1

T270

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T17

2

T18

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T17

1

T18

2

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T17

3

T54

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T18

1

T67

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T67

2

T270

1

T61

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T18

1

T54

1

T67

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T17

9

T18

11

T54

9

auto[1]

1074

1

T17

11

T18

9

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T17

5

T18

4

T54

6

from_0to1

527

1

T17

4

T18

5

T54

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T17

9

T18

12

T54

10

auto[1]

1084

1

T17

11

T18

8

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T17

13

T18

9

T54

9

auto[1]

1094

1

T17

7

T18

11

T54

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T17

1

T54

1

T25

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T18

1

T270

1

T61

2

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T18

1

T54

2

T25

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T17

1

T67

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T17

1

T18

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T18

1

T54

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T67

2

T61

2

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T18

1

T67

1

T270

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T17

1

T18

1

T270

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T18

1

T54

1

T270

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T17

1

T54

1

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T17

1

T54

1

T67

2

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T18

1

T54

1

T186

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T270

2

T61

1

T25

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T17

2

T18

1

T25

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T17

1

T54

2

T270

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T17

10

T18

12

T54

11

auto[1]

1077

1

T17

10

T18

8

T54

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T17

4

T18

5

T54

3

from_0to1

539

1

T17

5

T18

6

T54

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T17

11

T18

5

T54

11

auto[1]

1061

1

T17

9

T18

15

T54

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T17

11

T18

10

T54

8

auto[1]

1088

1

T17

9

T18

10

T54

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T17

1

T270

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T67

1

T270

1

T61

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T54

1

T61

1

T45

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T17

1

T18

3

T184

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T17

1

T18

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T17

1

T18

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T17

1

T270

2

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T18

1

T54

2

T270

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T17

1

T54

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T54

1

T67

1

T270

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T17

1

T18

2

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T25

1

T45

2

T271

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T17

1

T61

1

T25

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T18

1

T54

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T18

1

T25

1

T184

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T17

1

T18

1

T67

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T17

14

T18

14

T54

7

auto[1]

1132

1

T17

6

T18

6

T54

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T17

6

T18

5

T54

6

from_0to1

523

1

T17

5

T18

5

T54

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T17

11

T18

15

T54

6

auto[1]

1138

1

T17

9

T18

5

T54

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T17

6

T18

8

T54

10

auto[1]

1130

1

T17

14

T18

12

T54

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T17

1

T18

1

T61

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T17

1

T18

2

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T17

1

T54

1

T270

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T17

1

T54

1

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T17

2

T61

1

T25

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T17

2

T18

1

T54

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T67

1

T61

2

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T18

1

T270

1

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T18

1

T25

1

T186

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T17

1

T67

1

T184

2

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T54

2

T270

1

T184

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T17

1

T18

1

T54

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T18

2

T54

1

T186

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T18

1

T54

1

T67

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T54

3

T61

1

T25

1

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T17

1

T54

1

T67

1