Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158058	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121149

1

T4

12

T5

2

T1

446

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146427	1			T4	16		T5	3		T1	649
values[0x0]	65639	1			T4	4		T5	2		T1	173
values[0x1]	67141	1			T4	2		T1	172		T2	290

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127394	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151813

1

T4

14

T5

2

T1

537

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	965	1			T17	2		T39	4		T10	1
valid_sources[0x01]	1105	1			T2	14		T3	4		T6	8
valid_sources[0x02]	866	1			T17	1		T39	2		T54	1
valid_sources[0x03]	864	1			T4	1		T18	4		T39	1
valid_sources[0x04]	1105	1			T2	8		T39	2		T10	2
valid_sources[0x05]	1201	1			T4	1		T3	1		T14	1
valid_sources[0x06]	1651	1			T3	4		T14	1		T17	1
valid_sources[0x07]	2842	1			T3	2		T18	1		T6	26
valid_sources[0x08]	881	1			T3	2		T17	1		T18	3
valid_sources[0x09]	868	1			T3	8		T17	3		T10	1
valid_sources[0x0a]	935	1			T4	1		T18	1		T6	1
valid_sources[0x0b]	930	1			T3	1		T6	20		T39	3
valid_sources[0x0c]	1288	1			T17	2		T6	18		T39	4
valid_sources[0x0d]	1160	1			T3	2		T6	11		T270	1
valid_sources[0x0e]	1300	1			T3	2		T18	3		T36	1
valid_sources[0x0f]	1918	1			T3	10		T14	1		T17	1
valid_sources[0x10]	1183	1			T2	47		T39	1		T10	1
valid_sources[0x11]	1137	1			T5	2		T3	9		T17	2
valid_sources[0x12]	864	1			T3	2		T14	1		T18	1
valid_sources[0x13]	1044	1			T3	1		T18	3		T39	5
valid_sources[0x14]	1073	1			T1	3		T3	5		T14	1
valid_sources[0x15]	905	1			T3	2		T6	10		T39	1
valid_sources[0x16]	718	1			T3	3		T18	1		T39	1
valid_sources[0x17]	788	1			T3	1		T6	1		T54	1
valid_sources[0x18]	1304	1			T3	1		T6	12		T39	6
valid_sources[0x19]	1188	1			T3	4		T18	1		T6	25
valid_sources[0x1a]	1173	1			T3	1		T6	2		T10	3
valid_sources[0x1b]	853	1			T3	2		T6	1		T10	2
valid_sources[0x1c]	806	1			T3	2		T17	1		T6	5
valid_sources[0x1d]	923	1			T17	1		T6	11		T54	2
valid_sources[0x1e]	829	1			T2	1		T3	1		T14	1
valid_sources[0x1f]	893	1			T17	2		T39	3		T54	2
valid_sources[0x20]	3047	1			T17	1		T18	1		T10	2
valid_sources[0x21]	917	1			T3	2		T39	1		T54	1
valid_sources[0x22]	872	1			T3	3		T16	3		T17	1
valid_sources[0x23]	1098	1			T3	3		T39	1		T54	1
valid_sources[0x24]	1554	1			T2	24		T6	13		T270	2
valid_sources[0x25]	1042	1			T3	4		T17	1		T6	13
valid_sources[0x26]	1498	1			T4	1		T3	2		T259	1
valid_sources[0x27]	1767	1			T39	3		T10	1		T270	4
valid_sources[0x28]	757	1			T54	2		T10	1		T270	3
valid_sources[0x29]	839	1			T17	1		T39	3		T40	3
valid_sources[0x2a]	881	1			T3	6		T10	1		T41	6
valid_sources[0x2b]	2122	1			T14	1		T6	12		T39	5
valid_sources[0x2c]	843	1			T6	3		T270	1		T61	1
valid_sources[0x2d]	800	1			T3	2		T17	1		T6	4
valid_sources[0x2e]	925	1			T3	1		T17	1		T18	4
valid_sources[0x2f]	913	1			T3	1		T14	3		T17	1
valid_sources[0x30]	1098	1			T3	3		T14	1		T17	1
valid_sources[0x31]	1072	1			T14	2		T17	1		T18	1
valid_sources[0x32]	1179	1			T3	1		T6	6		T39	2
valid_sources[0x33]	917	1			T10	1		T41	5		T259	2
valid_sources[0x34]	853	1			T18	3		T40	20		T54	2
valid_sources[0x35]	838	1			T2	3		T14	2		T39	1
valid_sources[0x36]	1066	1			T3	5		T17	1		T6	4
valid_sources[0x37]	876	1			T3	2		T16	1		T6	5
valid_sources[0x38]	907	1			T3	1		T14	3		T17	1
valid_sources[0x39]	963	1			T1	120		T3	3		T39	2
valid_sources[0x3a]	1147	1			T3	3		T14	1		T17	1
valid_sources[0x3b]	824	1			T3	2		T18	1		T6	9
valid_sources[0x3c]	917	1			T14	1		T6	9		T39	1
valid_sources[0x3d]	1611	1			T18	3		T6	11		T39	3
valid_sources[0x3e]	782	1			T3	1		T39	7		T10	1
valid_sources[0x3f]	1698	1			T3	1		T6	7		T39	3
valid_sources[0x40]	685	1			T3	5		T17	1		T18	1
valid_sources[0x41]	991	1			T2	10		T3	8		T14	1
valid_sources[0x42]	928	1			T3	1		T15	44		T16	2
valid_sources[0x43]	890	1			T6	3		T39	1		T10	1
valid_sources[0x44]	1087	1			T16	1		T17	1		T39	10
valid_sources[0x45]	1248	1			T2	65		T3	3		T39	2
valid_sources[0x46]	1403	1			T3	2		T18	1		T39	6
valid_sources[0x47]	1333	1			T4	1		T18	2		T39	1
valid_sources[0x48]	1206	1			T3	2		T6	48		T10	1
valid_sources[0x49]	981	1			T3	3		T17	1		T18	6
valid_sources[0x4a]	1131	1			T3	1		T17	1		T6	1
valid_sources[0x4b]	951	1			T17	1		T6	4		T39	2
valid_sources[0x4c]	950	1			T17	2		T39	6		T54	1
valid_sources[0x4d]	1283	1			T3	6		T14	1		T16	4
valid_sources[0x4e]	1337	1			T3	1		T39	2		T10	3
valid_sources[0x4f]	958	1			T3	4		T41	3		T38	2
valid_sources[0x50]	840	1			T6	9		T39	5		T54	1
valid_sources[0x51]	879	1			T2	8		T3	4		T17	2
valid_sources[0x52]	1243	1			T3	1		T16	1		T39	10
valid_sources[0x53]	1514	1			T3	1		T54	1		T58	1
valid_sources[0x54]	944	1			T3	2		T17	1		T18	1
valid_sources[0x55]	1030	1			T16	1		T10	1		T41	1
valid_sources[0x56]	1906	1			T3	2		T39	5		T41	1
valid_sources[0x57]	836	1			T4	1		T2	40		T3	2
valid_sources[0x58]	1941	1			T54	1		T36	1		T270	1
valid_sources[0x59]	2138	1			T3	5		T14	1		T39	1
valid_sources[0x5a]	766	1			T2	16		T3	1		T16	1
valid_sources[0x5b]	819	1			T39	2		T10	2		T29	9
valid_sources[0x5c]	1717	1			T3	1		T18	1		T54	1
valid_sources[0x5d]	904	1			T3	2		T14	1		T39	1
valid_sources[0x5e]	910	1			T4	2		T3	1		T14	1
valid_sources[0x5f]	869	1			T2	14		T10	3		T41	5
valid_sources[0x60]	1029	1			T3	2		T14	1		T17	1
valid_sources[0x61]	1150	1			T3	2		T6	5		T39	2
valid_sources[0x62]	1006	1			T3	2		T41	1		T42	11
valid_sources[0x63]	1035	1			T4	1		T3	7		T14	1
valid_sources[0x64]	879	1			T14	1		T17	3		T6	2
valid_sources[0x65]	1007	1			T2	3		T3	1		T18	3
valid_sources[0x66]	1035	1			T2	10		T3	5		T54	3
valid_sources[0x67]	1116	1			T3	5		T18	4		T6	1
valid_sources[0x68]	842	1			T3	1		T17	1		T18	3
valid_sources[0x69]	928	1			T3	8		T16	1		T17	3
valid_sources[0x6a]	1278	1			T3	1		T39	1		T10	2
valid_sources[0x6b]	1282	1			T2	6		T3	1		T18	4
valid_sources[0x6c]	915	1			T3	4		T10	2		T149	1
valid_sources[0x6d]	2012	1			T17	2		T6	28		T42	2
valid_sources[0x6e]	1253	1			T1	2		T3	13		T6	6
valid_sources[0x6f]	834	1			T3	1		T14	3		T10	1
valid_sources[0x70]	1796	1			T4	2		T1	607		T3	4
valid_sources[0x71]	1072	1			T3	2		T14	1		T6	25
valid_sources[0x72]	1021	1			T2	4		T3	3		T17	1
valid_sources[0x73]	1777	1			T3	10		T17	1		T6	7
valid_sources[0x74]	827	1			T2	3		T3	1		T6	10
valid_sources[0x75]	959	1			T3	2		T17	2		T42	9
valid_sources[0x76]	963	1			T3	3		T6	1		T39	13
valid_sources[0x77]	1123	1			T3	1		T17	2		T39	1
valid_sources[0x78]	1029	1			T17	1		T6	27		T10	2
valid_sources[0x79]	866	1			T3	8		T6	1		T29	11
valid_sources[0x7a]	887	1			T3	2		T6	5		T39	5
valid_sources[0x7b]	895	1			T17	2		T6	14		T54	1
valid_sources[0x7c]	1028	1			T3	1		T16	3		T10	1
valid_sources[0x7d]	905	1			T4	1		T3	1		T6	1
valid_sources[0x7e]	1140	1			T2	13		T6	5		T39	7
valid_sources[0x7f]	883	1			T6	3		T39	4		T10	3
valid_sources[0x80]	945	1			T1	20		T56	4		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65799

1

T4

9

T5

2

T1

334

values[0x0]

all_enables

biggest_size

32216

1

T4

3

T1

75

T2

107

values[0x1]

all_enables

biggest_size

23134

1

T1

37

T2

68

T3

20