Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1270635435	11771	0	0
auto_block_debounce_ctl_rd_A	1270635435	2487	0	0
auto_block_out_ctl_rd_A	1270635435	3438	0	0
com_det_ctl_0_rd_A	1270635435	4536	0	0
com_det_ctl_1_rd_A	1270635435	4620	0	0
com_det_ctl_2_rd_A	1270635435	4878	0	0
com_det_ctl_3_rd_A	1270635435	4634	0	0
com_out_ctl_0_rd_A	1270635435	5224	0	0
com_out_ctl_1_rd_A	1270635435	5637	0	0
com_out_ctl_2_rd_A	1270635435	5309	0	0
com_out_ctl_3_rd_A	1270635435	5289	0	0
com_pre_det_ctl_0_rd_A	1270635435	1915	0	0
com_pre_det_ctl_1_rd_A	1270635435	1934	0	0
com_pre_det_ctl_2_rd_A	1270635435	1853	0	0
com_pre_det_ctl_3_rd_A	1270635435	1884	0	0
com_pre_sel_ctl_0_rd_A	1270635435	5570	0	0
com_pre_sel_ctl_1_rd_A	1270635435	5639	0	0
com_pre_sel_ctl_2_rd_A	1270635435	5945	0	0
com_pre_sel_ctl_3_rd_A	1270635435	5987	0	0
com_sel_ctl_0_rd_A	1270635435	5754	0	0
com_sel_ctl_1_rd_A	1270635435	5643	0	0
com_sel_ctl_2_rd_A	1270635435	5608	0	0
com_sel_ctl_3_rd_A	1270635435	5660	0	0
ec_rst_ctl_rd_A	1270635435	2914	0	0
intr_enable_rd_A	1270635435	2762	0	0
key_intr_ctl_rd_A	1270635435	5050	0	0
key_intr_debounce_ctl_rd_A	1270635435	2047	0	0
key_invert_ctl_rd_A	1270635435	7198	0	0
pin_allowed_ctl_rd_A	1270635435	7712	0	0
pin_out_ctl_rd_A	1270635435	5887	0	0
pin_out_value_rd_A	1270635435	6312	0	0
regwen_rd_A	1270635435	2275	0	0
ulp_ac_debounce_ctl_rd_A	1270635435	2014	0	0
ulp_ctl_rd_A	1270635435	2075	0	0
ulp_lid_debounce_ctl_rd_A	1270635435	1970	0	0
ulp_pwrb_debounce_ctl_rd_A	1270635435	2117	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	11771	0	0
T1	100753	8	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T10	0	7	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	17	0	0
T31	0	9	0	0
T33	0	13	0	0
T34	0	11	0	0
T40	0	11	0	0
T45	0	18	0	0
T49	0	3	0	0
T128	0	21	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2487	0	0
T1	100753	14	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	40	0	0
T33	0	31	0	0
T34	0	12	0	0
T49	0	18	0	0
T110	0	41	0	0
T171	0	20	0	0
T193	0	29	0	0
T262	0	9	0	0
T263	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	3438	0	0
T1	100753	9	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	39	0	0
T33	0	38	0	0
T34	0	15	0	0
T49	0	21	0	0
T110	0	43	0	0
T193	0	12	0	0
T262	0	17	0	0
T263	0	15	0	0
T264	0	1	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	4536	0	0
T1	100753	75	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	33	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	19	0	0
T33	0	39	0	0
T34	0	21	0	0
T49	0	8	0	0
T64	0	63	0	0
T217	0	99	0	0
T228	0	73	0	0
T265	0	31	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	4620	0	0
T1	100753	76	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	42	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	18	0	0
T33	0	36	0	0
T34	0	14	0	0
T49	0	4	0	0
T64	0	66	0	0
T217	0	96	0	0
T228	0	70	0	0
T265	0	45	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	4878	0	0
T1	100753	98	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	33	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	32	0	0
T33	0	23	0	0
T34	0	17	0	0
T49	0	16	0	0
T64	0	50	0	0
T217	0	103	0	0
T228	0	91	0	0
T265	0	26	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	4634	0	0
T1	100753	68	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	26	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	23	0	0
T33	0	30	0	0
T34	0	28	0	0
T49	0	12	0	0
T64	0	70	0	0
T217	0	81	0	0
T228	0	87	0	0
T265	0	28	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5224	0	0
T1	100753	88	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	49	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	26	0	0
T33	0	38	0	0
T34	0	37	0	0
T49	0	4	0	0
T64	0	60	0	0
T217	0	100	0	0
T228	0	98	0	0
T265	0	38	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5637	0	0
T1	100753	61	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	29	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	34	0	0
T33	0	36	0	0
T34	0	8	0	0
T49	0	18	0	0
T64	0	48	0	0
T217	0	95	0	0
T228	0	72	0	0
T265	0	33	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5309	0	0
T1	100753	81	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	37	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	17	0	0
T33	0	46	0	0
T34	0	29	0	0
T49	0	13	0	0
T64	0	67	0	0
T217	0	89	0	0
T228	0	73	0	0
T265	0	31	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5289	0	0
T1	100753	66	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	38	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	17	0	0
T33	0	35	0	0
T34	0	8	0	0
T49	0	10	0	0
T64	0	79	0	0
T217	0	99	0	0
T228	0	65	0	0
T265	0	31	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	1915	0	0
T1	100753	1	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	29	0	0
T33	0	33	0	0
T34	0	14	0	0
T49	0	10	0	0
T110	0	32	0	0
T146	0	28	0	0
T171	0	18	0	0
T193	0	17	0	0
T266	0	28	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	1934	0	0
T1	100753	10	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	27	0	0
T33	0	27	0	0
T34	0	12	0	0
T49	0	4	0	0
T110	0	33	0	0
T146	0	26	0	0
T171	0	31	0	0
T193	0	19	0	0
T266	0	40	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	1853	0	0
T1	100753	13	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	21	0	0
T33	0	31	0	0
T34	0	5	0	0
T49	0	14	0	0
T110	0	30	0	0
T146	0	20	0	0
T171	0	29	0	0
T193	0	12	0	0
T266	0	39	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	1884	0	0
T1	100753	3	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	23	0	0
T33	0	27	0	0
T34	0	19	0	0
T49	0	19	0	0
T110	0	21	0	0
T146	0	20	0	0
T171	0	24	0	0
T193	0	19	0	0
T266	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5570	0	0
T1	100753	82	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	31	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	30	0	0
T33	0	42	0	0
T34	0	18	0	0
T49	0	18	0	0
T64	0	65	0	0
T217	0	95	0	0
T228	0	81	0	0
T265	0	27	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5639	0	0
T1	100753	66	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	28	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	26	0	0
T33	0	33	0	0
T34	0	17	0	0
T49	0	18	0	0
T64	0	61	0	0
T217	0	62	0	0
T228	0	63	0	0
T265	0	30	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5945	0	0
T1	100753	77	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	29	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	5	0	0
T33	0	23	0	0
T34	0	11	0	0
T49	0	7	0	0
T64	0	66	0	0
T217	0	107	0	0
T228	0	58	0	0
T265	0	37	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5987	0	0
T1	100753	91	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	33	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	11	0	0
T33	0	40	0	0
T34	0	19	0	0
T49	0	4	0	0
T64	0	79	0	0
T217	0	83	0	0
T228	0	74	0	0
T265	0	25	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5754	0	0
T1	100753	62	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	31	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	15	0	0
T33	0	34	0	0
T34	0	21	0	0
T49	0	6	0	0
T64	0	58	0	0
T217	0	110	0	0
T228	0	84	0	0
T265	0	36	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5643	0	0
T1	100753	91	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	29	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	25	0	0
T33	0	31	0	0
T34	0	21	0	0
T49	0	15	0	0
T64	0	104	0	0
T217	0	68	0	0
T228	0	64	0	0
T265	0	44	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5608	0	0
T1	100753	75	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	33	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	24	0	0
T33	0	47	0	0
T34	0	29	0	0
T49	0	12	0	0
T64	0	67	0	0
T217	0	108	0	0
T228	0	65	0	0
T265	0	26	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5660	0	0
T1	100753	71	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	38	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	22	0	0
T33	0	35	0	0
T34	0	22	0	0
T64	0	79	0	0
T110	0	46	0	0
T217	0	93	0	0
T228	0	73	0	0
T265	0	23	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2914	0	0
T1	100753	38	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T7	0	9	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	41	0	0
T33	0	22	0	0
T34	0	21	0	0
T49	0	12	0	0
T64	0	50	0	0
T123	0	4	0	0
T217	0	55	0	0
T228	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2762	0	0
T1	100753	63	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	27	0	0
T33	0	62	0	0
T34	0	10	0	0
T49	0	9	0	0
T110	0	42	0	0
T146	0	22	0	0
T171	0	22	0	0
T193	0	22	0	0
T266	0	40	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5050	0	0
T1	100753	17	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	34	0	0
T33	0	43	0	0
T34	0	9	0	0
T36	0	1	0	0
T37	0	5	0	0
T49	0	5	0	0
T110	0	33	0	0
T193	0	21	0	0
T267	0	6	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2047	0	0
T1	100753	22	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	22	0	0
T33	0	36	0	0
T34	0	3	0	0
T49	0	18	0	0
T110	0	52	0	0
T146	0	25	0	0
T171	0	29	0	0
T193	0	9	0	0
T266	0	23	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	7198	0	0
T1	100753	162	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	79	0	0
T14	57962	0	0	0
T15	234150	67	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	15	0	0
T33	0	36	0	0
T34	0	41	0	0
T49	0	7	0	0
T64	0	58	0	0
T268	0	84	0	0
T269	0	66	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	7712	0	0
T1	100753	1	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	75	0	0
T33	0	25	0	0
T34	0	112	0	0
T49	0	6	0	0
T101	0	76	0	0
T110	0	108	0	0
T193	0	221	0	0
T270	0	76	0	0
T271	0	42	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	5887	0	0
T1	100753	10	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	77	0	0
T33	0	41	0	0
T34	0	156	0	0
T49	0	10	0	0
T101	0	67	0	0
T110	0	87	0	0
T193	0	234	0	0
T270	0	49	0	0
T271	0	80	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	6312	0	0
T1	100753	4	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	99	0	0
T33	0	27	0	0
T34	0	117	0	0
T49	0	12	0	0
T101	0	74	0	0
T110	0	121	0	0
T193	0	241	0	0
T270	0	55	0	0
T271	0	54	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2275	0	0
T1	100753	8	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	0	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	28	0	0
T33	0	26	0	0
T34	0	19	0	0
T49	0	8	0	0
T110	0	14	0	0
T146	0	30	0	0
T171	0	33	0	0
T193	0	15	0	0
T266	0	35	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2014	0	0
T1	100753	22	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	5	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	22	0	0
T33	0	45	0	0
T34	0	23	0	0
T49	0	17	0	0
T60	0	4	0	0
T62	0	5	0	0
T72	0	9	0	0
T272	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2075	0	0
T1	100753	13	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	5	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	16	0	0
T33	0	35	0	0
T49	0	15	0	0
T60	0	5	0	0
T62	0	15	0	0
T72	0	4	0	0
T126	0	16	0	0
T272	0	22	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	1970	0	0
T1	100753	22	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	1	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	28	0	0
T33	0	8	0	0
T34	0	20	0	0
T49	0	14	0	0
T60	0	4	0	0
T62	0	1	0	0
T72	0	11	0	0
T272	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270635435	2117	0	0
T1	100753	16	0	0
T2	166829	0	0	0
T3	846406	0	0	0
T6	175949	0	0	0
T13	94342	0	0	0
T14	57962	0	0	0
T15	234150	0	0	0
T16	105099	12	0	0
T17	63057	0	0	0
T18	173663	0	0	0
T25	0	28	0	0
T33	0	34	0	0
T34	0	14	0	0
T49	0	12	0	0
T60	0	5	0	0
T62	0	2	0	0
T72	0	3	0	0
T272	0	20	0	0