Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_intr_status_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_intr_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	0	28	100.00

Variables for Group Instance sysrst_ctrl_key_intr_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_h2l	2	0	2	100.00	100	1	1	2
cp_ac_present_l2h	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_h2l	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_l2h	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_h2l	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_l2h	2	0	2	100.00	100	1	1	2
cp_key0_in_h2l	2	0	2	100.00	100	1	1	2
cp_key0_in_l2h	2	0	2	100.00	100	1	1	2
cp_key1_in_h2l	2	0	2	100.00	100	1	1	2
cp_key1_in_l2h	2	0	2	100.00	100	1	1	2
cp_key2_in_h2l	2	0	2	100.00	100	1	1	2
cp_key2_in_l2h	2	0	2	100.00	100	1	1	2
cp_pwrb_h2l	2	0	2	100.00	100	1	1	2
cp_pwrb_l2h	2	0	2	100.00	100	1	1	2

Summary for Variable cp_ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T1

2

T3

4

T7

10

auto[1]

127

1

T1

1

T3

3

T8

1

---

Summary for Variable cp_ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T1

1

T3

3

T7

10

auto[1]

162

1

T1

2

T3

4

T8

7

---

Summary for Variable cp_ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T1

3

T3

7

T7

10

auto[1]

137

1

T8

3

T46

2

T45

1

---

Summary for Variable cp_ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T1

2

T3

7

T7

10

auto[1]

105

1

T1

1

T8

3

T11

1

---

Summary for Variable cp_flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T1

3

T3

7

T7

10

auto[1]

136

1

T8

5

T11

2

T13

3

---

Summary for Variable cp_flash_wp_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T1

3

T3

7

T7

10

auto[1]

89

1

T8

1

T11

2

T27

2

---

Summary for Variable cp_key0_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T1

2

T3

7

T7

10

auto[1]

105

1

T1

1

T11

3

T27

2

---

Summary for Variable cp_key0_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T1

1

T3

3

T7

10

auto[1]

122

1

T1

2

T3

4

T8

5

---

Summary for Variable cp_key1_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T1

3

T3

5

T7

10

auto[1]

137

1

T3

2

T8

6

T13

1

---

Summary for Variable cp_key1_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T1

1

T3

7

T7

10

auto[1]

155

1

T1

2

T8

7

T11

2

---

Summary for Variable cp_key2_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T1

2

T3

6

T7

10

auto[1]

116

1

T1

1

T3

1

T8

2

---

Summary for Variable cp_key2_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T1

1

T3

5

T7

10

auto[1]

134

1

T1

2

T3

2

T8

2

---

Summary for Variable cp_pwrb_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T1

2

T3

6

T7

10

auto[1]

119

1

T1

1

T3

1

T8

3

---

Summary for Variable cp_pwrb_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T1

1

T3

7

T7

10

auto[1]

142

1

T1

2

T8

10

T11

2