Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.59	86.59	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	86.59	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.59	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	11	51	82.26

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	11	20	64.52	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1757

1

T2

3

T8

3

T10

27

auto[1]

623

1

T14

5

T2

9

T15

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1798

1

T14

5

T2

4

T8

1

auto[1]

582

1

T2

8

T15

2

T50

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1762

1

T2

9

T50

2

T9

2

auto[1]

618

1

T14

5

T2

3

T15

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1732

1

T14

5

T2

8

T15

2

auto[1]

648

1

T2

4

T50

2

T8

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2243

1

T14

5

T2

12

T15

2

auto[1]

137

1

T81

10

T106

2

T262

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2223

1

T14

5

T2

12

T15

2

auto[1]

157

1

T10

6

T38

13

T80

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2199

1

T14

5

T2

12

T15

2

auto[1]

181

1

T106

4

T107

1

T262

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2230

1

T14

5

T2

12

T15

2

auto[1]

150

1

T10

21

T38

4

T49

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2207

1

T14

5

T2

12

T15

2

auto[1]

173

1

T10

6

T38

6

T40

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1797

1

T14

3

T2

8

T8

1

auto[1]

583

1

T14

2

T2

4

T15

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	11	20	64.52	11
Automatically Generated Cross Bins	31	11	20	64.52	11
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	951	1			T14	5		T2	4		T15	2
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	66	1			T81	10		T263	7		T271	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	55	1			T38	3		T40	3		T107	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T106	2		T361	3		T362	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	62	1			T10	5		T49	1		T363	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T194	8		T181	8		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	12	1			T10	5		T359	2		T364	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T365	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	56	1			T107	1		T276	5		T312	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	20	1			T263	4		T270	6		T357	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	56	1			T263	9		T357	22		T366	8
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	13	1			T106	4		T262	2		T367	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	51	1			T38	7		T80	1		T276	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	3	1			T362	3		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	19	1			T264	4		T360	3		T362	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T181	2		T368	1		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	24	1			T10	2		T38	4		T40	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	13	1			T276	4		T350	9		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T262	1		T368	3		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T364	3		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

99

1

T38

7

T41

13

T264

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

93

1

T262

2

T267

10

T357

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

50

1

T64

2

T106

4

T109

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

164

1

T41

11

T262

1

T263

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

60

1

T63

7

T247

7

T369

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T107

1

T120

2

T353

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T39

1

T370

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

92

1

T10

2

T247

9

T263

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

70

1

T14

3

T12

5

T247

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T38

4

T63

6

T81

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T14

2

T10

5

T80

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

66

1

T64

8

T54

3

T109

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T8

1

T39

1

T40

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T2

3

T271

1

T90

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T9

2

T109

1

T370

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

87

1

T106

2

T109

1

T371

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

40

1

T49

1

T109

4

T175

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T312

1

T113

3

T155

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T264

3

T164

2

T372

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T41

3

T263

4

T109

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T9

2

T276

5

T140

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T373

4

T90

2

T120

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T50

2

T266

2

T268

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

78

1

T10

5

T12

14

T81

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T38

3

T109

3

T164

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T273

3

T361

4

T356

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T15

2

T8

1

T41

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T107

1

T269

1

T351

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T109

3

T266

1

T267

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T13

2

T374

4

T375

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T186

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded