Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T4

11

T21

10

T59

9

auto[1]

1134

1

T4

9

T21

10

T59

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T4

5

T21

6

T59

4

from_0to1

534

1

T4

6

T21

6

T59

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T4

9

T21

10

T59

11

auto[1]

1073

1

T4

11

T21

10

T59

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T4

14

T21

8

T59

9

auto[1]

1074

1

T4

6

T21

12

T59

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T59

1

T13

2

T324

2

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T4

2

T21

1

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T4

1

T8

1

T13

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T324

1

T115

1

T318

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T8

1

T42

2

T318

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T21

3

T8

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T4

2

T21

2

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T59

1

T8

1

T13

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T21

2

T8

3

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T4

2

T73

1

T13

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T59

2

T73

3

T324

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T21

3

T73

1

T13

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T4

1

T73

1

T13

2

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T59

1

T73

1

T315

1

auto[1]

from_0to1

auto[1]

auto[0]

88

1

T4

2

T59

2

T13

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T4

1

T21

1

T8

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T4

15

T21

5

T59

10

auto[1]

1113

1

T4

5

T21

15

T59

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T4

4

T21

4

T59

4

from_0to1

527

1

T4

5

T21

3

T59

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T4

8

T21

14

T59

10

auto[1]

1178

1

T4

12

T21

6

T59

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T4

10

T21

12

T59

8

auto[1]

1083

1

T4

10

T21

8

T59

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T4

1

T21

1

T13

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T4

1

T59

1

T13

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T4

1

T73

2

T13

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T59

1

T73

2

T324

2

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T4

1

T315

1

T115

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T59

2

T324

3

T315

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T4

2

T324

1

T315

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T4

2

T73

1

T42

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T59

1

T13

2

T42

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T4

1

T21

1

T59

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T21

1

T8

2

T13

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T21

1

T73

1

T324

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T21

2

T8

1

T73

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T8

1

T13

1

T115

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T59

2

T8

1

T13

3

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T21

1

T59

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T4

6

T21

11

T59

10

auto[1]

1106

1

T4

14

T21

9

T59

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T4

5

T21

4

T59

6

from_0to1

531

1

T4

5

T21

5

T59

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T4

9

T21

10

T59

8

auto[1]

1079

1

T4

11

T21

10

T59

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T4

13

T21

15

T59

9

auto[1]

1147

1

T4

7

T21

5

T59

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T4

1

T59

1

T73

1

auto[0]

from_1to0

auto[0]

auto[1]

86

1

T21

1

T59

1

T13

5

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T4

1

T315

1

T122

3

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T8

2

T13

1

T320

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T21

1

T13

1

T122

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T21

1

T59

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T4

1

T59

2

T13

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T59

1

T13

1

T324

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T21

2

T59

1

T13

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T4

1

T8

2

T42

2

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T4

1

T21

1

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T4

1

T59

3

T324

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T4

3

T59

1

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T4

1

T8

2

T73

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T21

3

T59

1

T8

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T59

1

T8

3

T13

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T4

11

T21

7

T59

7

auto[1]

1103

1

T4

9

T21

13

T59

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T4

5

T21

6

T59

6

from_0to1

541

1

T4

5

T21

7

T59

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T4

11

T21

10

T59

9

auto[1]

1138

1

T4

9

T21

10

T59

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T4

13

T21

10

T59

12

auto[1]

1109

1

T4

7

T21

10

T59

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T59

1

T8

1

T13

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T4

1

T73

1

T13

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T4

2

T21

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T59

1

T315

2

T115

1

auto[0]

from_0to1

auto[0]

auto[0]

80

1

T4

1

T21

2

T59

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T4

2

T21

2

T13

3

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T8

1

T324

1

T42

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T59

2

T73

1

T324

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T4

1

T21

1

T315

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T21

1

T73

2

T13

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T4

1

T59

2

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T21

3

T59

1

T8

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T4

1

T21

2

T59

2

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

1

T8

2

T73

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T21

1

T73

1

T13

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T59

1

T8

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T4

14

T21

10

T59

9

auto[1]

1099

1

T4

6

T21

10

T59

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T4

4

T21

4

T59

6

from_0to1

526

1

T4

5

T21

3

T59

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T4

14

T21

12

T59

10

auto[1]

1084

1

T4

6

T21

8

T59

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T4

11

T21

13

T59

17

auto[1]

1063

1

T4

9

T21

7

T59

3

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T4

1

T73

2

T13

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T4

1

T21

1

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T21

1

T59

2

T73

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T8

1

T13

2

T324

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T4

1

T21

1

T59

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T4

1

T73

1

T13

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T324

2

T42

2

T122

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T4

1

T8

1

T13

3

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T21

1

T13

1

T115

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T4

2

T8

1

T42

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T59

4

T8

1

T324

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T21

1

T73

2

T13

3

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T4

1

T59

2

T324

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T59

1

T13

4

T324

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T4

1

T59

1

T8

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T21

2

T8

1

T13

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T4

9

T21

14

T59

10

auto[1]

1107

1

T4

11

T21

6

T59

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T4

4

T21

4

T59

6

from_0to1

538

1

T4

3

T21

5

T59

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T4

10

T21

11

T59

9

auto[1]

1113

1

T4

10

T21

9

T59

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T4

11

T21

14

T59

10

auto[1]

1094

1

T4

9

T21

6

T59

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T4

1

T59

1

T13

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T4

1

T21

2

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T4

1

T21

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T59

1

T73

1

T122

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T4

1

T21

3

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T21

1

T59

1

T8

3

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T21

1

T13

2

T42

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T13

2

T42

1

T122

2

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T21

1

T8

1

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T4

1

T59

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T59

1

T8

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T13

3

T324

2

T315

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T4

1

T59

1

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T59

2

T13

3

T324

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T4

1

T59

2

T8

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T8

1

T73

1

T42

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T4

6

T21

12

T59

11

auto[1]

1098

1

T4

14

T21

8

T59

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T4

3

T21

7

T59

6

from_0to1

544

1

T4

2

T21

7

T59

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T4

13

T21

11

T59

13

auto[1]

1101

1

T4

7

T21

9

T59

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T4

8

T21

11

T59

13

auto[1]

1093

1

T4

12

T21

9

T59

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T4

1

T21

2

T59

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T59

2

T8

1

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T13

2

T315

1

T42

3

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T4

1

T21

1

T42

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T21

2

T59

1

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T59

1

T8

1

T13

4

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T73

2

T324

1

T315

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T21

2

T59

1

T315

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T4

1

T21

3

T59

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T13

3

T315

1

T42

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T21

1

T59

1

T73

3

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T59

1

T8

1

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

80

1

T4

2

T21

1

T59

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T21

1

T73

2

T13

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T59

1

T73

1

T13

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T21

1

T13

1

T324

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T4

11

T21

10

T59

12

auto[1]

1110

1

T4

9

T21

10

T59

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T4

6

T21

5

T59

7

from_0to1

527

1

T4

7

T21

4

T59

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T4

13

T21

8

T59

6

auto[1]

1110

1

T4

7

T21

12

T59

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T4

6

T21

10

T59

10

auto[1]

1097

1

T4

14

T21

10

T59

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T4

2

T59

2

T73

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T21

1

T8

1

T324

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T21

1

T59

1

T73

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T4

2

T21

1

T59

2

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T324

1

T315

1

T42

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T4

1

T13

3

T320

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T4

1

T21

1

T59

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T4

2

T59

2

T8

3

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T59

2

T8

1

T322

1

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T4

2

T8

2

T73

2

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T21

2

T324

1

T315

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T8

1

T13

1

T42

2

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T21

1

T8

1

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

3

T59

1

T13

1

auto[1]

from_0to1

auto[1]

auto[0]

82

1

T21

1

T8

1

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T21

1

T59

2

T73

1