Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120120

1

T4

55

T5

23

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144998	1			T4	62		T5	2		T6	3
values[0x0]	65897	1			T4	33		T5	31		T21	29
values[0x1]	67451	1			T4	28		T5	30		T6	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128172	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150174

1

T4

67

T5

29

T6

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1546	1			T4	1		T22	2		T15	1
valid_sources[0x01]	1227	1			T22	1		T16	1		T18	3
valid_sources[0x02]	887	1			T22	3		T15	1		T18	2
valid_sources[0x03]	930	1			T22	2		T15	1		T18	1
valid_sources[0x04]	1720	1			T4	1		T22	3		T15	3
valid_sources[0x05]	1965	1			T4	1		T22	5		T15	1
valid_sources[0x06]	1015	1			T4	1		T22	5		T15	1
valid_sources[0x07]	1001	1			T4	1		T5	3		T15	1
valid_sources[0x08]	1768	1			T22	5		T15	2		T16	1
valid_sources[0x09]	1698	1			T4	2		T22	1		T15	2
valid_sources[0x0a]	744	1			T22	4		T15	2		T50	12
valid_sources[0x0b]	737	1			T22	4		T18	9		T30	3
valid_sources[0x0c]	1366	1			T4	2		T22	3		T15	1
valid_sources[0x0d]	946	1			T22	4		T18	2		T30	4
valid_sources[0x0e]	772	1			T22	4		T15	3		T18	1
valid_sources[0x0f]	1058	1			T4	2		T22	3		T15	2
valid_sources[0x10]	1098	1			T5	5		T22	1		T18	2
valid_sources[0x11]	1717	1			T22	3		T15	2		T30	4
valid_sources[0x12]	2389	1			T22	4		T15	3		T18	1
valid_sources[0x13]	1249	1			T22	3		T15	1		T16	1
valid_sources[0x14]	856	1			T22	4		T15	1		T18	2
valid_sources[0x15]	1086	1			T4	1		T22	5		T15	2
valid_sources[0x16]	1134	1			T22	1		T15	2		T18	3
valid_sources[0x17]	962	1			T22	2		T15	1		T16	1
valid_sources[0x18]	961	1			T4	1		T22	2		T1	10
valid_sources[0x19]	1620	1			T16	2		T18	5		T30	4
valid_sources[0x1a]	1350	1			T4	1		T22	1		T15	5
valid_sources[0x1b]	798	1			T22	6		T15	1		T18	1
valid_sources[0x1c]	896	1			T5	2		T22	1		T15	1
valid_sources[0x1d]	923	1			T5	2		T22	7		T18	1
valid_sources[0x1e]	812	1			T4	1		T22	1		T15	2
valid_sources[0x1f]	822	1			T22	4		T15	2		T18	5
valid_sources[0x20]	846	1			T4	1		T22	9		T18	3
valid_sources[0x21]	735	1			T22	3		T15	2		T18	1
valid_sources[0x22]	803	1			T22	3		T15	3		T16	1
valid_sources[0x23]	961	1			T22	4		T15	1		T18	2
valid_sources[0x24]	1102	1			T22	4		T3	2		T18	1
valid_sources[0x25]	1084	1			T4	1		T22	7		T16	1
valid_sources[0x26]	748	1			T4	1		T22	2		T16	1
valid_sources[0x27]	821	1			T5	1		T22	3		T15	2
valid_sources[0x28]	1093	1			T22	7		T15	2		T18	1
valid_sources[0x29]	994	1			T22	3		T15	4		T18	1
valid_sources[0x2a]	954	1			T22	6		T15	3		T18	3
valid_sources[0x2b]	1091	1			T22	7		T16	2		T30	3
valid_sources[0x2c]	1003	1			T22	9		T15	2		T59	2
valid_sources[0x2d]	828	1			T22	3		T15	4		T30	4
valid_sources[0x2e]	692	1			T15	3		T30	3		T9	1
valid_sources[0x2f]	1097	1			T22	4		T15	1		T18	1
valid_sources[0x30]	1061	1			T22	1		T15	2		T18	1
valid_sources[0x31]	2454	1			T4	1		T22	5		T15	1
valid_sources[0x32]	713	1			T22	8		T15	4		T30	6
valid_sources[0x33]	1033	1			T22	1		T15	1		T16	1
valid_sources[0x34]	2167	1			T22	2		T15	3		T18	1
valid_sources[0x35]	1065	1			T22	3		T15	1		T30	1
valid_sources[0x36]	1198	1			T4	1		T22	6		T15	2
valid_sources[0x37]	891	1			T4	1		T22	1		T3	1
valid_sources[0x38]	857	1			T22	6		T15	1		T18	9
valid_sources[0x39]	1613	1			T4	1		T5	2		T22	9
valid_sources[0x3a]	980	1			T22	3		T30	2		T9	3
valid_sources[0x3b]	855	1			T22	4		T15	1		T17	9
valid_sources[0x3c]	842	1			T4	1		T22	3		T15	2
valid_sources[0x3d]	893	1			T4	1		T5	1		T22	6
valid_sources[0x3e]	906	1			T22	1		T15	2		T29	3
valid_sources[0x3f]	2191	1			T4	1		T22	4		T15	3
valid_sources[0x40]	976	1			T4	2		T5	2		T22	4
valid_sources[0x41]	739	1			T22	7		T30	3		T9	3
valid_sources[0x42]	1721	1			T22	3		T16	1		T18	4
valid_sources[0x43]	1128	1			T4	1		T22	2		T15	1
valid_sources[0x44]	842	1			T22	5		T15	2		T18	4
valid_sources[0x45]	1562	1			T22	4		T15	2		T18	4
valid_sources[0x46]	844	1			T4	3		T21	122		T22	1
valid_sources[0x47]	1158	1			T4	1		T22	3		T15	3
valid_sources[0x48]	812	1			T4	1		T15	4		T30	3
valid_sources[0x49]	1152	1			T15	2		T30	2		T7	1
valid_sources[0x4a]	936	1			T22	2		T15	1		T30	2
valid_sources[0x4b]	1269	1			T4	1		T22	2		T15	2
valid_sources[0x4c]	906	1			T22	3		T15	2		T16	2
valid_sources[0x4d]	1045	1			T15	1		T18	2		T19	63
valid_sources[0x4e]	708	1			T22	8		T15	3		T18	2
valid_sources[0x4f]	784	1			T4	2		T22	4		T15	1
valid_sources[0x50]	846	1			T4	1		T5	1		T22	6
valid_sources[0x51]	826	1			T22	2		T15	2		T18	10
valid_sources[0x52]	1426	1			T22	2		T15	1		T18	2
valid_sources[0x53]	1004	1			T4	2		T5	1		T22	1
valid_sources[0x54]	1233	1			T22	3		T15	1		T16	1
valid_sources[0x55]	858	1			T4	4		T5	1		T22	5
valid_sources[0x56]	1764	1			T22	5		T15	1		T18	1
valid_sources[0x57]	822	1			T4	1		T22	3		T15	2
valid_sources[0x58]	1014	1			T5	2		T22	6		T15	3
valid_sources[0x59]	1190	1			T22	5		T16	2		T30	8
valid_sources[0x5a]	818	1			T5	3		T22	3		T15	1
valid_sources[0x5b]	1328	1			T4	2		T22	2		T15	3
valid_sources[0x5c]	1085	1			T22	6		T15	1		T18	1
valid_sources[0x5d]	790	1			T4	1		T15	4		T59	2
valid_sources[0x5e]	1094	1			T4	1		T22	4		T15	3
valid_sources[0x5f]	993	1			T5	4		T22	2		T30	2
valid_sources[0x60]	1035	1			T22	1		T15	1		T18	1
valid_sources[0x61]	962	1			T22	4		T15	1		T16	1
valid_sources[0x62]	1363	1			T22	2		T15	3		T18	1
valid_sources[0x63]	1238	1			T4	1		T22	2		T16	1
valid_sources[0x64]	743	1			T22	4		T15	3		T30	4
valid_sources[0x65]	1003	1			T5	1		T22	4		T15	1
valid_sources[0x66]	985	1			T4	1		T5	1		T22	3
valid_sources[0x67]	929	1			T22	5		T15	2		T9	1
valid_sources[0x68]	810	1			T4	1		T22	3		T15	2
valid_sources[0x69]	825	1			T4	2		T5	1		T22	5
valid_sources[0x6a]	1187	1			T5	1		T22	1		T15	4
valid_sources[0x6b]	778	1			T22	3		T18	2		T9	3
valid_sources[0x6c]	775	1			T4	1		T22	1		T15	1
valid_sources[0x6d]	945	1			T4	1		T22	2		T16	1
valid_sources[0x6e]	1192	1			T22	3		T15	1		T30	5
valid_sources[0x6f]	840	1			T4	1		T5	1		T22	3
valid_sources[0x70]	1551	1			T22	6		T18	1		T30	1
valid_sources[0x71]	822	1			T4	1		T5	1		T22	4
valid_sources[0x72]	1323	1			T4	1		T22	5		T18	1
valid_sources[0x73]	821	1			T4	1		T22	3		T15	6
valid_sources[0x74]	891	1			T5	1		T22	4		T15	2
valid_sources[0x75]	793	1			T5	2		T22	2		T16	1
valid_sources[0x76]	1003	1			T22	3		T15	2		T18	2
valid_sources[0x77]	2130	1			T5	1		T22	4		T15	5
valid_sources[0x78]	839	1			T15	1		T30	2		T7	6
valid_sources[0x79]	919	1			T22	10		T15	2		T18	2
valid_sources[0x7a]	1471	1			T4	1		T5	2		T22	1
valid_sources[0x7b]	1976	1			T22	3		T30	1		T7	3
valid_sources[0x7c]	1146	1			T4	2		T22	6		T15	2
valid_sources[0x7d]	1645	1			T22	2		T15	1		T30	3
valid_sources[0x7e]	1888	1			T4	1		T22	2		T15	4
valid_sources[0x7f]	1358	1			T22	1		T15	1		T30	5
valid_sources[0x80]	776	1			T22	2		T3	1		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65534

1

T4

36

T6

2

T21

33

values[0x0]

all_enables

biggest_size

31848

1

T4

14

T5

15

T21

10

values[0x1]

all_enables

biggest_size

22738

1

T4

5

T5

8

T6

1