Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T27,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T27,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T46
0	1	Covered	T8,T27,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T46
1	-	Covered	T8,T27,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T46
DetectSt	168	Covered	T8,T27,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T27,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T46
DebounceSt->IdleSt	163	Covered	T87,T88
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T27,T46
IdleSt->DebounceSt	148	Covered	T8,T27,T46
StableSt->IdleSt	206	Covered	T8,T27,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T27,T46
0	1	Covered	T8,T27,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T46
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T42
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	80	0	0
CntIncr_A	7461812	102980	0	0
CntNoWrap_A	7461812	6763435	0	0
DetectStDropOut_A	7461812	0	0	0
DetectedOut_A	7461812	58790	0	0
DetectedPulseOut_A	7461812	39	0	0
DisabledIdleSt_A	7461812	6371480	0	0
DisabledNoDetection_A	7461812	6373876	0	0
EnterDebounceSt_A	7461812	41	0	0
EnterDetectSt_A	7461812	39	0	0
EnterStableSt_A	7461812	39	0	0
PulseIsPulse_A	7461812	39	0	0
StayInStableSt	7461812	58734	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	80	0	0
T8	26040	4	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	4	0	0
T39	0	2	0	0
T42	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T87	0	1	0	0
T133	0	2	0	0
T175	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	102980	0	0
T8	26040	200	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	54	0	0
T39	0	57	0	0
T42	0	93	0	0
T46	0	52	0	0
T47	0	61	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T87	0	43	0	0
T133	0	87	0	0
T175	0	57360	0	0
T187	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763435	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	58790	0	0
T8	26040	103	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	130	0	0
T39	0	42	0	0
T42	0	40	0	0
T46	0	36	0	0
T47	0	117	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	131	0	0
T154	0	104	0	0
T175	0	38	0	0
T187	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	39	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6371480	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6373876	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	41	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T87	0	1	0	0
T133	0	1	0	0
T175	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	39	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	39	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	39	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	58734	0	0
T8	26040	100	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	127	0	0
T39	0	40	0	0
T42	0	39	0	0
T46	0	34	0	0
T47	0	116	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	130	0	0
T154	0	103	0	0
T175	0	36	0	0
T187	0	141	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	22	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T46,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T46,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T46,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T46,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T46,T47
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T46,T47
0	1	Covered	T46,T47,T48
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T46,T47
1	-	Covered	T46,T47,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T46,T45
DetectSt	168	Covered	T8,T46,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T46,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T46,T47
DebounceSt->IdleSt	163	Covered	T8,T45,T87
DetectSt->IdleSt	186	Covered	T189
DetectSt->StableSt	191	Covered	T8,T46,T47
IdleSt->DebounceSt	148	Covered	T8,T46,T45
StableSt->IdleSt	206	Covered	T8,T46,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T46,T45
0	1	Covered	T8,T46,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T46,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T46,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T45,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T46,T45
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T8,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T47,T48
StableSt	-	-	-	-	-	-	0	Covered	T8,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	133	0	0
CntIncr_A	7461812	18623	0	0
CntNoWrap_A	7461812	6763382	0	0
DetectStDropOut_A	7461812	1	0	0
DetectedOut_A	7461812	76070	0	0
DetectedPulseOut_A	7461812	63	0	0
DisabledIdleSt_A	7461812	6645794	0	0
DisabledNoDetection_A	7461812	6648188	0	0
EnterDebounceSt_A	7461812	69	0	0
EnterDetectSt_A	7461812	64	0	0
EnterStableSt_A	7461812	63	0	0
PulseIsPulse_A	7461812	63	0	0
StayInStableSt	7461812	75976	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	3153	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	133	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	2	0	0
T176	0	2	0	0
T177	0	4	0	0
T191	0	2	0	0
T192	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	18623	0	0
T8	26040	108	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T45	0	45	0	0
T46	0	52	0	0
T47	0	122	0	0
T48	0	21	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	72	0	0
T176	0	52	0	0
T177	0	46	0	0
T191	0	74	0	0
T192	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763382	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1	0	0
T132	1365	0	0	0
T189	817	1	0	0
T193	653	0	0	0
T194	21602	0	0	0
T195	445	0	0	0
T196	35619	0	0	0
T197	673	0	0	0
T198	502	0	0	0
T199	1882	0	0	0
T200	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	76070	0	0
T8	26040	41	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	5	0	0
T47	0	154	0	0
T48	0	64	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	452	0	0
T176	0	17	0	0
T177	0	28	0	0
T191	0	138	0	0
T192	0	133	0	0
T201	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	63	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0
T192	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6645794	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6648188	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	69	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0
T192	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0
T192	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	63	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0
T192	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	63	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0
T192	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	75976	0	0
T8	26040	39	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	4	0	0
T47	0	151	0	0
T48	0	63	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	450	0	0
T176	0	16	0	0
T177	0	26	0	0
T191	0	136	0	0
T192	0	131	0	0
T201	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3153	0	0
T1	635	1	0	0
T2	16315	3	0	0
T3	693	2	0	0
T4	503	5	0	0
T5	524	6	0	0
T6	490	2	0	0
T14	12958	0	0	0
T16	0	5	0	0
T19	0	5	0	0
T21	504	5	0	0
T22	6629	0	0	0
T23	494	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	32	0	0
T28	792	0	0	0
T42	10472	0	0	0
T46	2412	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	10167	0	0	0
T57	717	0	0	0
T58	113683	0	0	0
T95	0	2	0	0
T115	4398	0	0	0
T122	502	0	0	0
T123	615	0	0	0
T152	0	2	0	0
T153	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T187	0	1	0	0
T202	0	2	0	0
T203	415	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T39,T153
1	0	Covered	T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T3,T8,T27
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T3,T8,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T155,T88,T204
DetectSt->IdleSt	186	Covered	T39,T87,T153
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T3,T8,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T155,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T39,T87,T153
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T27
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	153	0	0
CntIncr_A	7461812	4172	0	0
CntNoWrap_A	7461812	6763362	0	0
DetectStDropOut_A	7461812	2	0	0
DetectedOut_A	7461812	6038	0	0
DetectedPulseOut_A	7461812	72	0	0
DisabledIdleSt_A	7461812	6585202	0	0
DisabledNoDetection_A	7461812	6587586	0	0
EnterDebounceSt_A	7461812	78	0	0
EnterDetectSt_A	7461812	75	0	0
EnterStableSt_A	7461812	72	0	0
PulseIsPulse_A	7461812	72	0	0
StayInStableSt	7461812	5937	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	153	0	0
T1	635	2	0	0
T2	16315	0	0	0
T3	693	4	0	0
T8	0	6	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	6	0	0
T39	0	2	0	0
T43	0	2	0	0
T174	0	4	0	0
T178	0	2	0	0
T201	0	2	0	0
T205	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	4172	0	0
T1	635	93	0	0
T2	16315	0	0	0
T3	693	70	0	0
T8	0	293	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	115	0	0
T39	0	57	0	0
T43	0	98	0	0
T174	0	144	0	0
T178	0	17	0	0
T201	0	13	0	0
T205	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763362	0	0
T1	635	232	0	0
T2	16315	15073	0	0
T3	693	288	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	2	0	0
T39	12869	1	0	0
T77	494	0	0	0
T78	494	0	0	0
T80	12166	0	0	0
T153	0	1	0	0
T206	644	0	0	0
T207	526	0	0	0
T208	402	0	0	0
T209	403	0	0	0
T210	527	0	0	0
T211	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6038	0	0
T1	635	132	0	0
T2	16315	0	0	0
T3	693	148	0	0
T8	0	310	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	178	0	0
T43	0	91	0	0
T95	0	56	0	0
T174	0	32	0	0
T178	0	70	0	0
T201	0	62	0	0
T205	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T43	0	1	0	0
T95	0	2	0	0
T174	0	2	0	0
T178	0	1	0	0
T201	0	1	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6585202	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6587586	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	78	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T39	0	1	0	0
T43	0	1	0	0
T174	0	2	0	0
T178	0	1	0	0
T201	0	1	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	75	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T39	0	1	0	0
T43	0	1	0	0
T174	0	2	0	0
T178	0	1	0	0
T201	0	1	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T43	0	1	0	0
T95	0	2	0	0
T174	0	2	0	0
T178	0	1	0	0
T201	0	1	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T43	0	1	0	0
T95	0	2	0	0
T174	0	2	0	0
T178	0	1	0	0
T201	0	1	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5937	0	0
T1	635	130	0	0
T2	16315	0	0	0
T3	693	145	0	0
T8	0	305	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	175	0	0
T43	0	90	0	0
T95	0	54	0	0
T174	0	30	0	0
T178	0	68	0	0
T201	0	60	0	0
T205	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	43	0	0
T3	693	1	0	0
T8	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T29	34371	0	0	0
T43	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	2	0	0
T153	0	1	0	0
T156	0	2	0	0
T174	0	2	0	0
T187	0	2	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T21
1	1	Covered	T3,T11,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T45
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T45
0	1	Covered	T3,T45,T213
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T45
1	-	Covered	T3,T45,T213

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T42
DetectSt	168	Covered	T3,T11,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T45
DebounceSt->IdleSt	163	Covered	T42,T45,T87
DetectSt->IdleSt	186	Covered	T189
DetectSt->StableSt	191	Covered	T3,T11,T45
IdleSt->DebounceSt	148	Covered	T3,T11,T42
StableSt->IdleSt	206	Covered	T3,T45,T213

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T42
0	1	Covered	T3,T11,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T42
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T45,T213
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	94	0	0
CntIncr_A	7461812	59823	0	0
CntNoWrap_A	7461812	6763421	0	0
DetectStDropOut_A	7461812	1	0	0
DetectedOut_A	7461812	64545	0	0
DetectedPulseOut_A	7461812	44	0	0
DisabledIdleSt_A	7461812	6366581	0	0
DisabledNoDetection_A	7461812	6368964	0	0
EnterDebounceSt_A	7461812	49	0	0
EnterDetectSt_A	7461812	45	0	0
EnterStableSt_A	7461812	44	0	0
PulseIsPulse_A	7461812	44	0	0
StayInStableSt	7461812	64480	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	6641	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	94	0	0
T3	693	2	0	0
T11	0	2	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	6	0	0
T152	0	2	0	0
T175	0	2	0	0
T177	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	59823	0	0
T3	693	35	0	0
T11	0	31	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T42	0	93	0	0
T44	0	78	0	0
T45	0	90	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	169	0	0
T152	0	75	0	0
T175	0	57360	0	0
T177	0	99	0	0
T213	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763421	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	290	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1	0	0
T132	1365	0	0	0
T189	817	1	0	0
T193	653	0	0	0
T194	21602	0	0	0
T195	445	0	0	0
T196	35619	0	0	0
T197	673	0	0	0
T198	502	0	0	0
T199	1882	0	0	0
T200	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64545	0	0
T3	693	28	0	0
T11	0	103	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T44	0	40	0	0
T45	0	102	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	229	0	0
T152	0	58	0	0
T153	0	107	0	0
T175	0	61451	0	0
T177	0	238	0	0
T213	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	44	0	0
T3	693	1	0	0
T11	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T175	0	1	0	0
T177	0	1	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6366581	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6368964	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	49	0	0
T3	693	1	0	0
T11	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	3	0	0
T152	0	1	0	0
T175	0	1	0	0
T177	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	45	0	0
T3	693	1	0	0
T11	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T175	0	1	0	0
T177	0	1	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	44	0	0
T3	693	1	0	0
T11	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T175	0	1	0	0
T177	0	1	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	44	0	0
T3	693	1	0	0
T11	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T175	0	1	0	0
T177	0	1	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64480	0	0
T3	693	27	0	0
T11	0	101	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T44	0	38	0	0
T45	0	101	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	225	0	0
T152	0	57	0	0
T153	0	104	0	0
T175	0	61449	0	0
T177	0	237	0	0
T213	0	90	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6641	0	0
T1	635	0	0	0
T2	16315	19	0	0
T3	693	1	0	0
T4	503	5	0	0
T5	524	4	0	0
T6	490	0	0	0
T14	12958	12	0	0
T15	0	7	0	0
T16	0	5	0	0
T21	504	4	0	0
T22	6629	31	0	0
T23	494	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	23	0	0
T3	693	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T45	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T177	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T44,T214,T215
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T11,T27,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T11,T27,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T27,T42,T44
DetectSt->IdleSt	186	Covered	T44,T214,T215
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T8,T11,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T42,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T44,T214,T215
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T27,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	132	0	0
CntIncr_A	7461812	77269	0	0
CntNoWrap_A	7461812	6763383	0	0
DetectStDropOut_A	7461812	4	0	0
DetectedOut_A	7461812	145094	0	0
DetectedPulseOut_A	7461812	58	0	0
DisabledIdleSt_A	7461812	6486190	0	0
DisabledNoDetection_A	7461812	6488577	0	0
EnterDebounceSt_A	7461812	70	0	0
EnterDetectSt_A	7461812	62	0	0
EnterStableSt_A	7461812	58	0	0
PulseIsPulse_A	7461812	58	0	0
StayInStableSt	7461812	145007	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	132	0	0
T1	635	2	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	2	0	0
T11	0	4	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	5	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	5	0	0
T47	0	2	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	77269	0	0
T1	635	93	0	0
T2	16315	0	0	0
T3	693	35	0	0
T8	0	93	0	0
T11	0	62	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	115	0	0
T39	0	57	0	0
T42	0	93	0	0
T44	0	234	0	0
T47	0	61	0	0
T191	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763383	0	0
T1	635	232	0	0
T2	16315	15073	0	0
T3	693	290	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	4	0	0
T44	904	1	0	0
T79	490	0	0	0
T82	1211	0	0	0
T98	14666	0	0	0
T173	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	505	0	0	0
T217	521	0	0	0
T218	2072	0	0	0
T219	493	0	0	0
T220	523	0	0	0
T221	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	145094	0	0
T1	635	38	0	0
T2	16315	0	0	0
T3	693	188	0	0
T8	0	158	0	0
T11	0	85	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	368	0	0
T39	0	1	0	0
T44	0	40	0	0
T47	0	469	0	0
T48	0	19	0	0
T191	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	58	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	1	0	0
T8	0	1	0	0
T11	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6486190	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6488577	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	70	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	1	0	0
T8	0	1	0	0
T11	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	3	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	3	0	0
T47	0	1	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	62	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	1	0	0
T8	0	1	0	0
T11	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	58	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	1	0	0
T8	0	1	0	0
T11	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	58	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	1	0	0
T8	0	1	0	0
T11	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T39	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	145007	0	0
T1	635	36	0	0
T2	16315	0	0	0
T3	693	186	0	0
T8	0	156	0	0
T11	0	82	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	365	0	0
T44	0	38	0	0
T47	0	467	0	0
T48	0	17	0	0
T191	0	36	0	0
T213	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	29	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	1	0	0
T36	631	0	0	0
T39	0	1	0	0
T48	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	1	0	0
T97	0	1	0	0
T152	0	1	0	0
T155	0	2	0	0
T157	405	0	0	0
T174	0	1	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T45,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T27,T45,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T45,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T21
1	1	Covered	T27,T45,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T45,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T45,T44
0	1	Covered	T27,T45,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T45,T44
1	-	Covered	T27,T45,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T45,T44
DetectSt	168	Covered	T27,T45,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T27,T45,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T45,T44
DebounceSt->IdleSt	163	Covered	T87,T88
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T27,T45,T44
IdleSt->DebounceSt	148	Covered	T27,T45,T44
StableSt->IdleSt	206	Covered	T27,T45,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T45,T44
0	1	Covered	T27,T45,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T45,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T45,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T45,T44
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T45,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T27,T45,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T45,T44
StableSt	-	-	-	-	-	-	0	Covered	T27,T45,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	94	0	0
CntIncr_A	7461812	32491	0	0
CntNoWrap_A	7461812	6763421	0	0
DetectStDropOut_A	7461812	0	0	0
DetectedOut_A	7461812	3161	0	0
DetectedPulseOut_A	7461812	46	0	0
DisabledIdleSt_A	7461812	6643504	0	0
DisabledNoDetection_A	7461812	6645894	0	0
EnterDebounceSt_A	7461812	48	0	0
EnterDetectSt_A	7461812	46	0	0
EnterStableSt_A	7461812	46	0	0
PulseIsPulse_A	7461812	46	0	0
StayInStableSt	7461812	3093	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	6436	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	94	0	0
T27	5364	4	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	2412	0	0	0
T48	0	4	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T87	0	1	0	0
T95	0	2	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	2	0	0
T154	0	2	0	0
T155	0	4	0	0
T174	0	2	0	0
T203	415	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	32491	0	0
T27	5364	54	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	156	0	0
T45	0	90	0	0
T46	2412	0	0	0
T48	0	42	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T87	0	44	0	0
T95	0	91	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	87	0	0
T154	0	39	0	0
T155	0	192	0	0
T174	0	72	0	0
T203	415	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763421	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3161	0	0
T27	5364	81	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	134	0	0
T45	0	106	0	0
T46	2412	0	0	0
T48	0	76	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T95	0	45	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	38	0	0
T154	0	4	0	0
T155	0	128	0	0
T174	0	119	0	0
T202	0	134	0	0
T203	415	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T27	5364	2	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	2412	0	0	0
T48	0	2	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T95	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T174	0	1	0	0
T202	0	2	0	0
T203	415	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6643504	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6645894	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	48	0	0
T27	5364	2	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	2412	0	0	0
T48	0	2	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T87	0	1	0	0
T95	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T174	0	1	0	0
T203	415	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T27	5364	2	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	2412	0	0	0
T48	0	2	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T95	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T174	0	1	0	0
T202	0	2	0	0
T203	415	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T27	5364	2	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	2412	0	0	0
T48	0	2	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T95	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T174	0	1	0	0
T202	0	2	0	0
T203	415	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T27	5364	2	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	2412	0	0	0
T48	0	2	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T95	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T174	0	1	0	0
T202	0	2	0	0
T203	415	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3093	0	0
T27	5364	78	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	132	0	0
T45	0	103	0	0
T46	2412	0	0	0
T48	0	73	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T95	0	43	0	0
T122	502	0	0	0
T123	615	0	0	0
T133	0	36	0	0
T154	0	3	0	0
T155	0	125	0	0
T174	0	117	0	0
T202	0	131	0	0
T203	415	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6436	0	0
T1	635	0	0	0
T2	16315	19	0	0
T3	693	0	0	0
T4	503	5	0	0
T5	524	3	0	0
T6	490	0	0	0
T14	12958	14	0	0
T15	0	12	0	0
T16	0	4	0	0
T18	0	26	0	0
T21	504	5	0	0
T22	6629	31	0	0
T23	494	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	24	0	0
T27	5364	1	0	0
T28	792	0	0	0
T42	10472	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	2412	0	0	0
T48	0	1	0	0
T49	10167	0	0	0
T56	687	0	0	0
T57	717	0	0	0
T122	502	0	0	0
T123	615	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T202	0	1	0	0
T203	415	0	0	0
T223	0	1	0	0
T224	0	1	0	0