Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T8,T11,T27
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T8,T11,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T11
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T175,T87,T155
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T11
StableSt->IdleSt	206	Covered	T8,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T175,T155,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T27
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	152	0	0
CntIncr_A	7461812	162223	0	0
CntNoWrap_A	7461812	6763363	0	0
DetectStDropOut_A	7461812	0	0	0
DetectedOut_A	7461812	61007	0	0
DetectedPulseOut_A	7461812	72	0	0
DisabledIdleSt_A	7461812	6368334	0	0
DisabledNoDetection_A	7461812	6370719	0	0
EnterDebounceSt_A	7461812	80	0	0
EnterDetectSt_A	7461812	72	0	0
EnterStableSt_A	7461812	72	0	0
PulseIsPulse_A	7461812	72	0	0
StayInStableSt	7461812	60903	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	152	0	0
T1	635	2	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	6	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T43	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T177	0	4	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	162223	0	0
T1	635	93	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	293	0	0
T11	0	31	0	0
T13	0	64	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	61	0	0
T43	0	98	0	0
T45	0	90	0	0
T46	0	52	0	0
T177	0	46	0	0
T191	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763363	0	0
T1	635	232	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	61007	0	0
T1	635	38	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	301	0	0
T11	0	27	0	0
T13	0	43	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	206	0	0
T43	0	228	0	0
T45	0	100	0	0
T46	0	5	0	0
T177	0	160	0	0
T191	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6368334	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6370719	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	80	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	72	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T177	0	2	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	60903	0	0
T1	635	36	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	297	0	0
T11	0	26	0	0
T13	0	41	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	205	0	0
T43	0	226	0	0
T45	0	97	0	0
T46	0	4	0	0
T177	0	157	0	0
T191	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	40	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	2	0	0
T133	0	1	0	0
T139	0	1	0	0
T152	0	2	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T13
1	0	Covered	T4,T5,T21
1	1	Covered	T3,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T27
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T27
0	1	Covered	T8,T45,T177
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T27
1	-	Covered	T8,T45,T177

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T27
DetectSt	168	Covered	T3,T8,T27
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T27
DebounceSt->IdleSt	163	Covered	T87,T88,T225
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T27
IdleSt->DebounceSt	148	Covered	T3,T8,T27
StableSt->IdleSt	206	Covered	T8,T27,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T27
0	1	Covered	T3,T8,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T27
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T225,T172,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T45,T177
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	115	0	0
CntIncr_A	7461812	3361	0	0
CntNoWrap_A	7461812	6763400	0	0
DetectStDropOut_A	7461812	0	0	0
DetectedOut_A	7461812	3816	0	0
DetectedPulseOut_A	7461812	55	0	0
DisabledIdleSt_A	7461812	6583359	0	0
DisabledNoDetection_A	7461812	6585743	0	0
EnterDebounceSt_A	7461812	60	0	0
EnterDetectSt_A	7461812	55	0	0
EnterStableSt_A	7461812	55	0	0
PulseIsPulse_A	7461812	55	0	0
StayInStableSt	7461812	3737	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	6526	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	115	0	0
T3	693	2	0	0
T8	0	6	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T29	34371	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0
T87	0	1	0	0
T95	0	2	0	0
T154	0	4	0	0
T177	0	4	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3361	0	0
T3	693	35	0	0
T8	0	215	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	61	0	0
T29	34371	0	0	0
T45	0	45	0	0
T48	0	21	0	0
T59	504	0	0	0
T60	432	0	0	0
T87	0	43	0	0
T95	0	91	0	0
T154	0	78	0	0
T177	0	122	0	0
T187	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763400	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	290	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3816	0	0
T3	693	45	0	0
T8	0	243	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	41	0	0
T29	34371	0	0	0
T45	0	107	0	0
T48	0	136	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	46	0	0
T154	0	132	0	0
T155	0	310	0	0
T177	0	154	0	0
T187	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	55	0	0
T3	693	1	0	0
T8	0	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T29	34371	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	1	0	0
T154	0	2	0	0
T155	0	3	0	0
T177	0	2	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6583359	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6585743	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	60	0	0
T3	693	1	0	0
T8	0	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T29	34371	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T87	0	1	0	0
T95	0	1	0	0
T154	0	2	0	0
T177	0	2	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	55	0	0
T3	693	1	0	0
T8	0	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T29	34371	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	1	0	0
T154	0	2	0	0
T155	0	3	0	0
T177	0	2	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	55	0	0
T3	693	1	0	0
T8	0	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T29	34371	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	1	0	0
T154	0	2	0	0
T155	0	3	0	0
T177	0	2	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	55	0	0
T3	693	1	0	0
T8	0	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T29	34371	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	1	0	0
T154	0	2	0	0
T155	0	3	0	0
T177	0	2	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3737	0	0
T3	693	43	0	0
T8	0	239	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	39	0	0
T29	34371	0	0	0
T45	0	106	0	0
T48	0	134	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	44	0	0
T154	0	130	0	0
T155	0	305	0	0
T177	0	152	0	0
T187	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6526	0	0
T1	635	0	0	0
T2	16315	16	0	0
T3	693	1	0	0
T4	503	5	0	0
T5	524	4	0	0
T6	490	0	0	0
T14	12958	10	0	0
T15	0	13	0	0
T16	0	8	0	0
T21	504	4	0	0
T22	6629	35	0	0
T23	494	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	31	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T45	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T97	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T158	0	1	0	0
T177	0	2	0	0
T187	0	1	0	0
T202	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T153,T223,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T3,T8,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T3,T8,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T87,T88,T227
DetectSt->IdleSt	186	Covered	T153,T223,T97
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T3,T8,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T227,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T153,T223,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T47
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	124	0	0
CntIncr_A	7461812	18339	0	0
CntNoWrap_A	7461812	6763391	0	0
DetectStDropOut_A	7461812	7	0	0
DetectedOut_A	7461812	60983	0	0
DetectedPulseOut_A	7461812	53	0	0
DisabledIdleSt_A	7461812	6644941	0	0
DisabledNoDetection_A	7461812	6647332	0	0
EnterDebounceSt_A	7461812	64	0	0
EnterDetectSt_A	7461812	60	0	0
EnterStableSt_A	7461812	53	0	0
PulseIsPulse_A	7461812	53	0	0
StayInStableSt	7461812	60909	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	124	0	0
T1	635	2	0	0
T2	16315	0	0	0
T3	693	4	0	0
T8	0	6	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T176	0	2	0	0
T177	0	2	0	0
T178	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	18339	0	0
T1	635	93	0	0
T2	16315	0	0	0
T3	693	70	0	0
T8	0	123	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	93	0	0
T47	0	122	0	0
T48	0	21	0	0
T176	0	52	0	0
T177	0	23	0	0
T178	0	17	0	0
T213	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763391	0	0
T1	635	232	0	0
T2	16315	15073	0	0
T3	693	288	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	7	0	0
T89	7096	0	0	0
T97	0	1	0	0
T119	1033	0	0	0
T153	7444	1	0	0
T154	844	0	0	0
T172	0	1	0	0
T215	0	1	0	0
T223	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	414	0	0	0
T231	436	0	0	0
T232	493	0	0	0
T233	422	0	0	0
T234	506	0	0	0
T235	19448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	60983	0	0
T1	635	132	0	0
T2	16315	0	0	0
T3	693	67	0	0
T8	0	242	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	381	0	0
T47	0	256	0	0
T48	0	14	0	0
T176	0	110	0	0
T177	0	43	0	0
T178	0	42	0	0
T213	0	565	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	53	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6644941	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6647332	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	60	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	53	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	53	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	2	0	0
T8	0	3	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	60909	0	0
T1	635	130	0	0
T2	16315	0	0	0
T3	693	64	0	0
T8	0	238	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T42	0	379	0	0
T47	0	253	0	0
T48	0	13	0	0
T176	0	109	0	0
T177	0	42	0	0
T178	0	40	0	0
T213	0	564	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	32	0	0
T3	693	1	0	0
T8	0	2	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T59	504	0	0	0
T60	432	0	0	0
T95	0	2	0	0
T133	0	1	0	0
T158	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T27,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T27,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T27,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T27
1	0	Covered	T4,T5,T21
1	1	Covered	T11,T27,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T27,T44
0	1	Covered	T236
1	0	Covered	T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T27,T44
0	1	Covered	T11,T44,T174
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T27,T44
1	-	Covered	T11,T44,T174

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T27,T44
DetectSt	168	Covered	T11,T27,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T27,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T27,T44
DebounceSt->IdleSt	163	Covered	T152,T88,T236
DetectSt->IdleSt	186	Covered	T87,T236
DetectSt->StableSt	191	Covered	T11,T27,T44
IdleSt->DebounceSt	148	Covered	T11,T27,T44
StableSt->IdleSt	206	Covered	T11,T27,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T27,T44
0	1	Covered	T11,T27,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T27,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T27,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T88
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T27,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T152
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T27,T44
DetectSt	-	-	-	-	1	-	-	Covered	T87,T236
DetectSt	-	-	-	-	0	1	-	Covered	T11,T27,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T44,T174
StableSt	-	-	-	-	-	-	0	Covered	T11,T27,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	82	0	0
CntIncr_A	7461812	17126	0	0
CntNoWrap_A	7461812	6763433	0	0
DetectStDropOut_A	7461812	1	0	0
DetectedOut_A	7461812	3380	0	0
DetectedPulseOut_A	7461812	38	0	0
DisabledIdleSt_A	7461812	6269948	0	0
DisabledNoDetection_A	7461812	6272338	0	0
EnterDebounceSt_A	7461812	43	0	0
EnterDetectSt_A	7461812	40	0	0
EnterStableSt_A	7461812	38	0	0
PulseIsPulse_A	7461812	38	0	0
StayInStableSt	7461812	3323	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	6345	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	82	0	0
T11	673	2	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	2	0	0
T36	631	0	0	0
T44	0	4	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0
T157	405	0	0	0
T174	0	4	0	0
T177	0	2	0	0
T202	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	17126	0	0
T11	673	31	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	61	0	0
T36	631	0	0	0
T44	0	156	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	44	0	0
T152	0	75	0	0
T153	0	27	0	0
T157	405	0	0	0
T174	0	144	0	0
T177	0	23	0	0
T202	0	45	0	0
T213	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763433	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1	0	0
T114	661	0	0	0
T172	1162	0	0	0
T236	9670	1	0	0
T237	746	0	0	0
T238	402	0	0	0
T239	856	0	0	0
T240	18125	0	0	0
T241	4866	0	0	0
T242	426	0	0	0
T243	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3380	0	0
T11	673	28	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	40	0	0
T36	631	0	0	0
T44	0	158	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T153	0	69	0	0
T157	405	0	0	0
T158	0	41	0	0
T174	0	80	0	0
T177	0	155	0	0
T202	0	43	0	0
T213	0	41	0	0
T222	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	38	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	1	0	0
T36	631	0	0	0
T44	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T153	0	1	0	0
T157	405	0	0	0
T158	0	1	0	0
T174	0	2	0	0
T177	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T222	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6269948	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6272338	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	43	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	1	0	0
T36	631	0	0	0
T44	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T157	405	0	0	0
T174	0	2	0	0
T177	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	40	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	1	0	0
T36	631	0	0	0
T44	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	1	0	0
T153	0	1	0	0
T157	405	0	0	0
T158	0	1	0	0
T174	0	2	0	0
T177	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	38	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	1	0	0
T36	631	0	0	0
T44	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T153	0	1	0	0
T157	405	0	0	0
T158	0	1	0	0
T174	0	2	0	0
T177	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T222	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	38	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	1	0	0
T36	631	0	0	0
T44	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T153	0	1	0	0
T157	405	0	0	0
T158	0	1	0	0
T174	0	2	0	0
T177	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T222	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3323	0	0
T11	673	27	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T27	0	38	0	0
T36	631	0	0	0
T44	0	155	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T153	0	68	0	0
T157	405	0	0	0
T158	0	39	0	0
T174	0	77	0	0
T177	0	153	0	0
T202	0	42	0	0
T213	0	39	0	0
T222	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6345	0	0
T1	635	0	0	0
T2	16315	20	0	0
T3	693	1	0	0
T4	503	4	0	0
T5	524	4	0	0
T6	490	0	0	0
T14	12958	10	0	0
T15	0	11	0	0
T16	0	4	0	0
T21	504	6	0	0
T22	6629	24	0	0
T23	494	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	19	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T44	0	1	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T153	0	1	0	0
T157	405	0	0	0
T160	0	3	0	0
T174	0	1	0	0
T202	0	1	0	0
T222	0	1	0	0
T244	0	1	0	0
T245	0	2	0	0
T246	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T45
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T8,T46,T177
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T8,T46,T177

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T11
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T175,T87,T155
DetectSt->IdleSt	186	Covered	T45
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T11
StableSt->IdleSt	206	Covered	T8,T27,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T175,T155,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T45
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T46,T177
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	146	0	0
CntIncr_A	7461812	148476	0	0
CntNoWrap_A	7461812	6763369	0	0
DetectStDropOut_A	7461812	1	0	0
DetectedOut_A	7461812	6237	0	0
DetectedPulseOut_A	7461812	68	0	0
DisabledIdleSt_A	7461812	6425846	0	0
DisabledNoDetection_A	7461812	6428234	0	0
EnterDebounceSt_A	7461812	77	0	0
EnterDetectSt_A	7461812	69	0	0
EnterStableSt_A	7461812	68	0	0
PulseIsPulse_A	7461812	68	0	0
StayInStableSt	7461812	6141	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	146	0	0
T1	635	2	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	10	0	0
T11	0	2	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	2	0	0
T45	0	4	0	0
T46	0	4	0	0
T152	0	2	0	0
T175	0	3	0	0
T177	0	4	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	148476	0	0
T1	635	93	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	238	0	0
T11	0	31	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	27	0	0
T45	0	90	0	0
T46	0	104	0	0
T152	0	75	0	0
T175	0	114720	0	0
T177	0	46	0	0
T178	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763369	0	0
T1	635	232	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1	0	0
T44	904	0	0	0
T45	799	1	0	0
T47	939	0	0	0
T100	592	0	0	0
T106	23389	0	0	0
T107	11109	0	0	0
T151	433	0	0	0
T247	24712	0	0	0
T248	422	0	0	0
T249	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6237	0	0
T1	635	133	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	458	0	0
T11	0	232	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	190	0	0
T45	0	209	0	0
T46	0	76	0	0
T152	0	160	0	0
T175	0	38	0	0
T177	0	93	0	0
T178	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	68	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T152	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6425846	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6428234	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	77	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T152	0	1	0	0
T175	0	2	0	0
T177	0	2	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	69	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T152	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	68	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T152	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	68	0	0
T1	635	1	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T152	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6141	0	0
T1	635	131	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	451	0	0
T11	0	230	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T27	0	188	0	0
T45	0	207	0	0
T46	0	73	0	0
T152	0	159	0	0
T175	0	36	0	0
T177	0	91	0	0
T178	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	40	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T46	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T152	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0
T159	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T223	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T42,T43
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T42,T43
0	1	Covered	T8,T177,T175
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T42,T43
1	-	Covered	T8,T177,T175

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T42,T43
DetectSt	168	Covered	T8,T42,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T42,T43
DebounceSt->IdleSt	163	Covered	T87,T88
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T8,T42,T43
IdleSt->DebounceSt	148	Covered	T8,T42,T43
StableSt->IdleSt	206	Covered	T8,T42,T177

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T42,T43
0	1	Covered	T8,T42,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T42,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T42,T43
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T8,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T177,T175
StableSt	-	-	-	-	-	-	0	Covered	T8,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	92	0	0
CntIncr_A	7461812	89702	0	0
CntNoWrap_A	7461812	6763423	0	0
DetectStDropOut_A	7461812	1	0	0
DetectedOut_A	7461812	108688	0	0
DetectedPulseOut_A	7461812	44	0	0
DisabledIdleSt_A	7461812	6425476	0	0
DisabledNoDetection_A	7461812	6427863	0	0
EnterDebounceSt_A	7461812	47	0	0
EnterDetectSt_A	7461812	45	0	0
EnterStableSt_A	7461812	44	0	0
PulseIsPulse_A	7461812	44	0	0
StayInStableSt	7461812	108622	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	7035	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	92	0	0
T8	26040	4	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T87	0	1	0	0
T95	0	6	0	0
T155	0	2	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	89702	0	0
T8	26040	30	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	93	0	0
T43	0	98	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T87	0	43	0	0
T95	0	169	0	0
T155	0	39	0	0
T175	0	57360	0	0
T177	0	46	0	0
T178	0	17	0	0
T213	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763423	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1	0	0
T91	663	1	0	0
T245	21547	0	0	0
T250	40612	0	0	0
T251	656	0	0	0
T252	438	0	0	0
T253	499	0	0	0
T254	505	0	0	0
T255	406	0	0	0
T256	2333	0	0	0
T257	438	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	108688	0	0
T8	26040	55	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	41	0	0
T43	0	38	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	95	0	0
T155	0	43	0	0
T175	0	61456	0	0
T177	0	100	0	0
T178	0	42	0	0
T202	0	10	0	0
T213	0	229	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	44	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	3	0	0
T155	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6425476	0	0
T1	635	4	0	0
T2	16315	15073	0	0
T3	693	3	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6427863	0	0
T1	635	4	0	0
T2	16315	15079	0	0
T3	693	3	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	47	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T87	0	1	0	0
T95	0	3	0	0
T155	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	45	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	3	0	0
T155	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	44	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	3	0	0
T155	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	44	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	3	0	0
T155	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	108622	0	0
T8	26040	53	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T42	0	39	0	0
T43	0	36	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	91	0	0
T155	0	41	0	0
T175	0	61455	0	0
T177	0	97	0	0
T178	0	40	0	0
T202	0	9	0	0
T213	0	227	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	7035	0	0
T1	635	0	0	0
T2	16315	19	0	0
T3	693	0	0	0
T4	503	5	0	0
T5	524	5	0	0
T6	490	0	0	0
T14	12958	12	0	0
T15	0	14	0	0
T16	0	6	0	0
T18	0	31	0	0
T21	504	5	0	0
T22	6629	25	0	0
T23	494	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	22	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T95	0	2	0	0
T156	0	1	0	0
T160	0	2	0	0
T175	0	1	0	0
T177	0	1	0	0
T202	0	1	0	0
T214	0	2	0	0
T258	0	1	0	0
T259	0	1	0	0