Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T18,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T18,T30
1	0	Covered	T22,T30,T10
1	1	Covered	T22,T18,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T30
0	1	Covered	T18,T51,T104
1	0	Covered	T22,T106,T107

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T10,T38
0	1	Covered	T30,T10,T38
1	0	Covered	T92,T93

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T10,T38
1	-	Covered	T30,T10,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T18,T30
DetectSt	168	Covered	T22,T18,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T30,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T18,T30
DebounceSt->IdleSt	163	Covered	T98,T260,T87
DetectSt->IdleSt	186	Covered	T22,T18,T51
DetectSt->StableSt	191	Covered	T30,T10,T38
IdleSt->DebounceSt	148	Covered	T22,T18,T30
StableSt->IdleSt	206	Covered	T30,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T18,T30
0	1	Covered	T22,T18,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T18,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T18,T30
IdleSt	0	-	-	-	-	-	-	Covered	T22,T18,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T18,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T260,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T18,T30
DetectSt	-	-	-	-	1	-	-	Covered	T22,T18,T51
DetectSt	-	-	-	-	0	1	-	Covered	T30,T10,T38
DetectSt	-	-	-	-	0	0	-	Covered	T22,T18,T30
StableSt	-	-	-	-	-	-	1	Covered	T30,T10,T38
StableSt	-	-	-	-	-	-	0	Covered	T30,T10,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	2746	0	0
CntIncr_A	7461812	92628	0	0
CntNoWrap_A	7461812	6760769	0	0
DetectStDropOut_A	7461812	330	0	0
DetectedOut_A	7461812	65057	0	0
DetectedPulseOut_A	7461812	888	0	0
DisabledIdleSt_A	7461812	6326525	0	0
DisabledNoDetection_A	7461812	6328800	0	0
EnterDebounceSt_A	7461812	1404	0	0
EnterDetectSt_A	7461812	1343	0	0
EnterStableSt_A	7461812	888	0	0
PulseIsPulse_A	7461812	888	0	0
StayInStableSt	7461812	64091	0	0
gen_high_event_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	790	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	2746	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	62	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	18	0	0
T22	6629	10	0	0
T23	494	0	0	0
T30	0	44	0	0
T38	0	14	0	0
T40	0	52	0	0
T49	0	30	0	0
T51	0	26	0	0
T80	0	30	0	0
T81	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	92628	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	1395	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	452	0	0
T22	6629	286	0	0
T23	494	0	0	0
T30	0	572	0	0
T38	0	385	0	0
T40	0	1794	0	0
T49	0	1170	0	0
T51	0	573	0	0
T80	0	1245	0	0
T81	0	1176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6760769	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6218	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	330	0	0
T7	6322	0	0	0
T18	5166	9	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T50	8992	0	0	0
T51	0	13	0	0
T59	504	0	0	0
T60	432	0	0	0
T61	846	0	0	0
T104	0	12	0	0
T106	0	1	0	0
T107	0	6	0	0
T108	0	23	0	0
T110	0	4	0	0
T111	0	10	0	0
T112	0	26	0	0
T260	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	65057	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	2347	0	0
T11	673	0	0	0
T30	5700	384	0	0
T38	0	184	0	0
T40	0	2921	0	0
T49	0	56	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	546	0	0
T81	0	2047	0	0
T98	0	227	0	0
T261	0	84	0	0
T262	0	1239	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	888	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	31	0	0
T11	673	0	0	0
T30	5700	22	0	0
T38	0	7	0	0
T40	0	26	0	0
T49	0	15	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	15	0	0
T81	0	28	0	0
T98	0	1	0	0
T261	0	1	0	0
T262	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6326525	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	3214	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6328800	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	3214	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1404	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	31	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	9	0	0
T22	6629	5	0	0
T23	494	0	0	0
T30	0	22	0	0
T38	0	7	0	0
T40	0	26	0	0
T49	0	15	0	0
T51	0	13	0	0
T80	0	15	0	0
T81	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1343	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	31	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	9	0	0
T22	6629	5	0	0
T23	494	0	0	0
T30	0	22	0	0
T38	0	7	0	0
T40	0	26	0	0
T49	0	15	0	0
T51	0	13	0	0
T80	0	15	0	0
T81	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	888	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	31	0	0
T11	673	0	0	0
T30	5700	22	0	0
T38	0	7	0	0
T40	0	26	0	0
T49	0	15	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	15	0	0
T81	0	28	0	0
T98	0	1	0	0
T261	0	1	0	0
T262	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	888	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	31	0	0
T11	673	0	0	0
T30	5700	22	0	0
T38	0	7	0	0
T40	0	26	0	0
T49	0	15	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	15	0	0
T81	0	28	0	0
T98	0	1	0	0
T261	0	1	0	0
T262	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64091	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	2313	0	0
T11	673	0	0	0
T30	5700	362	0	0
T38	0	177	0	0
T40	0	2893	0	0
T49	0	41	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	531	0	0
T81	0	2015	0	0
T98	0	226	0	0
T261	0	82	0	0
T262	0	1223	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	790	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	28	0	0
T11	673	0	0	0
T30	5700	22	0	0
T38	0	7	0	0
T40	0	24	0	0
T49	0	15	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	15	0	0
T81	0	24	0	0
T98	0	1	0	0
T262	0	16	0	0
T263	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T14,T2,T50

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T30
1	0	Covered	T22,T14,T2
1	1	Covered	T14,T2,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T50
0	1	Covered	T14,T50,T8
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T10
0	1	Covered	T2,T7,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T10
1	-	Covered	T2,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T50
DetectSt	168	Covered	T14,T2,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T50
DebounceSt->IdleSt	163	Covered	T14,T2,T50
DetectSt->IdleSt	186	Covered	T14,T50,T8
DetectSt->StableSt	191	Covered	T2,T7,T10
IdleSt->DebounceSt	148	Covered	T14,T2,T50
StableSt->IdleSt	206	Covered	T2,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T2,T50
0	1	Covered	T14,T2,T50
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T50
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T50
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T2,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T50
DetectSt	-	-	-	-	1	-	-	Covered	T14,T50,T8
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T10
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T50
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	1100	0	0
CntIncr_A	7461812	61980	0	0
CntNoWrap_A	7461812	6762415	0	0
DetectStDropOut_A	7461812	128	0	0
DetectedOut_A	7461812	13728	0	0
DetectedPulseOut_A	7461812	366	0	0
DisabledIdleSt_A	7461812	6372160	0	0
DisabledNoDetection_A	7461812	6373861	0	0
EnterDebounceSt_A	7461812	604	0	0
EnterDetectSt_A	7461812	499	0	0
EnterStableSt_A	7461812	366	0	0
PulseIsPulse_A	7461812	366	0	0
StayInStableSt	7461812	13330	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	331	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1100	0	0
T2	16315	7	0	0
T3	693	0	0	0
T7	0	2	0	0
T8	0	10	0	0
T9	0	19	0	0
T10	0	8	0	0
T12	0	26	0	0
T13	0	6	0	0
T14	12958	17	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T50	0	5	0	0
T63	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	61980	0	0
T2	16315	439	0	0
T3	693	0	0	0
T7	0	25	0	0
T8	0	264	0	0
T9	0	744	0	0
T10	0	242	0	0
T12	0	1125	0	0
T13	0	275	0	0
T14	12958	1442	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T50	0	246	0	0
T63	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6762415	0	0
T1	635	234	0	0
T2	16315	15066	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12521	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	128	0	0
T2	16315	0	0	0
T3	693	0	0	0
T8	0	4	0	0
T9	0	9	0	0
T12	0	13	0	0
T13	0	1	0	0
T14	12958	8	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T50	0	2	0	0
T63	0	1	0	0
T105	0	1	0	0
T109	0	5	0	0
T113	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	13728	0	0
T2	16315	122	0	0
T3	693	0	0	0
T7	0	4	0	0
T10	0	184	0	0
T13	0	77	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T39	0	7	0	0
T40	0	78	0	0
T46	0	3	0	0
T54	0	59	0	0
T59	504	0	0	0
T64	0	145	0	0
T115	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	366	0	0
T2	16315	3	0	0
T3	693	0	0	0
T7	0	1	0	0
T10	0	3	0	0
T13	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T46	0	1	0	0
T54	0	3	0	0
T59	504	0	0	0
T64	0	2	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6372160	0	0
T1	635	234	0	0
T2	16315	10163	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	8058	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6373861	0	0
T1	635	235	0	0
T2	16315	10164	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	8058	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	604	0	0
T2	16315	4	0	0
T3	693	0	0	0
T7	0	1	0	0
T8	0	7	0	0
T9	0	10	0	0
T10	0	5	0	0
T12	0	13	0	0
T13	0	5	0	0
T14	12958	9	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T50	0	3	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	499	0	0
T2	16315	3	0	0
T3	693	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T9	0	9	0	0
T10	0	3	0	0
T12	0	13	0	0
T13	0	2	0	0
T14	12958	8	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T50	0	2	0	0
T63	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	366	0	0
T2	16315	3	0	0
T3	693	0	0	0
T7	0	1	0	0
T10	0	3	0	0
T13	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T46	0	1	0	0
T54	0	3	0	0
T59	504	0	0	0
T64	0	2	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	366	0	0
T2	16315	3	0	0
T3	693	0	0	0
T7	0	1	0	0
T10	0	3	0	0
T13	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T46	0	1	0	0
T54	0	3	0	0
T59	504	0	0	0
T64	0	2	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	13330	0	0
T2	16315	119	0	0
T3	693	0	0	0
T7	0	3	0	0
T10	0	181	0	0
T13	0	76	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T39	0	6	0	0
T40	0	75	0	0
T46	0	2	0	0
T54	0	56	0	0
T59	504	0	0	0
T64	0	143	0	0
T115	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	331	0	0
T2	16315	3	0	0
T3	693	0	0	0
T7	0	1	0	0
T10	0	3	0	0
T13	0	1	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T54	0	3	0	0
T59	504	0	0	0
T64	0	2	0	0
T115	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T18,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T18,T30
1	0	Covered	T22,T30,T10
1	1	Covered	T22,T18,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T30
0	1	Covered	T18,T51,T104
1	0	Covered	T30,T81,T264

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T10,T38
0	1	Covered	T22,T10,T38
1	0	Covered	T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T10,T38
1	-	Covered	T22,T10,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T18,T30
DetectSt	168	Covered	T22,T18,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T18,T30
DebounceSt->IdleSt	163	Covered	T98,T260,T87
DetectSt->IdleSt	186	Covered	T18,T30,T51
DetectSt->StableSt	191	Covered	T22,T10,T38
IdleSt->DebounceSt	148	Covered	T22,T18,T30
StableSt->IdleSt	206	Covered	T22,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T18,T30
0	1	Covered	T22,T18,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T18,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T18,T30
IdleSt	0	-	-	-	-	-	-	Covered	T22,T18,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T18,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T260,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T18,T30
DetectSt	-	-	-	-	1	-	-	Covered	T18,T30,T51
DetectSt	-	-	-	-	0	1	-	Covered	T22,T10,T38
DetectSt	-	-	-	-	0	0	-	Covered	T22,T18,T30
StableSt	-	-	-	-	-	-	1	Covered	T22,T10,T38
StableSt	-	-	-	-	-	-	0	Covered	T22,T10,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	3101	0	0
CntIncr_A	7461812	109114	0	0
CntNoWrap_A	7461812	6760414	0	0
DetectStDropOut_A	7461812	388	0	0
DetectedOut_A	7461812	75341	0	0
DetectedPulseOut_A	7461812	927	0	0
DisabledIdleSt_A	7461812	6317538	0	0
DisabledNoDetection_A	7461812	6319802	0	0
EnterDebounceSt_A	7461812	1600	0	0
EnterDetectSt_A	7461812	1502	0	0
EnterStableSt_A	7461812	927	0	0
PulseIsPulse_A	7461812	927	0	0
StayInStableSt	7461812	74324	0	0
gen_high_event_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	836	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3101	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	34	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	48	0	0
T22	6629	44	0	0
T23	494	0	0	0
T30	0	30	0	0
T38	0	58	0	0
T40	0	52	0	0
T49	0	10	0	0
T51	0	32	0	0
T80	0	52	0	0
T81	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	109114	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	697	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	1220	0	0
T22	6629	1144	0	0
T23	494	0	0	0
T30	0	611	0	0
T38	0	1421	0	0
T40	0	2418	0	0
T49	0	390	0	0
T51	0	713	0	0
T80	0	2392	0	0
T81	0	984	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6760414	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6184	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	388	0	0
T7	6322	0	0	0
T18	5166	24	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T50	8992	0	0	0
T51	0	16	0	0
T59	504	0	0	0
T60	432	0	0	0
T61	846	0	0	0
T87	0	1	0	0
T104	0	23	0	0
T108	0	15	0	0
T110	0	13	0	0
T111	0	14	0	0
T112	0	15	0	0
T260	0	7	0	0
T265	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	75341	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	1705	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	159	0	0
T23	494	0	0	0
T38	0	1794	0	0
T40	0	1527	0	0
T49	0	15	0	0
T80	0	2285	0	0
T106	0	829	0	0
T107	0	577	0	0
T262	0	4302	0	0
T263	0	2901	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	927	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	17	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	22	0	0
T23	494	0	0	0
T38	0	29	0	0
T40	0	26	0	0
T49	0	5	0	0
T80	0	26	0	0
T106	0	10	0	0
T107	0	12	0	0
T262	0	31	0	0
T263	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6317538	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	3147	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6319802	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	3147	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1600	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	17	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	24	0	0
T22	6629	22	0	0
T23	494	0	0	0
T30	0	15	0	0
T38	0	29	0	0
T40	0	26	0	0
T49	0	5	0	0
T51	0	16	0	0
T80	0	26	0	0
T81	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1502	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	17	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	24	0	0
T22	6629	22	0	0
T23	494	0	0	0
T30	0	15	0	0
T38	0	29	0	0
T40	0	26	0	0
T49	0	5	0	0
T51	0	16	0	0
T80	0	26	0	0
T81	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	927	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	17	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	22	0	0
T23	494	0	0	0
T38	0	29	0	0
T40	0	26	0	0
T49	0	5	0	0
T80	0	26	0	0
T106	0	10	0	0
T107	0	12	0	0
T262	0	31	0	0
T263	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	927	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	17	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	22	0	0
T23	494	0	0	0
T38	0	29	0	0
T40	0	26	0	0
T49	0	5	0	0
T80	0	26	0	0
T106	0	10	0	0
T107	0	12	0	0
T262	0	31	0	0
T263	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	74324	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	1687	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	137	0	0
T23	494	0	0	0
T38	0	1758	0	0
T40	0	1501	0	0
T49	0	10	0	0
T80	0	2258	0	0
T106	0	817	0	0
T107	0	565	0	0
T262	0	4270	0	0
T263	0	2879	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	836	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	16	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	22	0	0
T23	494	0	0	0
T38	0	22	0	0
T40	0	26	0	0
T49	0	5	0	0
T80	0	25	0	0
T106	0	8	0	0
T107	0	12	0	0
T262	0	30	0	0
T263	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T14,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T14,T2
1	0	Covered	T22,T14,T2
1	1	Covered	T14,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T15
0	1	Covered	T15,T50,T54
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T8
0	1	Covered	T14,T2,T8
1	0	Covered	T10,T89,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T2,T8
1	-	Covered	T14,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T15
DetectSt	168	Covered	T14,T2,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T14,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T15
DebounceSt->IdleSt	163	Covered	T14,T50,T13
DetectSt->IdleSt	186	Covered	T15,T50,T54
DetectSt->StableSt	191	Covered	T14,T2,T8
IdleSt->DebounceSt	148	Covered	T14,T2,T15
StableSt->IdleSt	206	Covered	T14,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T2,T15
0	1	Covered	T14,T2,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T50,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T50,T54
DetectSt	-	-	-	-	0	1	-	Covered	T14,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T15
StableSt	-	-	-	-	-	-	1	Covered	T14,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T14,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	895	0	0
CntIncr_A	7461812	49092	0	0
CntNoWrap_A	7461812	6762620	0	0
DetectStDropOut_A	7461812	55	0	0
DetectedOut_A	7461812	16160	0	0
DetectedPulseOut_A	7461812	367	0	0
DisabledIdleSt_A	7461812	6359224	0	0
DisabledNoDetection_A	7461812	6360999	0	0
EnterDebounceSt_A	7461812	471	0	0
EnterDetectSt_A	7461812	426	0	0
EnterStableSt_A	7461812	367	0	0
PulseIsPulse_A	7461812	367	0	0
StayInStableSt	7461812	15770	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	337	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	895	0	0
T2	16315	16	0	0
T3	693	0	0	0
T8	0	2	0	0
T9	0	4	0	0
T10	0	6	0	0
T12	0	14	0	0
T13	0	2	0	0
T14	12958	5	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	10	0	0
T50	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	49092	0	0
T2	16315	816	0	0
T3	693	0	0	0
T8	0	47	0	0
T9	0	94	0	0
T10	0	144	0	0
T12	0	560	0	0
T13	0	141	0	0
T14	12958	413	0	0
T15	9729	97	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	240	0	0
T50	0	941	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6762620	0	0
T1	635	234	0	0
T2	16315	15057	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12533	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	55	0	0
T15	9729	1	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T39	0	3	0	0
T50	0	9	0	0
T54	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T266	0	2	0	0
T267	0	2	0	0
T268	0	4	0	0
T269	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	16160	0	0
T2	16315	439	0	0
T3	693	0	0	0
T8	0	5	0	0
T9	0	62	0	0
T10	0	354	0	0
T12	0	39	0	0
T13	0	77	0	0
T14	12958	36	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	424	0	0
T63	0	101	0	0
T80	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	367	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	7	0	0
T13	0	1	0	0
T14	12958	2	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	5	0	0
T63	0	6	0	0
T80	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6359224	0	0
T1	635	234	0	0
T2	16315	10163	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	8058	0	0
T21	504	103	0	0
T22	6629	6069	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6360999	0	0
T1	635	235	0	0
T2	16315	10164	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	8058	0	0
T21	504	104	0	0
T22	6629	6070	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	471	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	7	0	0
T13	0	2	0	0
T14	12958	3	0	0
T15	9729	1	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	5	0	0
T50	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	426	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	7	0	0
T13	0	1	0	0
T14	12958	2	0	0
T15	9729	1	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	5	0	0
T50	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	367	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	7	0	0
T13	0	1	0	0
T14	12958	2	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	5	0	0
T63	0	6	0	0
T80	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	367	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	7	0	0
T13	0	1	0	0
T14	12958	2	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	5	0	0
T63	0	6	0	0
T80	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	15770	0	0
T2	16315	431	0	0
T3	693	0	0	0
T8	0	4	0	0
T9	0	60	0	0
T10	0	351	0	0
T12	0	32	0	0
T13	0	76	0	0
T14	12958	34	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	419	0	0
T63	0	95	0	0
T80	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	337	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	7	0	0
T13	0	1	0	0
T14	12958	2	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	5	0	0
T63	0	6	0	0
T80	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T18,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T18,T30
1	0	Covered	T22,T30,T10
1	1	Covered	T22,T18,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T30
0	1	Covered	T18,T51,T104
1	0	Covered	T22,T40,T270

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T10,T38
0	1	Covered	T30,T10,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T10,T38
1	-	Covered	T30,T10,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T18,T30
DetectSt	168	Covered	T22,T18,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T30,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T18,T30
DebounceSt->IdleSt	163	Covered	T98,T260,T87
DetectSt->IdleSt	186	Covered	T22,T18,T51
DetectSt->StableSt	191	Covered	T30,T10,T38
IdleSt->DebounceSt	148	Covered	T22,T18,T30
StableSt->IdleSt	206	Covered	T30,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T18,T30
0	1	Covered	T22,T18,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T18,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T18,T30
IdleSt	0	-	-	-	-	-	-	Covered	T22,T18,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T18,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T260,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T18,T30
DetectSt	-	-	-	-	1	-	-	Covered	T22,T18,T51
DetectSt	-	-	-	-	0	1	-	Covered	T30,T10,T38
DetectSt	-	-	-	-	0	0	-	Covered	T22,T18,T30
StableSt	-	-	-	-	-	-	1	Covered	T30,T10,T38
StableSt	-	-	-	-	-	-	0	Covered	T30,T10,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	2973	0	0
CntIncr_A	7461812	101766	0	0
CntNoWrap_A	7461812	6760542	0	0
DetectStDropOut_A	7461812	375	0	0
DetectedOut_A	7461812	71490	0	0
DetectedPulseOut_A	7461812	921	0	0
DisabledIdleSt_A	7461812	6319324	0	0
DisabledNoDetection_A	7461812	6321578	0	0
EnterDebounceSt_A	7461812	1529	0	0
EnterDetectSt_A	7461812	1445	0	0
EnterStableSt_A	7461812	921	0	0
PulseIsPulse_A	7461812	921	0	0
StayInStableSt	7461812	70469	0	0
gen_high_event_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	821	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	2973	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	20	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	22	0	0
T22	6629	44	0	0
T23	494	0	0	0
T30	0	54	0	0
T38	0	34	0	0
T40	0	30	0	0
T49	0	58	0	0
T51	0	26	0	0
T80	0	4	0	0
T81	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	101766	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	420	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	559	0	0
T22	6629	1260	0	0
T23	494	0	0	0
T30	0	837	0	0
T38	0	884	0	0
T40	0	2022	0	0
T49	0	1740	0	0
T51	0	574	0	0
T80	0	126	0	0
T81	0	1260	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6760542	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6184	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	375	0	0
T7	6322	0	0	0
T18	5166	11	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T50	8992	0	0	0
T51	0	13	0	0
T59	504	0	0	0
T60	432	0	0	0
T61	846	0	0	0
T104	0	27	0	0
T108	0	24	0	0
T110	0	9	0	0
T111	0	3	0	0
T112	0	19	0	0
T260	0	5	0	0
T270	0	7	0	0
T271	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	71490	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	1153	0	0
T11	673	0	0	0
T30	5700	1227	0	0
T38	0	866	0	0
T49	0	1694	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	112	0	0
T81	0	1963	0	0
T106	0	1227	0	0
T107	0	1431	0	0
T262	0	405	0	0
T263	0	3128	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	921	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	10	0	0
T11	673	0	0	0
T30	5700	27	0	0
T38	0	17	0	0
T49	0	29	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	2	0	0
T81	0	28	0	0
T106	0	16	0	0
T107	0	23	0	0
T262	0	6	0	0
T263	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6319324	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	3220	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6321578	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	3220	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1529	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	10	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	11	0	0
T22	6629	22	0	0
T23	494	0	0	0
T30	0	27	0	0
T38	0	17	0	0
T40	0	15	0	0
T49	0	29	0	0
T51	0	13	0	0
T80	0	2	0	0
T81	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1445	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	10	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	11	0	0
T22	6629	22	0	0
T23	494	0	0	0
T30	0	27	0	0
T38	0	17	0	0
T40	0	15	0	0
T49	0	29	0	0
T51	0	13	0	0
T80	0	2	0	0
T81	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	921	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	10	0	0
T11	673	0	0	0
T30	5700	27	0	0
T38	0	17	0	0
T49	0	29	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	2	0	0
T81	0	28	0	0
T106	0	16	0	0
T107	0	23	0	0
T262	0	6	0	0
T263	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	921	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	10	0	0
T11	673	0	0	0
T30	5700	27	0	0
T38	0	17	0	0
T49	0	29	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	2	0	0
T81	0	28	0	0
T106	0	16	0	0
T107	0	23	0	0
T262	0	6	0	0
T263	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	70469	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	1140	0	0
T11	673	0	0	0
T30	5700	1200	0	0
T38	0	845	0	0
T49	0	1665	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	110	0	0
T81	0	1931	0	0
T106	0	1208	0	0
T107	0	1407	0	0
T262	0	398	0	0
T263	0	3092	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	821	0	0
T7	6322	0	0	0
T8	26040	0	0	0
T9	9027	0	0	0
T10	13667	7	0	0
T11	673	0	0	0
T30	5700	27	0	0
T38	0	13	0	0
T49	0	29	0	0
T50	8992	0	0	0
T61	846	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T80	0	2	0	0
T81	0	24	0	0
T106	0	13	0	0
T107	0	22	0	0
T262	0	5	0	0
T263	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T14,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T15
1	0	Covered	T22,T14,T2
1	1	Covered	T14,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T15
0	1	Covered	T15,T50,T54
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T8
0	1	Covered	T14,T2,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T2,T8
1	-	Covered	T14,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T15
DetectSt	168	Covered	T14,T2,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T14,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T15
DebounceSt->IdleSt	163	Covered	T14,T50,T13
DetectSt->IdleSt	186	Covered	T15,T50,T54
DetectSt->StableSt	191	Covered	T14,T2,T8
IdleSt->DebounceSt	148	Covered	T14,T2,T15
StableSt->IdleSt	206	Covered	T14,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T2,T15
0	1	Covered	T14,T2,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T50,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T50,T54
DetectSt	-	-	-	-	0	1	-	Covered	T14,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T15
StableSt	-	-	-	-	-	-	1	Covered	T14,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T14,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	959	0	0
CntIncr_A	7461812	54934	0	0
CntNoWrap_A	7461812	6762556	0	0
DetectStDropOut_A	7461812	102	0	0
DetectedOut_A	7461812	16547	0	0
DetectedPulseOut_A	7461812	351	0	0
DisabledIdleSt_A	7461812	6357048	0	0
DisabledNoDetection_A	7461812	6358810	0	0
EnterDebounceSt_A	7461812	503	0	0
EnterDetectSt_A	7461812	460	0	0
EnterStableSt_A	7461812	351	0	0
PulseIsPulse_A	7461812	351	0	0
StayInStableSt	7461812	16154	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	307	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	959	0	0
T2	16315	2	0	0
T3	693	0	0	0
T8	0	2	0	0
T9	0	4	0	0
T10	0	4	0	0
T12	0	10	0	0
T13	0	2	0	0
T14	12958	7	0	0
T15	9729	4	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	4	0	0
T50	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	54934	0	0
T2	16315	148	0	0
T3	693	0	0	0
T8	0	47	0	0
T9	0	142	0	0
T10	0	92	0	0
T12	0	370	0	0
T13	0	164	0	0
T14	12958	596	0	0
T15	9729	193	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	106	0	0
T50	0	941	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6762556	0	0
T1	635	234	0	0
T2	16315	15071	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12531	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	102	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T50	0	9	0	0
T54	0	9	0	0
T59	504	0	0	0
T60	432	0	0	0
T105	0	1	0	0
T109	0	7	0	0
T155	0	4	0	0
T272	0	7	0	0
T273	0	11	0	0
T274	0	3	0	0
T275	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	16547	0	0
T2	16315	9	0	0
T3	693	0	0	0
T8	0	5	0	0
T9	0	14	0	0
T10	0	156	0	0
T12	0	57	0	0
T13	0	54	0	0
T14	12958	20	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	157	0	0
T63	0	30	0	0
T64	0	364	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	351	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	0	1	0	0
T14	12958	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	2	0	0
T63	0	7	0	0
T64	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6357048	0	0
T1	635	234	0	0
T2	16315	10163	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	8058	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6358810	0	0
T1	635	235	0	0
T2	16315	10164	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	8058	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	503	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	0	2	0	0
T14	12958	4	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	2	0	0
T50	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	460	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	0	1	0	0
T14	12958	3	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	2	0	0
T50	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	351	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	0	1	0	0
T14	12958	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	2	0	0
T63	0	7	0	0
T64	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	351	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	0	1	0	0
T14	12958	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	2	0	0
T63	0	7	0	0
T64	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	16154	0	0
T2	16315	8	0	0
T3	693	0	0	0
T8	0	4	0	0
T9	0	12	0	0
T10	0	154	0	0
T12	0	52	0	0
T13	0	53	0	0
T14	12958	17	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	153	0	0
T63	0	23	0	0
T64	0	356	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	307	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	0	1	0	0
T14	12958	3	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T41	0	11	0	0
T63	0	7	0	0
T64	0	8	0	0