Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T18,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T18,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T18,T30
1	0	Covered	T22,T30,T10
1	1	Covered	T22,T18,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T30
0	1	Covered	T18,T30,T51
1	0	Covered	T30,T10,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T38,T49
0	1	Covered	T22,T38,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T38,T49
1	-	Covered	T22,T38,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T18,T30
DetectSt	168	Covered	T22,T18,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T38,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T18,T30
DebounceSt->IdleSt	163	Covered	T98,T260,T87
DetectSt->IdleSt	186	Covered	T18,T30,T10
DetectSt->StableSt	191	Covered	T22,T38,T49
IdleSt->DebounceSt	148	Covered	T22,T18,T30
StableSt->IdleSt	206	Covered	T22,T38,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T18,T30
0	1	Covered	T22,T18,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T18,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T18,T30
IdleSt	0	-	-	-	-	-	-	Covered	T22,T18,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T18,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T260,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T18,T30
DetectSt	-	-	-	-	1	-	-	Covered	T18,T30,T10
DetectSt	-	-	-	-	0	1	-	Covered	T22,T38,T49
DetectSt	-	-	-	-	0	0	-	Covered	T22,T18,T30
StableSt	-	-	-	-	-	-	1	Covered	T22,T38,T49
StableSt	-	-	-	-	-	-	0	Covered	T22,T38,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	3368	0	0
CntIncr_A	7461812	120093	0	0
CntNoWrap_A	7461812	6760147	0	0
DetectStDropOut_A	7461812	537	0	0
DetectedOut_A	7461812	64587	0	0
DetectedPulseOut_A	7461812	864	0	0
DisabledIdleSt_A	7461812	6326038	0	0
DisabledNoDetection_A	7461812	6328338	0	0
EnterDebounceSt_A	7461812	1735	0	0
EnterDetectSt_A	7461812	1634	0	0
EnterStableSt_A	7461812	864	0	0
PulseIsPulse_A	7461812	864	0	0
StayInStableSt	7461812	63668	0	0
gen_high_event_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	809	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3368	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	26	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	16	0	0
T22	6629	62	0	0
T23	494	0	0	0
T30	0	46	0	0
T38	0	56	0	0
T40	0	26	0	0
T49	0	48	0	0
T51	0	52	0	0
T80	0	28	0	0
T81	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	120093	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	840	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	401	0	0
T22	6629	1550	0	0
T23	494	0	0	0
T30	0	938	0	0
T38	0	1316	0	0
T40	0	1261	0	0
T49	0	1056	0	0
T51	0	1162	0	0
T80	0	1190	0	0
T81	0	593	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6760147	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6166	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	537	0	0
T7	6322	0	0	0
T18	5166	8	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	11	0	0
T50	8992	0	0	0
T51	0	26	0	0
T59	504	0	0	0
T60	432	0	0	0
T61	846	0	0	0
T81	0	6	0	0
T104	0	16	0	0
T108	0	27	0	0
T110	0	14	0	0
T111	0	5	0	0
T112	0	28	0	0
T262	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64587	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	1340	0	0
T23	494	0	0	0
T38	0	2221	0	0
T40	0	775	0	0
T49	0	1306	0	0
T80	0	1193	0	0
T98	0	225	0	0
T106	0	1376	0	0
T107	0	2811	0	0
T263	0	1721	0	0
T276	0	883	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	864	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	31	0	0
T23	494	0	0	0
T38	0	28	0	0
T40	0	13	0	0
T49	0	24	0	0
T80	0	14	0	0
T98	0	1	0	0
T106	0	16	0	0
T107	0	33	0	0
T263	0	8	0	0
T276	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6326038	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	2053	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6328338	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	2053	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1735	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	13	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	8	0	0
T22	6629	31	0	0
T23	494	0	0	0
T30	0	23	0	0
T38	0	28	0	0
T40	0	13	0	0
T49	0	24	0	0
T51	0	26	0	0
T80	0	14	0	0
T81	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	1634	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T10	0	13	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	8	0	0
T22	6629	31	0	0
T23	494	0	0	0
T30	0	23	0	0
T38	0	28	0	0
T40	0	13	0	0
T49	0	24	0	0
T51	0	26	0	0
T80	0	14	0	0
T81	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	864	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	31	0	0
T23	494	0	0	0
T38	0	28	0	0
T40	0	13	0	0
T49	0	24	0	0
T80	0	14	0	0
T98	0	1	0	0
T106	0	16	0	0
T107	0	33	0	0
T263	0	8	0	0
T276	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	864	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	31	0	0
T23	494	0	0	0
T38	0	28	0	0
T40	0	13	0	0
T49	0	24	0	0
T80	0	14	0	0
T98	0	1	0	0
T106	0	16	0	0
T107	0	33	0	0
T263	0	8	0	0
T276	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	63668	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	1309	0	0
T23	494	0	0	0
T38	0	2190	0	0
T40	0	761	0	0
T49	0	1281	0	0
T80	0	1179	0	0
T98	0	224	0	0
T106	0	1357	0	0
T107	0	2777	0	0
T263	0	1710	0	0
T276	0	856	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	809	0	0
T1	635	0	0	0
T2	16315	0	0	0
T3	693	0	0	0
T14	12958	0	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T22	6629	31	0	0
T23	494	0	0	0
T38	0	25	0	0
T40	0	12	0	0
T49	0	23	0	0
T80	0	14	0	0
T98	0	1	0	0
T106	0	13	0	0
T107	0	32	0	0
T263	0	5	0	0
T276	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T14,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T2,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T14,T2
1	0	Covered	T22,T14,T2
1	1	Covered	T14,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T15
0	1	Covered	T14,T2,T63
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T50,T8
0	1	Covered	T15,T50,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T50,T8
1	-	Covered	T15,T50,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T15
DetectSt	168	Covered	T14,T2,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T50,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T15
DebounceSt->IdleSt	163	Covered	T63,T107,T263
DetectSt->IdleSt	186	Covered	T14,T2,T63
DetectSt->StableSt	191	Covered	T15,T50,T8
IdleSt->DebounceSt	148	Covered	T14,T2,T15
StableSt->IdleSt	206	Covered	T15,T50,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T2,T15
0	1	Covered	T14,T2,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T107,T263
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T14,T2,T63
DetectSt	-	-	-	-	0	1	-	Covered	T15,T50,T8
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T15
StableSt	-	-	-	-	-	-	1	Covered	T15,T50,T8
StableSt	-	-	-	-	-	-	0	Covered	T15,T50,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	821	0	0
CntIncr_A	7461812	47712	0	0
CntNoWrap_A	7461812	6762694	0	0
DetectStDropOut_A	7461812	50	0	0
DetectedOut_A	7461812	17142	0	0
DetectedPulseOut_A	7461812	335	0	0
DisabledIdleSt_A	7461812	6364777	0	0
DisabledNoDetection_A	7461812	6366573	0	0
EnterDebounceSt_A	7461812	433	0	0
EnterDetectSt_A	7461812	389	0	0
EnterStableSt_A	7461812	335	0	0
PulseIsPulse_A	7461812	335	0	0
StayInStableSt	7461812	16798	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	821	0	0
T2	16315	2	0	0
T3	693	0	0	0
T8	0	6	0	0
T9	0	6	0	0
T12	0	14	0	0
T14	12958	8	0	0
T15	9729	4	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	6	0	0
T49	0	2	0	0
T50	0	4	0	0
T63	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	47712	0	0
T2	16315	156	0	0
T3	693	0	0	0
T8	0	141	0	0
T9	0	213	0	0
T12	0	546	0	0
T14	12958	663	0	0
T15	9729	180	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	138	0	0
T49	0	82	0	0
T50	0	162	0	0
T63	0	102	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6762694	0	0
T1	635	234	0	0
T2	16315	15071	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12530	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	50	0	0
T2	16315	1	0	0
T3	693	0	0	0
T14	12958	4	0	0
T15	9729	0	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T63	0	2	0	0
T117	0	2	0	0
T235	0	2	0	0
T266	0	6	0	0
T272	0	7	0	0
T277	0	2	0	0
T278	0	10	0	0
T279	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	17142	0	0
T8	0	13	0	0
T9	0	21	0	0
T12	0	53	0	0
T15	9729	13	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T38	0	261	0	0
T39	0	68	0	0
T40	0	50	0	0
T41	0	172	0	0
T49	0	45	0	0
T50	0	12	0	0
T59	504	0	0	0
T60	432	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	335	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	7	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6364777	0	0
T1	635	234	0	0
T2	16315	10163	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	8058	0	0
T21	504	103	0	0
T22	6629	4888	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6366573	0	0
T1	635	235	0	0
T2	16315	10164	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	8058	0	0
T21	504	104	0	0
T22	6629	4889	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	433	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	7	0	0
T14	12958	4	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T63	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	389	0	0
T2	16315	1	0	0
T3	693	0	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	7	0	0
T14	12958	4	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T38	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T63	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	335	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	7	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	335	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	7	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	16798	0	0
T8	0	10	0	0
T9	0	18	0	0
T12	0	46	0	0
T15	9729	11	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T38	0	258	0	0
T39	0	67	0	0
T40	0	49	0	0
T41	0	169	0	0
T49	0	43	0	0
T50	0	10	0	0
T59	504	0	0	0
T60	432	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	323	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	7	0	0
T15	9729	2	0	0
T16	522	0	0	0
T17	408	0	0	0
T18	5166	0	0	0
T19	527	0	0	0
T20	415	0	0	0
T29	34371	0	0	0
T30	5700	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T50	0	2	0	0
T59	504	0	0	0
T60	432	0	0	0
T106	0	3	0	0