Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1422806683	9732	0	0
auto_block_debounce_ctl_rd_A	1422806683	2219	0	0
auto_block_out_ctl_rd_A	1422806683	3108	0	0
com_det_ctl_0_rd_A	1422806683	4579	0	0
com_det_ctl_1_rd_A	1422806683	4752	0	0
com_det_ctl_2_rd_A	1422806683	4692	0	0
com_det_ctl_3_rd_A	1422806683	4608	0	0
com_out_ctl_0_rd_A	1422806683	5403	0	0
com_out_ctl_1_rd_A	1422806683	5435	0	0
com_out_ctl_2_rd_A	1422806683	5300	0	0
com_out_ctl_3_rd_A	1422806683	5414	0	0
com_pre_det_ctl_0_rd_A	1422806683	1913	0	0
com_pre_det_ctl_1_rd_A	1422806683	1804	0	0
com_pre_det_ctl_2_rd_A	1422806683	1998	0	0
com_pre_det_ctl_3_rd_A	1422806683	1844	0	0
com_pre_sel_ctl_0_rd_A	1422806683	5438	0	0
com_pre_sel_ctl_1_rd_A	1422806683	5701	0	0
com_pre_sel_ctl_2_rd_A	1422806683	5653	0	0
com_pre_sel_ctl_3_rd_A	1422806683	5837	0	0
com_sel_ctl_0_rd_A	1422806683	5394	0	0
com_sel_ctl_1_rd_A	1422806683	5404	0	0
com_sel_ctl_2_rd_A	1422806683	5585	0	0
com_sel_ctl_3_rd_A	1422806683	5706	0	0
ec_rst_ctl_rd_A	1422806683	3062	0	0
intr_enable_rd_A	1422806683	2477	0	0
key_intr_ctl_rd_A	1422806683	5095	0	0
key_intr_debounce_ctl_rd_A	1422806683	1752	0	0
key_invert_ctl_rd_A	1422806683	6158	0	0
pin_allowed_ctl_rd_A	1422806683	7169	0	0
pin_out_ctl_rd_A	1422806683	5626	0	0
pin_out_value_rd_A	1422806683	5869	0	0
regwen_rd_A	1422806683	2115	0	0
ulp_ac_debounce_ctl_rd_A	1422806683	1804	0	0
ulp_ctl_rd_A	1422806683	1892	0	0
ulp_lid_debounce_ctl_rd_A	1422806683	1992	0	0
ulp_pwrb_debounce_ctl_rd_A	1422806683	1954	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	9732	0	0
T7	309841	7	0	0
T8	618519	19	0	0
T9	112841	0	0	0
T10	314350	0	0	0
T11	125820	0	0	0
T13	0	12	0	0
T27	0	16	0	0
T42	0	13	0	0
T62	100581	0	0	0
T69	57616	0	0	0
T70	51118	0	0	0
T71	200278	0	0	0
T72	56378	0	0	0
T85	0	12	0	0
T109	0	16	0	0
T115	0	11	0	0
T117	0	3	0	0
T313	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	2219	0	0
T27	166064	0	0	0
T42	0	38	0	0
T46	115779	0	0	0
T53	61087	9	0	0
T54	316899	0	0	0
T55	325613	0	0	0
T56	330006	0	0	0
T66	286571	0	0	0
T75	237049	0	0	0
T85	0	40	0	0
T115	0	9	0	0
T116	0	14	0	0
T117	0	19	0	0
T192	0	12	0	0
T205	0	10	0	0
T309	0	24	0	0
T314	0	1	0	0
T315	60935	0	0	0
T316	200541	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	3108	0	0
T27	166064	0	0	0
T42	0	29	0	0
T46	115779	0	0	0
T53	61087	3	0	0
T54	316899	0	0	0
T55	325613	0	0	0
T56	330006	0	0	0
T66	286571	0	0	0
T75	237049	0	0	0
T85	0	31	0	0
T115	0	28	0	0
T116	0	9	0	0
T117	0	19	0	0
T192	0	4	0	0
T205	0	11	0	0
T309	0	13	0	0
T314	0	7	0	0
T315	60935	0	0	0
T316	200541	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	4579	0	0
T1	317693	0	0	0
T2	815799	78	0	0
T3	57231	0	0	0
T10	0	35	0	0
T14	628533	66	0	0
T15	340531	71	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	38	0	0
T23	61718	0	0	0
T38	0	68	0	0
T42	0	47	0	0
T50	0	33	0	0
T63	0	87	0	0
T64	0	77	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	4752	0	0
T1	317693	0	0	0
T2	815799	76	0	0
T3	57231	0	0	0
T10	0	55	0	0
T14	628533	84	0	0
T15	340531	77	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	57	0	0
T23	61718	0	0	0
T38	0	96	0	0
T42	0	36	0	0
T50	0	27	0	0
T63	0	80	0	0
T64	0	82	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	4692	0	0
T1	317693	0	0	0
T2	815799	75	0	0
T3	57231	0	0	0
T10	0	34	0	0
T14	628533	67	0	0
T15	340531	75	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	43	0	0
T23	61718	0	0	0
T38	0	65	0	0
T42	0	62	0	0
T50	0	54	0	0
T63	0	71	0	0
T64	0	68	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	4608	0	0
T1	317693	0	0	0
T2	815799	67	0	0
T3	57231	0	0	0
T10	0	37	0	0
T14	628533	64	0	0
T15	340531	68	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	54	0	0
T23	61718	0	0	0
T38	0	72	0	0
T42	0	34	0	0
T50	0	28	0	0
T63	0	77	0	0
T64	0	46	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5403	0	0
T1	317693	0	0	0
T2	815799	67	0	0
T3	57231	0	0	0
T10	0	29	0	0
T14	628533	63	0	0
T15	340531	72	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	37	0	0
T23	61718	0	0	0
T38	0	78	0	0
T42	0	38	0	0
T50	0	40	0	0
T63	0	68	0	0
T64	0	62	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5435	0	0
T1	317693	0	0	0
T2	815799	61	0	0
T3	57231	0	0	0
T10	0	46	0	0
T14	628533	60	0	0
T15	340531	78	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	43	0	0
T23	61718	0	0	0
T38	0	75	0	0
T42	0	54	0	0
T50	0	45	0	0
T63	0	69	0	0
T64	0	79	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5300	0	0
T1	317693	0	0	0
T2	815799	70	0	0
T3	57231	0	0	0
T10	0	53	0	0
T14	628533	100	0	0
T15	340531	82	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	30	0	0
T23	61718	0	0	0
T38	0	59	0	0
T42	0	39	0	0
T50	0	34	0	0
T63	0	65	0	0
T64	0	61	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5414	0	0
T1	317693	0	0	0
T2	815799	80	0	0
T3	57231	0	0	0
T10	0	65	0	0
T14	628533	90	0	0
T15	340531	64	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	23	0	0
T23	61718	0	0	0
T38	0	63	0	0
T42	0	47	0	0
T50	0	46	0	0
T63	0	56	0	0
T64	0	47	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1913	0	0
T42	426451	26	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	23	0	0
T97	0	17	0	0
T115	217737	16	0	0
T117	0	15	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T142	0	32	0	0
T188	0	50	0	0
T205	0	12	0	0
T228	0	20	0	0
T317	0	15	0	0
T318	14040	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1804	0	0
T42	426451	35	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	16	0	0
T97	0	8	0	0
T115	217737	11	0	0
T117	0	12	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T142	0	17	0	0
T188	0	19	0	0
T205	0	12	0	0
T228	0	20	0	0
T317	0	13	0	0
T318	14040	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1998	0	0
T42	426451	39	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	24	0	0
T97	0	30	0	0
T115	217737	20	0	0
T117	0	15	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T142	0	22	0	0
T188	0	31	0	0
T205	0	4	0	0
T228	0	45	0	0
T317	0	17	0	0
T318	14040	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1844	0	0
T42	426451	38	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	19	0	0
T97	0	13	0	0
T115	217737	11	0	0
T117	0	13	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T142	0	27	0	0
T188	0	26	0	0
T205	0	15	0	0
T228	0	20	0	0
T317	0	18	0	0
T318	14040	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5438	0	0
T1	317693	0	0	0
T2	815799	66	0	0
T3	57231	0	0	0
T10	0	59	0	0
T14	628533	91	0	0
T15	340531	62	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	41	0	0
T23	61718	0	0	0
T38	0	51	0	0
T42	0	23	0	0
T50	0	51	0	0
T63	0	66	0	0
T64	0	68	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5701	0	0
T1	317693	0	0	0
T2	815799	76	0	0
T3	57231	0	0	0
T10	0	46	0	0
T14	628533	69	0	0
T15	340531	65	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	39	0	0
T23	61718	0	0	0
T38	0	75	0	0
T42	0	29	0	0
T50	0	35	0	0
T63	0	62	0	0
T64	0	76	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5653	0	0
T1	317693	0	0	0
T2	815799	48	0	0
T3	57231	0	0	0
T10	0	37	0	0
T14	628533	63	0	0
T15	340531	52	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	41	0	0
T23	61718	0	0	0
T38	0	56	0	0
T42	0	26	0	0
T50	0	30	0	0
T63	0	73	0	0
T64	0	66	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5837	0	0
T1	317693	0	0	0
T2	815799	60	0	0
T3	57231	0	0	0
T10	0	42	0	0
T14	628533	61	0	0
T15	340531	75	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	42	0	0
T23	61718	0	0	0
T38	0	62	0	0
T42	0	38	0	0
T50	0	54	0	0
T63	0	71	0	0
T64	0	92	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5394	0	0
T1	317693	0	0	0
T2	815799	73	0	0
T3	57231	0	0	0
T10	0	50	0	0
T14	628533	63	0	0
T15	340531	65	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	41	0	0
T23	61718	0	0	0
T38	0	66	0	0
T42	0	19	0	0
T50	0	40	0	0
T63	0	73	0	0
T64	0	78	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5404	0	0
T1	317693	0	0	0
T2	815799	67	0	0
T3	57231	0	0	0
T10	0	44	0	0
T14	628533	51	0	0
T15	340531	59	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	42	0	0
T23	61718	0	0	0
T38	0	107	0	0
T42	0	33	0	0
T50	0	47	0	0
T63	0	74	0	0
T64	0	92	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5585	0	0
T1	317693	0	0	0
T2	815799	70	0	0
T3	57231	0	0	0
T10	0	36	0	0
T14	628533	78	0	0
T15	340531	74	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	30	0	0
T23	61718	0	0	0
T38	0	64	0	0
T42	0	36	0	0
T50	0	30	0	0
T63	0	71	0	0
T64	0	65	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5706	0	0
T1	317693	0	0	0
T2	815799	92	0	0
T3	57231	0	0	0
T10	0	54	0	0
T14	628533	77	0	0
T15	340531	81	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T22	331433	45	0	0
T23	61718	0	0	0
T38	0	71	0	0
T42	0	31	0	0
T50	0	44	0	0
T63	0	68	0	0
T64	0	92	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	3062	0	0
T2	815799	11	0	0
T3	57231	0	0	0
T10	0	18	0	0
T14	628533	19	0	0
T15	340531	10	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T19	65857	0	0	0
T20	68590	0	0	0
T29	360896	0	0	0
T38	0	34	0	0
T42	0	37	0	0
T49	0	8	0	0
T50	0	2	0	0
T63	0	37	0	0
T64	0	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	2477	0	0
T28	243851	0	0	0
T42	426451	57	0	0
T46	115779	12	0	0
T48	0	20	0	0
T49	482958	0	0	0
T57	347920	0	0	0
T58	522923	0	0	0
T85	0	56	0	0
T97	0	39	0	0
T115	217737	40	0	0
T117	0	31	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T141	0	17	0	0
T188	0	56	0	0
T203	99740	0	0	0
T205	0	19	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5095	0	0
T28	243851	0	0	0
T42	426451	40	0	0
T46	115779	3	0	0
T48	0	8	0	0
T49	482958	0	0	0
T57	347920	0	0	0
T58	522923	0	0	0
T85	0	6	0	0
T115	217737	6	0	0
T117	0	9	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T174	0	2	0	0
T175	0	1	0	0
T192	0	2	0	0
T203	99740	0	0	0
T205	0	4	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1752	0	0
T42	426451	30	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	15	0	0
T97	0	24	0	0
T115	217737	14	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T142	0	25	0	0
T188	0	37	0	0
T205	0	4	0	0
T228	0	30	0	0
T317	0	18	0	0
T318	14040	0	0	0
T319	0	1	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	6158	0	0
T2	815799	77	0	0
T3	57231	0	0	0
T15	340531	0	0	0
T16	261022	0	0	0
T17	42888	0	0	0
T18	258292	0	0	0
T19	65857	0	0	0
T20	68590	0	0	0
T29	360896	0	0	0
T42	0	35	0	0
T48	0	63	0	0
T59	63130	0	0	0
T74	0	64	0	0
T75	0	68	0	0
T78	0	51	0	0
T85	0	136	0	0
T115	0	14	0	0
T117	0	36	0	0
T219	0	80	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	7169	0	0
T42	426451	153	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	153	0	0
T115	217737	94	0	0
T117	0	62	0	0
T122	241155	62	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T216	0	91	0	0
T318	14040	66	0	0
T320	0	49	0	0
T321	0	74	0	0
T322	0	97	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5626	0	0
T42	426451	138	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	131	0	0
T115	217737	79	0	0
T117	0	31	0	0
T122	241155	50	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T216	0	62	0	0
T318	14040	34	0	0
T320	0	40	0	0
T321	0	60	0	0
T322	0	84	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	5869	0	0
T42	426451	205	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	161	0	0
T115	217737	89	0	0
T117	0	66	0	0
T122	241155	60	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T216	0	55	0	0
T318	14040	75	0	0
T320	0	51	0	0
T321	0	87	0	0
T322	0	77	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	2115	0	0
T42	426451	46	0	0
T49	482958	0	0	0
T58	522923	0	0	0
T76	59857	0	0	0
T85	0	9	0	0
T97	0	20	0	0
T115	217737	7	0	0
T117	0	3	0	0
T122	241155	0	0	0
T123	304582	0	0	0
T124	209150	0	0	0
T125	181665	0	0	0
T142	0	27	0	0
T188	0	35	0	0
T205	0	7	0	0
T228	0	29	0	0
T317	0	17	0	0
T318	14040	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1804	0	0
T13	380225	0	0	0
T36	29231	3	0	0
T37	35876	1	0	0
T38	105716	0	0	0
T42	0	32	0	0
T48	0	1	0	0
T51	584682	0	0	0
T52	321556	0	0	0
T63	346072	0	0	0
T64	684714	0	0	0
T65	0	5	0	0
T85	0	30	0	0
T115	0	5	0	0
T117	0	4	0	0
T157	48690	0	0	0
T205	0	9	0	0
T323	0	14	0	0
T324	128221	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1892	0	0
T13	380225	0	0	0
T36	29231	8	0	0
T37	35876	0	0	0
T38	105716	0	0	0
T42	0	56	0	0
T48	0	4	0	0
T51	584682	0	0	0
T52	321556	0	0	0
T63	346072	0	0	0
T64	684714	0	0	0
T65	0	3	0	0
T85	0	24	0	0
T86	0	6	0	0
T115	0	14	0	0
T117	0	21	0	0
T157	48690	0	0	0
T205	0	12	0	0
T323	0	9	0	0
T324	128221	0	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1992	0	0
T13	380225	0	0	0
T36	29231	2	0	0
T37	35876	3	0	0
T38	105716	0	0	0
T42	0	47	0	0
T48	0	3	0	0
T51	584682	0	0	0
T52	321556	0	0	0
T63	346072	0	0	0
T64	684714	0	0	0
T85	0	28	0	0
T86	0	3	0	0
T115	0	14	0	0
T117	0	13	0	0
T157	48690	0	0	0
T205	0	7	0	0
T323	0	6	0	0
T324	128221	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422806683	1954	0	0
T13	380225	0	0	0
T36	29231	1	0	0
T37	35876	6	0	0
T38	105716	0	0	0
T42	0	29	0	0
T48	0	9	0	0
T51	584682	0	0	0
T52	321556	0	0	0
T63	346072	0	0	0
T64	684714	0	0	0
T65	0	2	0	0
T85	0	19	0	0
T115	0	12	0	0
T117	0	6	0	0
T157	48690	0	0	0
T205	0	18	0	0
T323	0	11	0	0
T324	128221	0	0	0