SYSRST_CTRL Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.350s	2.108ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.390s	2.475ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.080s	2.436ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.390s	2.367ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.930s	6.030ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.130s	2.049ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.912m	74.905ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	13.870s	3.150ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.470s	2.104ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.130s	2.049ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.870s	3.150ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	9.011m	197.788ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	5.318m	124.361ms	93	100	93.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	24.485m	568.418ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	50.840s	789.511ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.550s	2.509ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.700s	2.224ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	19.484m	987.869ms	49	50	98.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	8.220s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.803m	967.615ms	43	50	86.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.498m	35.667ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	47.652m	1.090s	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	6.350s	2.010ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.160s	2.012ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.780s	2.094ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.780s	2.094ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.930s	6.030ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.130s	2.049ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.870s	3.150ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	26.260s	7.453ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.930s	6.030ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.130s	2.049ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.870s	3.150ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	26.260s	7.453ms	20	20	100.00
V2		TOTAL			676	692	97.69
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.291m	42.013ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.783m	42.437ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.783m	42.437ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.710m	2.803s	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			912	932	97.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.29	96.38	100.00	96.79	98.71	99.52	93.35

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 8 failures:

Test sysrst_ctrl_ultra_low_pwr has 7 failures.

7.sysrst_ctrl_ultra_low_pwr.21645783726785333617401922632438771544994246286453837272773459479388634584220
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2261961076 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2479461076 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_ERROR @ 3881961076 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3881961076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.sysrst_ctrl_ultra_low_pwr.63531723501036401817073878380256229490006351666181842611642280074962861698632
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2144848422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2162348422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 3742348422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 5532348422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 5609060694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 5 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

28.sysrst_ctrl_stress_all_with_rand_reset.42295263133494783625822013020390919890156945787488817436672984729478586667173
Line 651, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43575758137 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 45728258137 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 45728258137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 3 failures.

63.sysrst_ctrl_combo_detect_with_pre_cond.20186264321898340513865886746645930135892018641023139051810679851254166349850
Line 586, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 26677442308 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 26762442308 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 26782442308 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 36919443397 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x1b
  UVM_INFO @ 36919567105 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x24

71.sysrst_ctrl_combo_detect_with_pre_cond.38746016393885674441416369752533908084895507379338983404114618947079305682732
Line 596, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 94398222870 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 94398222870 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 94398222870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.sysrst_ctrl_stress_all_with_rand_reset.115573746372144482336663694145200022029338279615111924315117172028338112617860
    Line 670, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 84710098461 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 84710098461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 47.sysrst_ctrl_ec_pwr_on_rst.15681564228505705889847094919628512460953632048241533148681916292343893325123
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 3418859882 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 3418859882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

33.sysrst_ctrl_combo_detect_with_pre_cond.53421287048095947415359985693414982022352960515828705320532516866173991669440
Line 632, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 86839289822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 86839289822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 86839289822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

57.sysrst_ctrl_combo_detect_with_pre_cond.26829561050403122202832181723799646804085961401944586550830949692624381324852
Line 579, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 26022730971 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 26022730971 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 26022730971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 1.sysrst_ctrl_stress_all.111273671721346447021422706158568148640005529489312310147545024932035465094269
    Line 563, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 6629239735 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 6933905203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

11.sysrst_ctrl_stress_all_with_rand_reset.100748418312853551622766018701198186699621790519677533500009018134384270483714
Line 630, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28193178021 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 28209307099 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 7/10
  UVM_INFO @ 28211464117 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 28212231793 ps: (cip_base_vseq.sv:717) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 8/10

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

15.sysrst_ctrl_combo_detect_with_pre_cond.15903063868045979729449393857668255796862984077759490923625963713915788080258
Line 577, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 16073615168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-4
  UVM_ERROR @ 16073615168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
  UVM_INFO @ 16073615168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

39.sysrst_ctrl_combo_detect_with_pre_cond.109192034000196514715715035231297958278560533388056388645382221349127709542361
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 32437166439 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4
  UVM_INFO @ 32442166439 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 32582166439 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 32602166439 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 33228292344 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

49.sysrst_ctrl_stress_all_with_rand_reset.41217422758676483224112026856498329453763390239927158677740951479910368502311
Line 617, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 81593449310 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 81593449310 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 81593449310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---