SYSRST_CTRL Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.210s 2.110ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.220s 2.467ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.680s 2.422ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.930s 2.302ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.280s 4.012ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.580s 2.050ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.595m 37.983ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 8.960s 2.672ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.840s 2.116ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.580s 2.050ms 20 20 100.00
sysrst_ctrl_csr_aliasing 8.960s 2.672ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 8.502m 187.790ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 5.711m 132.518ms 96 100 96.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 13.476m 297.490ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 22.728m 1.097s 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.820s 2.510ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.870s 2.238ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 9.367m 233.584ms 49 50 98.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.830s 2.609ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.610m 784.351ms 47 50 94.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.554m 38.313ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 10.200m 798.555ms 50 50 100.00
V2 alert_test sysrst_ctrl_alert_test 6.180s 2.013ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.350s 2.015ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.830s 2.038ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.830s 2.038ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.280s 4.012ms 5 5 100.00
sysrst_ctrl_csr_rw 6.580s 2.050ms 20 20 100.00
sysrst_ctrl_csr_aliasing 8.960s 2.672ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 37.410s 10.727ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.280s 4.012ms 5 5 100.00
sysrst_ctrl_csr_rw 6.580s 2.050ms 20 20 100.00
sysrst_ctrl_csr_aliasing 8.960s 2.672ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 37.410s 10.727ms 20 20 100.00
V2 TOTAL 684 692 98.84
V2S tl_intg_err sysrst_ctrl_sec_cm 55.070s 42.023ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.866m 42.399ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.866m 42.399ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.248m 1.242s 38 50 76.00
V3 TOTAL 38 50 76.00
TOTAL 912 932 97.85

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.90 98.92 96.89 100.00 97.44 98.37 99.81 93.85

Failure Buckets

Past Results