Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1286

1

T1

35

T4

34

T22

12

auto[1]

1253

1

T1

24

T4

46

T22

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

628

1

T1

13

T4

20

T22

5

from_0to1

628

1

T1

13

T4

20

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1306

1

T1

23

T4

43

T22

14

auto[1]

1233

1

T1

36

T4

37

T22

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1242

1

T1

32

T4

42

T22

7

auto[1]

1297

1

T1

27

T4

38

T22

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T1

1

T4

4

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

98

1

T1

5

T4

3

T22

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T1

2

T4

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T4

1

T69

1

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T1

1

T4

3

T22

2

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T1

1

T4

1

T9

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T1

4

T4

1

T69

2

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T1

3

T4

3

T325

2

auto[1]

from_1to0

auto[0]

auto[0]

82

1

T1

1

T4

2

T9

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T4

3

T22

1

T74

1

auto[1]

from_1to0

auto[1]

auto[0]

86

1

T1

3

T4

5

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T1

1

T4

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

85

1

T1

1

T4

6

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

81

1

T4

3

T22

1

T69

3

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T1

2

T4

1

T69

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T1

1

T4

2

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1286

1

T1

24

T4

44

T22

12

auto[1]

1253

1

T1

35

T4

36

T22

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

607

1

T1

17

T4

21

T22

3

from_0to1

608

1

T1

16

T4

21

T22

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T1

33

T4

25

T22

8

auto[1]

1336

1

T1

26

T4

55

T22

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1236

1

T1

27

T4

38

T22

9

auto[1]

1303

1

T1

32

T4

42

T22

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T1

3

T69

1

T9

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T1

4

T4

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T4

5

T73

1

T323

1

auto[0]

from_1to0

auto[1]

auto[1]

92

1

T1

5

T4

4

T22

2

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T4

1

T22

2

T9

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T1

2

T4

3

T9

1

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T1

1

T4

2

T325

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T4

2

T69

1

T9

2

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T1

2

T4

2

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

86

1

T1

2

T4

1

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T4

4

T22

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T1

1

T4

4

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T1

3

T4

4

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T1

3

T4

2

T74

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T1

3

T4

3

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T1

4

T4

4

T69

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1232

1

T1

33

T4

40

T22

10

auto[1]

1307

1

T1

26

T4

40

T22

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

603

1

T1

16

T4

20

T22

6

from_0to1

598

1

T1

16

T4

20

T22

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1266

1

T1

30

T4

30

T22

9

auto[1]

1273

1

T1

29

T4

50

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1277

1

T1

26

T4

42

T22

10

auto[1]

1262

1

T1

33

T4

38

T22

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T1

1

T4

1

T323

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T1

2

T69

2

T9

2

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T1

2

T4

8

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T1

3

T22

2

T9

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T1

2

T22

1

T69

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T1

3

T4

3

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T4

4

T22

1

T9

2

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T1

1

T4

4

T69

3

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T1

1

T4

4

T69

2

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T1

2

T4

2

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T1

2

T4

1

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T1

3

T4

4

T9

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T1

1

T4

3

T9

2

auto[1]

from_0to1

auto[0]

auto[1]

96

1

T1

6

T4

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T1

1

T4

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T1

2

T4

4

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1276

1

T1

32

T4

38

T22

11

auto[1]

1263

1

T1

27

T4

42

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

613

1

T1

14

T4

19

T22

5

from_0to1

619

1

T1

14

T4

19

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1276

1

T1

35

T4

46

T22

9

auto[1]

1263

1

T1

24

T4

34

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1277

1

T1

29

T4

40

T22

11

auto[1]

1262

1

T1

30

T4

40

T22

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T1

3

T4

3

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T1

2

T4

2

T9

1

auto[0]

from_1to0

auto[1]

auto[0]

84

1

T1

2

T4

3

T22

2

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T1

1

T4

4

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T4

4

T22

1

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

88

1

T1

4

T4

3

T69

2

auto[0]

from_0to1

auto[1]

auto[0]

92

1

T22

1

T69

1

T74

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T4

1

T9

2

T73

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T1

1

T4

1

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T1

3

T4

3

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T1

1

T73

2

T323

1

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T1

1

T4

3

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T1

1

T4

3

T69

2

auto[1]

from_0to1

auto[0]

auto[1]

78

1

T1

2

T4

3

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T1

4

T4

4

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T1

3

T4

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1278

1

T1

29

T4

43

T22

13

auto[1]

1261

1

T1

30

T4

37

T22

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

612

1

T1

13

T4

19

T22

5

from_0to1

610

1

T1

13

T4

20

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1265

1

T1

27

T4

48

T22

13

auto[1]

1274

1

T1

32

T4

32

T22

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1341

1

T1

41

T4

46

T22

15

auto[1]

1198

1

T1

18

T4

34

T22

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

89

1

T1

1

T4

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T4

1

T22

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T1

2

T4

1

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T1

1

T4

3

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

81

1

T1

2

T4

4

T22

3

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T1

1

T4

6

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T1

1

T4

1

T22

1

auto[0]

from_0to1

auto[1]

auto[1]

84

1

T1

3

T4

2

T9

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T1

1

T4

5

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T1

2

T4

2

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

91

1

T1

4

T4

5

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T1

2

T4

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

90

1

T1

2

T4

2

T9

3

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T4

1

T9

1

T323

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T1

2

T4

3

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T1

2

T4

1

T325

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1294

1

T1

24

T4

42

T22

11

auto[1]

1245

1

T1

35

T4

38

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

602

1

T1

15

T4

19

T22

6

from_0to1

598

1

T1

14

T4

20

T22

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1273

1

T1

31

T4

47

T22

10

auto[1]

1266

1

T1

28

T4

33

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1264

1

T1

31

T4

41

T22

12

auto[1]

1275

1

T1

28

T4

39

T22

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T1

3

T4

4

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T4

1

T69

1

T74

3

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T1

3

T4

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T1

2

T4

2

T73

2

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T4

2

T22

1

T323

2

auto[0]

from_0to1

auto[0]

auto[1]

92

1

T1

4

T4

6

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T1

3

T4

3

T74

2

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T4

1

T22

2

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T1

1

T4

4

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T1

3

T4

1

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

83

1

T1

2

T4

3

T22

3

auto[1]

from_1to0

auto[1]

auto[1]

83

1

T1

1

T4

3

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T4

2

T73

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T1

1

T4

3

T9

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T1

2

T4

3

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T1

4

T22

1

T69

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1247

1

T1

29

T4

43

T22

13

auto[1]

1292

1

T1

30

T4

37

T22

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

601

1

T1

17

T4

18

T22

4

from_0to1

582

1

T1

16

T4

17

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1270

1

T1

30

T4

31

T22

11

auto[1]

1269

1

T1

29

T4

49

T22

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1255

1

T1

31

T4

38

T22

10

auto[1]

1284

1

T1

28

T4

42

T22

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T1

1

T4

1

T22

2

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T1

2

T4

2

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T1

6

T4

5

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T4

4

T22

1

T325

3

auto[0]

from_0to1

auto[0]

auto[0]

85

1

T1

2

T4

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T1

2

T4

2

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T1

1

T4

1

T74

2

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T1

2

T4

3

T69

3

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T1

1

T4

2

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

86

1

T1

3

T4

2

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T1

1

T4

2

T69

2

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T1

3

T73

1

T323

2

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T1

4

T4

1

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T1

1

T4

3

T22

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T4

3

T9

2

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

86

1

T1

4

T4

3

T69

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1258

1

T1

35

T4

35

T22

11

auto[1]

1281

1

T1

24

T4

45

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

607

1

T1

15

T4

21

T22

5

from_0to1

604

1

T1

14

T4

21

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1255

1

T1

27

T4

36

T22

11

auto[1]

1284

1

T1

32

T4

44

T22

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T1

29

T4

33

T22

7

auto[1]

1267

1

T1

30

T4

47

T22

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

88

1

T1

1

T4

2

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T1

2

T4

4

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T1

2

T4

2

T69

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T1

2

T4

2

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T1

3

T4

1

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T1

2

T4

3

T22

2

auto[0]

from_0to1

auto[1]

auto[0]

89

1

T1

3

T4

1

T69

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T1

1

T4

5

T323

1

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T1

2

T4

3

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T1

1

T4

3

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T4

2

T323

1

T138

1

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T1

5

T4

3

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

80

1

T1

2

T4

2

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T1

2

T4

1

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T4

3

T22

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T1

1

T4

5

T22

1