Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120299

1

T5

281

T1

402

T2

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142092	1			T5	393		T1	576		T2	9
values[0x0]	65840	1			T5	87		T1	137		T12	219
values[0x1]	66462	1			T5	79		T1	150		T2	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149622

1

T5

335

T1

476

T2

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1020	1			T1	1		T4	10		T7	22
valid_sources[0x01]	2127	1			T7	6		T22	2		T38	2
valid_sources[0x02]	1233	1			T4	3		T7	1		T22	2
valid_sources[0x03]	1027	1			T1	2		T4	2		T7	4
valid_sources[0x04]	813	1			T6	3		T4	6		T7	5
valid_sources[0x05]	1743	1			T4	20		T22	1		T53	1
valid_sources[0x06]	879	1			T1	18		T4	2		T69	1
valid_sources[0x07]	1049	1			T4	3		T38	3		T63	1
valid_sources[0x08]	903	1			T4	11		T7	9		T38	2
valid_sources[0x09]	1725	1			T4	1		T7	9		T69	3
valid_sources[0x0a]	902	1			T1	4		T69	2		T71	1
valid_sources[0x0b]	879	1			T38	4		T37	17		T10	2
valid_sources[0x0c]	714	1			T4	3		T7	2		T22	1
valid_sources[0x0d]	2109	1			T4	15		T7	11		T22	1
valid_sources[0x0e]	976	1			T4	1		T22	1		T38	2
valid_sources[0x0f]	828	1			T4	5		T7	16		T22	1
valid_sources[0x10]	1066	1			T1	54		T38	1		T9	1
valid_sources[0x11]	1030	1			T1	10		T4	5		T38	5
valid_sources[0x12]	1047	1			T13	2		T50	3		T7	5
valid_sources[0x13]	1320	1			T1	7		T4	6		T7	1
valid_sources[0x14]	809	1			T4	6		T7	9		T69	1
valid_sources[0x15]	881	1			T1	3		T4	7		T22	1
valid_sources[0x16]	1014	1			T4	2		T7	6		T22	1
valid_sources[0x17]	898	1			T7	2		T69	2		T38	5
valid_sources[0x18]	1331	1			T1	22		T4	7		T7	5
valid_sources[0x19]	963	1			T16	1		T4	3		T38	5
valid_sources[0x1a]	761	1			T4	9		T22	3		T38	2
valid_sources[0x1b]	1337	1			T7	4		T69	2		T38	4
valid_sources[0x1c]	1778	1			T38	4		T72	3		T9	2
valid_sources[0x1d]	1075	1			T1	3		T4	2		T38	2
valid_sources[0x1e]	707	1			T38	5		T28	1		T64	2
valid_sources[0x1f]	1434	1			T4	5		T7	5		T22	1
valid_sources[0x20]	946	1			T1	2		T4	3		T7	8
valid_sources[0x21]	1011	1			T4	6		T7	12		T38	3
valid_sources[0x22]	1034	1			T8	2		T69	1		T38	5
valid_sources[0x23]	1021	1			T4	15		T7	8		T69	1
valid_sources[0x24]	2138	1			T4	9		T22	2		T38	9
valid_sources[0x25]	958	1			T4	8		T69	1		T38	2
valid_sources[0x26]	863	1			T1	4		T4	9		T69	1
valid_sources[0x27]	838	1			T16	1		T69	1		T38	4
valid_sources[0x28]	1121	1			T1	38		T4	9		T7	3
valid_sources[0x29]	912	1			T4	42		T7	6		T22	1
valid_sources[0x2a]	1179	1			T1	17		T4	5		T7	3
valid_sources[0x2b]	1076	1			T4	4		T69	1		T38	1
valid_sources[0x2c]	1591	1			T1	6		T4	7		T7	2
valid_sources[0x2d]	777	1			T7	10		T288	2		T38	4
valid_sources[0x2e]	852	1			T4	2		T7	5		T38	3
valid_sources[0x2f]	827	1			T1	8		T4	3		T7	1
valid_sources[0x30]	887	1			T4	33		T69	2		T38	3
valid_sources[0x31]	960	1			T4	21		T7	15		T8	1
valid_sources[0x32]	904	1			T1	6		T4	20		T7	10
valid_sources[0x33]	933	1			T7	9		T8	1		T38	6
valid_sources[0x34]	1026	1			T4	3		T7	15		T8	1
valid_sources[0x35]	2185	1			T49	18		T69	1		T38	8
valid_sources[0x36]	764	1			T4	15		T22	1		T38	1
valid_sources[0x37]	773	1			T4	11		T70	8		T38	5
valid_sources[0x38]	802	1			T4	2		T22	1		T69	3
valid_sources[0x39]	897	1			T4	9		T7	13		T22	2
valid_sources[0x3a]	1855	1			T4	4		T7	22		T8	1
valid_sources[0x3b]	954	1			T1	2		T4	3		T7	11
valid_sources[0x3c]	942	1			T1	1		T4	21		T8	1
valid_sources[0x3d]	2058	1			T1	5		T3	1183		T4	18
valid_sources[0x3e]	919	1			T22	1		T69	1		T38	7
valid_sources[0x3f]	1333	1			T1	12		T4	31		T22	1
valid_sources[0x40]	1183	1			T1	3		T22	1		T69	1
valid_sources[0x41]	928	1			T1	13		T4	16		T38	8
valid_sources[0x42]	891	1			T4	24		T7	10		T69	1
valid_sources[0x43]	1378	1			T4	10		T38	3		T71	1
valid_sources[0x44]	749	1			T1	13		T14	3		T4	7
valid_sources[0x45]	931	1			T1	20		T4	8		T7	2
valid_sources[0x46]	953	1			T4	7		T22	2		T69	1
valid_sources[0x47]	898	1			T4	4		T38	3		T21	9
valid_sources[0x48]	797	1			T4	9		T7	6		T8	2
valid_sources[0x49]	911	1			T4	2		T54	2		T69	1
valid_sources[0x4a]	1228	1			T4	3		T7	17		T69	2
valid_sources[0x4b]	943	1			T7	3		T38	2		T63	1
valid_sources[0x4c]	1006	1			T1	9		T8	3		T38	1
valid_sources[0x4d]	970	1			T7	6		T63	1		T9	1
valid_sources[0x4e]	835	1			T4	1		T7	12		T69	1
valid_sources[0x4f]	880	1			T4	4		T7	19		T38	1
valid_sources[0x50]	919	1			T4	4		T7	9		T38	2
valid_sources[0x51]	899	1			T1	27		T4	6		T22	3
valid_sources[0x52]	1080	1			T4	20		T7	2		T69	1
valid_sources[0x53]	933	1			T1	1		T70	8		T112	1
valid_sources[0x54]	993	1			T4	4		T7	1		T69	1
valid_sources[0x55]	1229	1			T4	1		T38	2		T72	1
valid_sources[0x56]	847	1			T15	17		T4	2		T69	2
valid_sources[0x57]	1186	1			T4	9		T38	10		T63	1
valid_sources[0x58]	1506	1			T1	3		T7	18		T22	1
valid_sources[0x59]	865	1			T4	6		T8	1		T22	2
valid_sources[0x5a]	863	1			T4	9		T7	1		T8	1
valid_sources[0x5b]	1205	1			T1	9		T4	8		T7	19
valid_sources[0x5c]	811	1			T4	5		T7	13		T22	1
valid_sources[0x5d]	944	1			T7	18		T38	2		T37	16
valid_sources[0x5e]	1086	1			T4	4		T38	4		T37	7
valid_sources[0x5f]	830	1			T4	23		T69	1		T70	7
valid_sources[0x60]	1058	1			T1	2		T4	23		T52	50
valid_sources[0x61]	930	1			T4	5		T22	1		T38	3
valid_sources[0x62]	910	1			T69	1		T38	6		T63	2
valid_sources[0x63]	867	1			T38	2		T63	4		T9	2
valid_sources[0x64]	1142	1			T1	2		T54	1		T38	2
valid_sources[0x65]	916	1			T1	4		T4	5		T22	1
valid_sources[0x66]	937	1			T1	9		T4	6		T69	2
valid_sources[0x67]	815	1			T1	11		T4	4		T38	1
valid_sources[0x68]	1369	1			T7	7		T8	1		T22	1
valid_sources[0x69]	946	1			T4	26		T7	4		T22	1
valid_sources[0x6a]	869	1			T4	2		T22	1		T70	2
valid_sources[0x6b]	1106	1			T4	1		T38	4		T9	2
valid_sources[0x6c]	1128	1			T1	2		T4	3		T7	1
valid_sources[0x6d]	914	1			T1	5		T7	8		T38	3
valid_sources[0x6e]	893	1			T1	9		T7	7		T22	1
valid_sources[0x6f]	809	1			T4	6		T69	1		T38	6
valid_sources[0x70]	2196	1			T4	5		T22	3		T38	5
valid_sources[0x71]	833	1			T38	3		T41	7		T10	3
valid_sources[0x72]	916	1			T38	7		T111	11		T9	2
valid_sources[0x73]	805	1			T1	11		T4	7		T22	1
valid_sources[0x74]	1248	1			T4	3		T38	4		T10	2
valid_sources[0x75]	845	1			T4	14		T7	2		T22	1
valid_sources[0x76]	891	1			T7	15		T38	4		T71	1
valid_sources[0x77]	1001	1			T1	7		T4	5		T7	3
valid_sources[0x78]	814	1			T1	3		T4	6		T50	1
valid_sources[0x79]	892	1			T4	23		T7	14		T123	1
valid_sources[0x7a]	882	1			T38	7		T63	2		T71	1
valid_sources[0x7b]	919	1			T4	7		T7	6		T69	1
valid_sources[0x7c]	2238	1			T4	6		T7	3		T38	4
valid_sources[0x7d]	1275	1			T4	14		T69	1		T38	2
valid_sources[0x7e]	694	1			T4	1		T22	2		T69	1
valid_sources[0x7f]	1074	1			T1	7		T4	3		T7	9
valid_sources[0x80]	1561	1			T4	1		T7	11		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64888

1

T5

195

T1

285

T2

4

values[0x0]

all_enables

biggest_size

32271

1

T5

53

T1

65

T12

80

values[0x1]

all_enables

biggest_size

23140

1

T5

33

T1

52

T2

3