Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T15,T4,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T15,T4,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T23,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T4,T23
1	0	Covered	T5,T1,T2
1	1	Covered	T15,T4,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T23,T11
0	1	Covered	T86,T104,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T23,T11
0	1	Covered	T4,T23,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T23,T11
1	-	Covered	T4,T23,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T4,T23
DetectSt	168	Covered	T4,T23,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T23,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T23,T11
DebounceSt->IdleSt	163	Covered	T15,T11,T46
DetectSt->IdleSt	186	Covered	T86,T104,T106
DetectSt->StableSt	191	Covered	T4,T23,T11
IdleSt->DebounceSt	148	Covered	T15,T4,T23
StableSt->IdleSt	206	Covered	T4,T23,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T4,T23
0	1	Covered	T15,T4,T23
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T23,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T4,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T23,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T11,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T4,T23
DetectSt	-	-	-	-	1	-	-	Covered	T86,T104,T106
DetectSt	-	-	-	-	0	1	-	Covered	T4,T23,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T23,T11
StableSt	-	-	-	-	-	-	0	Covered	T4,T23,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	301	0	0
CntIncr_A	8390318	177133	0	0
CntNoWrap_A	8390318	7714907	0	0
DetectStDropOut_A	8390318	4	0	0
DetectedOut_A	8390318	880	0	0
DetectedPulseOut_A	8390318	136	0	0
DisabledIdleSt_A	8390318	7531135	0	0
DisabledNoDetection_A	8390318	7533432	0	0
EnterDebounceSt_A	8390318	165	0	0
EnterDetectSt_A	8390318	140	0	0
EnterStableSt_A	8390318	136	0	0
PulseIsPulse_A	8390318	136	0	0
StayInStableSt	8390318	744	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6998	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	136	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	301	0	0
T4	314500	8	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	7	0	0
T15	703	1	0	0
T16	616	0	0	0
T17	414	0	0	0
T23	0	2	0	0
T43	0	6	0	0
T44	0	4	0	0
T45	0	6	0	0
T46	0	1	0	0
T47	0	5	0	0
T48	0	6	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	177133	0	0
T4	314500	267	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	202	0	0
T15	703	13	0	0
T16	616	0	0	0
T17	414	0	0	0
T23	0	29	0	0
T43	0	211	0	0
T44	0	69	0	0
T45	0	809	0	0
T46	0	83	0	0
T47	0	227	0	0
T48	0	157	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7714907	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	301	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	4	0	0
T81	7301	0	0	0
T86	770	1	0	0
T99	5716	0	0	0
T104	0	1	0	0
T106	0	1	0	0
T110	0	1	0	0
T114	497	0	0	0
T115	8104	0	0	0
T116	14455	0	0	0
T117	18988	0	0	0
T118	33463	0	0	0
T119	574	0	0	0
T120	83140	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	880	0	0
T4	314500	22	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	8	0	0
T22	518	0	0	0
T23	0	10	0	0
T43	0	23	0	0
T44	0	15	0	0
T45	0	13	0	0
T47	0	23	0	0
T48	0	29	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T101	0	7	0	0
T116	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	136	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T101	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7531135	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	257	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7533432	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	258	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	165	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	4	0	0
T15	703	1	0	0
T16	616	0	0	0
T17	414	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	140	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T86	0	1	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	136	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T101	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	136	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T101	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	744	0	0
T4	314500	18	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	5	0	0
T22	518	0	0	0
T23	0	9	0	0
T43	0	20	0	0
T44	0	13	0	0
T45	0	10	0	0
T47	0	21	0	0
T48	0	26	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T101	0	6	0	0
T116	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6998	0	0
T1	7528	24	0	0
T2	928	1	0	0
T3	33469	25	0	0
T4	0	87	0	0
T5	27545	9	0	0
T6	497	0	0	0
T7	0	35	0	0
T8	0	8	0	0
T12	5216	23	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	3	0	0
T16	616	0	0	0
T49	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	136	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T101	0	1	0	0
T116	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T11
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T55
0	1	Covered	T4,T8,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T55
0	1	Unreachable
1	0	Covered	T4,T11,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T11
DetectSt	168	Covered	T4,T8,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T11,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T11
DebounceSt->IdleSt	163	Covered	T4,T8,T56
DetectSt->IdleSt	186	Covered	T4,T8,T79
DetectSt->StableSt	191	Covered	T4,T11,T55
IdleSt->DebounceSt	148	Covered	T4,T8,T11
StableSt->IdleSt	206	Covered	T4,T11,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T11
0	1	Covered	T4,T8,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T8,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T4,T8,T79
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T55
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	181	0	0
CntIncr_A	8390318	174644	0	0
CntNoWrap_A	8390318	7715027	0	0
DetectStDropOut_A	8390318	18	0	0
DetectedOut_A	8390318	150082	0	0
DetectedPulseOut_A	8390318	52	0	0
DisabledIdleSt_A	8390318	6028990	0	0
DisabledNoDetection_A	8390318	6031344	0	0
EnterDebounceSt_A	8390318	112	0	0
EnterDetectSt_A	8390318	70	0	0
EnterStableSt_A	8390318	52	0	0
PulseIsPulse_A	8390318	52	0	0
StayInStableSt	8390318	150030	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6998	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_sticky_sva.StableStDropOut_A	8390318	1170796	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	181	0	0
T4	314500	11	0	0
T7	13513	0	0	0
T8	947	5	0	0
T11	0	2	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	2	0	0
T61	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	174644	0	0
T4	314500	264	0	0
T7	13513	0	0	0
T8	947	117	0	0
T11	0	34	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	170	0	0
T56	0	90	0	0
T57	0	39	0	0
T61	0	63835	0	0
T77	0	104	0	0
T78	0	86	0	0
T79	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715027	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	18	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	2	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T79	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T127	0	4	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	150082	0	0
T4	314500	488	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	213	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	374	0	0
T57	0	256	0	0
T61	0	22320	0	0
T77	0	373	0	0
T78	0	38	0	0
T79	0	1	0	0
T91	0	86	0	0
T125	0	214	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	52	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T91	0	1	0	0
T125	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6028990	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6031344	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	112	0	0
T4	314500	6	0	0
T7	13513	0	0	0
T8	947	3	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	70	0	0
T4	314500	5	0	0
T7	13513	0	0	0
T8	947	2	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	2	0	0
T125	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	52	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T91	0	1	0	0
T125	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	52	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T91	0	1	0	0
T125	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	150030	0	0
T4	314500	486	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	212	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	372	0	0
T57	0	255	0	0
T61	0	22319	0	0
T77	0	371	0	0
T78	0	37	0	0
T91	0	85	0	0
T125	0	212	0	0
T126	0	257	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6998	0	0
T1	7528	24	0	0
T2	928	1	0	0
T3	33469	25	0	0
T4	0	87	0	0
T5	27545	9	0	0
T6	497	0	0	0
T7	0	35	0	0
T8	0	8	0	0
T12	5216	23	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	3	0	0
T16	616	0	0	0
T49	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1170796	0	0
T4	314500	280072	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	102	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	259	0	0
T57	0	173	0	0
T61	0	30	0	0
T77	0	304	0	0
T78	0	27	0	0
T79	0	75	0	0
T91	0	205	0	0
T125	0	136	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T11
1	0	Covered	T1,T2,T6
1	1	Covered	T4,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T11
0	1	Covered	T61,T96,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T11
0	1	Unreachable
1	0	Covered	T4,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T11
DetectSt	168	Covered	T4,T8,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T11
DebounceSt->IdleSt	163	Covered	T55,T56,T79
DetectSt->IdleSt	186	Covered	T61,T96,T87
DetectSt->StableSt	191	Covered	T4,T8,T11
IdleSt->DebounceSt	148	Covered	T4,T8,T11
StableSt->IdleSt	206	Covered	T4,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T11
0	1	Covered	T4,T8,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T56,T79
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T61,T96,T87
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	182	0	0
CntIncr_A	8390318	125177	0	0
CntNoWrap_A	8390318	7715026	0	0
DetectStDropOut_A	8390318	13	0	0
DetectedOut_A	8390318	290981	0	0
DetectedPulseOut_A	8390318	47	0	0
DisabledIdleSt_A	8390318	6028990	0	0
DisabledNoDetection_A	8390318	6031344	0	0
EnterDebounceSt_A	8390318	123	0	0
EnterDetectSt_A	8390318	60	0	0
EnterStableSt_A	8390318	47	0	0
PulseIsPulse_A	8390318	47	0	0
StayInStableSt	8390318	290934	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_sticky_sva.StableStDropOut_A	8390318	1074725	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	182	0	0
T4	314500	6	0	0
T7	13513	0	0	0
T8	947	2	0	0
T11	0	2	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	6	0	0
T56	0	2	0	0
T57	0	2	0	0
T61	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	125177	0	0
T4	314500	40991	0	0
T7	13513	0	0	0
T8	947	19	0	0
T11	0	46	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	204	0	0
T56	0	164	0	0
T57	0	64	0	0
T61	0	23	0	0
T77	0	42	0	0
T78	0	28	0	0
T79	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715026	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	13	0	0
T44	663	0	0	0
T45	1333	0	0	0
T61	517485	1	0	0
T62	2901	0	0	0
T77	1277	0	0	0
T87	0	1	0	0
T96	0	3	0	0
T121	17567	0	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	4	0	0
T135	0	1	0	0
T136	429	0	0	0
T137	434	0	0	0
T138	501	0	0	0
T139	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	290981	0	0
T4	314500	239789	0	0
T7	13513	0	0	0
T8	947	65	0	0
T11	0	220	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	322	0	0
T77	0	186	0	0
T78	0	9	0	0
T91	0	172	0	0
T93	0	65	0	0
T97	0	1	0	0
T126	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	47	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T126	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6028990	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6031344	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	123	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	6	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	60	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T91	0	1	0	0
T97	0	1	0	0
T126	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	47	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T126	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	47	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T126	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	290934	0	0
T4	314500	239786	0	0
T7	13513	0	0	0
T8	947	64	0	0
T11	0	219	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	321	0	0
T77	0	184	0	0
T78	0	8	0	0
T91	0	171	0	0
T93	0	64	0	0
T126	0	67	0	0
T140	0	213	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1074725	0	0
T4	314500	286	0	0
T7	13513	0	0	0
T8	947	99	0	0
T11	0	83	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T57	0	72	0	0
T77	0	568	0	0
T78	0	104	0	0
T91	0	73	0	0
T93	0	174	0	0
T97	0	124	0	0
T126	0	1008	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T11,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T11
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T55
0	1	Covered	T4,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T55
0	1	Unreachable
1	0	Covered	T4,T11,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T11
DetectSt	168	Covered	T4,T11,T55
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T11,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T55
DebounceSt->IdleSt	163	Covered	T4,T8,T97
DetectSt->IdleSt	186	Covered	T4,T91,T92
DetectSt->StableSt	191	Covered	T4,T11,T55
IdleSt->DebounceSt	148	Covered	T4,T8,T11
StableSt->IdleSt	206	Covered	T4,T11,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T11
0	1	Covered	T4,T8,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T55
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T8,T97
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T4,T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T55
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	183	0	0
CntIncr_A	8390318	500850	0	0
CntNoWrap_A	8390318	7715025	0	0
DetectStDropOut_A	8390318	13	0	0
DetectedOut_A	8390318	643029	0	0
DetectedPulseOut_A	8390318	54	0	0
DisabledIdleSt_A	8390318	6028990	0	0
DisabledNoDetection_A	8390318	6031344	0	0
EnterDebounceSt_A	8390318	117	0	0
EnterDetectSt_A	8390318	67	0	0
EnterStableSt_A	8390318	54	0	0
PulseIsPulse_A	8390318	54	0	0
StayInStableSt	8390318	642975	0	0
gen_high_event_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_sticky_sva.StableStDropOut_A	8390318	537272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	183	0	0
T4	314500	11	0	0
T7	13513	0	0	0
T8	947	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	2	0	0
T61	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	500850	0	0
T4	314500	397	0	0
T7	13513	0	0	0
T8	947	66	0	0
T11	0	18	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	126	0	0
T56	0	4387	0	0
T57	0	57	0	0
T61	0	86	0	0
T77	0	136	0	0
T78	0	73	0	0
T79	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715025	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	13	0	0
T4	314500	3	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T91	0	1	0	0
T92	0	2	0	0
T129	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	643029	0	0
T4	314500	397	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	65	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	516	0	0
T56	0	6288	0	0
T57	0	197	0	0
T61	0	22	0	0
T77	0	584	0	0
T78	0	39	0	0
T79	0	98	0	0
T125	0	250	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	54	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T125	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6028990	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6031344	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	117	0	0
T4	314500	6	0	0
T7	13513	0	0	0
T8	947	3	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	67	0	0
T4	314500	5	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T125	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	54	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T125	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	54	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T125	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	642975	0	0
T4	314500	395	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	64	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	514	0	0
T56	0	6287	0	0
T57	0	196	0	0
T61	0	21	0	0
T77	0	582	0	0
T78	0	38	0	0
T79	0	97	0	0
T125	0	248	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	537272	0	0
T4	314500	280231	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	277	0	0
T22	518	0	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T55	0	179	0	0
T56	0	150	0	0
T57	0	221	0	0
T61	0	86083	0	0
T77	0	86	0	0
T78	0	49	0	0
T79	0	48	0	0
T125	0	158	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T11,T32,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T11,T32,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T11,T36,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T34
1	0	Covered	T5,T1,T2
1	1	Covered	T11,T32,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T35
0	1	Covered	T95,T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T35
0	1	Covered	T11,T36,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T36,T35
1	-	Covered	T11,T36,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T32,T36
DetectSt	168	Covered	T11,T36,T35
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T11,T36,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T36,T35
DebounceSt->IdleSt	163	Covered	T32,T82,T84
DetectSt->IdleSt	186	Covered	T95,T144
DetectSt->StableSt	191	Covered	T11,T36,T35
IdleSt->DebounceSt	148	Covered	T11,T32,T36
StableSt->IdleSt	206	Covered	T11,T36,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T32,T36
0	1	Covered	T11,T32,T36
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T36,T35
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T32,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T36,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T32,T36
DetectSt	-	-	-	-	1	-	-	Covered	T95,T144
DetectSt	-	-	-	-	0	1	-	Covered	T11,T36,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T36,T35
StableSt	-	-	-	-	-	-	0	Covered	T11,T36,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	86	0	0
CntIncr_A	8390318	2816	0	0
CntNoWrap_A	8390318	7715122	0	0
DetectStDropOut_A	8390318	2	0	0
DetectedOut_A	8390318	3463	0	0
DetectedPulseOut_A	8390318	39	0	0
DisabledIdleSt_A	8390318	7690722	0	0
DisabledNoDetection_A	8390318	7693022	0	0
EnterDebounceSt_A	8390318	45	0	0
EnterDetectSt_A	8390318	41	0	0
EnterStableSt_A	8390318	39	0	0
PulseIsPulse_A	8390318	39	0	0
StayInStableSt	8390318	3404	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	86	0	0
T11	24210	10	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	0	4	0	0
T36	0	2	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T82	0	1	0	0
T87	0	4	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2816	0	0
T11	24210	308	0	0
T30	0	51	0	0
T32	0	97	0	0
T35	0	146	0	0
T36	0	70	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T82	0	19	0	0
T87	0	153	0	0
T146	0	188	0	0
T147	0	30	0	0
T148	0	36	0	0
T149	492	0	0	0
T150	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715122	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2	0	0
T95	1153	1	0	0
T144	0	1	0	0
T151	524	0	0	0
T152	717	0	0	0
T153	18161	0	0	0
T154	497	0	0	0
T155	1130	0	0	0
T156	543	0	0	0
T157	664	0	0	0
T158	920	0	0	0
T159	8389	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3463	0	0
T11	24210	220	0	0
T30	0	134	0	0
T35	0	264	0	0
T36	0	42	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	770	0	0
T94	0	413	0	0
T146	0	112	0	0
T147	0	46	0	0
T148	0	112	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	186	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	39	0	0
T11	24210	5	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	2	0	0
T94	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7690722	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7693022	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	45	0	0
T11	24210	5	0	0
T30	0	1	0	0
T32	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T82	0	1	0	0
T87	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	41	0	0
T11	24210	5	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	2	0	0
T94	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	39	0	0
T11	24210	5	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	2	0	0
T94	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	39	0	0
T11	24210	5	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	2	0	0
T94	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3404	0	0
T11	24210	212	0	0
T30	0	133	0	0
T35	0	261	0	0
T36	0	41	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	766	0	0
T94	0	411	0	0
T146	0	109	0	0
T147	0	44	0	0
T148	0	110	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	185	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	19	0	0
T11	24210	2	0	0
T30	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T11,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T11,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T11,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T34
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T11,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T34
0	1	Covered	T164,T165,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T34
0	1	Covered	T4,T11,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T34
1	-	Covered	T4,T11,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T34
DetectSt	168	Covered	T4,T11,T34
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T11,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T34
DebounceSt->IdleSt	163	Covered	T11,T32,T35
DetectSt->IdleSt	186	Covered	T164,T165,T166
DetectSt->StableSt	191	Covered	T4,T11,T34
IdleSt->DebounceSt	148	Covered	T4,T11,T34
StableSt->IdleSt	206	Covered	T4,T11,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T34
0	1	Covered	T4,T11,T34
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T34
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T35,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T34
DetectSt	-	-	-	-	1	-	-	Covered	T164,T165,T166
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T32
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	110	0	0
CntIncr_A	8390318	8952	0	0
CntNoWrap_A	8390318	7715098	0	0
DetectStDropOut_A	8390318	3	0	0
DetectedOut_A	8390318	4737	0	0
DetectedPulseOut_A	8390318	47	0	0
DisabledIdleSt_A	8390318	7693774	0	0
DisabledNoDetection_A	8390318	7696083	0	0
EnterDebounceSt_A	8390318	62	0	0
EnterDetectSt_A	8390318	50	0	0
EnterStableSt_A	8390318	47	0	0
PulseIsPulse_A	8390318	47	0	0
StayInStableSt	8390318	4670	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	2789	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	110	0	0
T4	314500	4	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	8	0	0
T22	518	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T35	0	3	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	3	0	0
T147	0	6	0	0
T167	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	8952	0	0
T4	314500	112	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	287	0	0
T22	518	0	0	0
T32	0	199	0	0
T34	0	25	0	0
T35	0	146	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	20	0	0
T146	0	188	0	0
T147	0	45	0	0
T167	0	90	0	0
T168	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715098	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3	0	0
T164	3206	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T169	404	0	0	0
T170	614	0	0	0
T171	440	0	0	0
T172	423	0	0	0
T173	523	0	0	0
T174	4402	0	0	0
T175	1540	0	0	0
T176	9909	0	0	0
T177	82173	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	4737	0	0
T4	314500	49	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	268	0	0
T22	518	0	0	0
T32	0	576	0	0
T34	0	65	0	0
T35	0	40	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	43	0	0
T147	0	113	0	0
T167	0	190	0	0
T168	0	207	0	0
T178	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	47	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T147	0	3	0	0
T167	0	1	0	0
T168	0	1	0	0
T178	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7693774	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7696083	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	62	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	5	0	0
T22	518	0	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	50	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T147	0	3	0	0
T167	0	1	0	0
T168	0	1	0	0
T178	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	47	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T147	0	3	0	0
T167	0	1	0	0
T168	0	1	0	0
T178	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	47	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	3	0	0
T22	518	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T147	0	3	0	0
T167	0	1	0	0
T168	0	1	0	0
T178	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	4670	0	0
T4	314500	46	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	264	0	0
T22	518	0	0	0
T32	0	573	0	0
T34	0	63	0	0
T35	0	39	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	42	0	0
T147	0	109	0	0
T167	0	189	0	0
T168	0	205	0	0
T178	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2789	0	0
T1	7528	21	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	0	64	0	0
T6	497	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T22	0	5	0	0
T49	0	3	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	3	0	0
T123	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	27	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	2	0	0
T22	518	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T91	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0