Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T6,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T6,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T6,T4,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T9
1	0	Covered	T5,T1,T2
1	1	Covered	T6,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T9
0	1	Covered	T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T9
0	1	Covered	T32,T36,T146
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T4,T9
1	-	Covered	T32,T36,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T4,T9
DetectSt	168	Covered	T6,T4,T9
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T6,T4,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T4,T9
DebounceSt->IdleSt	163	Covered	T82,T84
DetectSt->IdleSt	186	Covered	T164
DetectSt->StableSt	191	Covered	T6,T4,T9
IdleSt->DebounceSt	148	Covered	T6,T4,T9
StableSt->IdleSt	206	Covered	T4,T32,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T4,T9
0	1	Covered	T6,T4,T9
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T9
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T4,T9
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T164
DetectSt	-	-	-	-	0	1	-	Covered	T6,T4,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T36,T146
StableSt	-	-	-	-	-	-	0	Covered	T6,T4,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	86	0	0
CntIncr_A	8390318	2516	0	0
CntNoWrap_A	8390318	7715122	0	0
DetectStDropOut_A	8390318	1	0	0
DetectedOut_A	8390318	3479	0	0
DetectedPulseOut_A	8390318	41	0	0
DisabledIdleSt_A	8390318	7580728	0	0
DisabledNoDetection_A	8390318	7583015	0	0
EnterDebounceSt_A	8390318	44	0	0
EnterDetectSt_A	8390318	42	0	0
EnterStableSt_A	8390318	41	0	0
PulseIsPulse_A	8390318	41	0	0
StayInStableSt	8390318	3416	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	86	0	0
T4	314500	2	0	0
T6	497	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	1	0	0
T146	0	2	0	0
T147	0	4	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2516	0	0
T4	314500	87	0	0
T6	497	24	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	94	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	97	0	0
T33	0	95	0	0
T36	0	70	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	18	0	0
T146	0	94	0	0
T147	0	30	0	0
T167	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715122	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	94	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1	0	0
T164	3206	1	0	0
T169	404	0	0	0
T170	614	0	0	0
T171	440	0	0	0
T172	423	0	0	0
T173	523	0	0	0
T174	4402	0	0	0
T175	1540	0	0	0
T176	9909	0	0	0
T177	82173	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3479	0	0
T4	314500	53	0	0
T6	497	43	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	71	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	269	0	0
T33	0	45	0	0
T36	0	113	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T146	0	109	0	0
T147	0	10	0	0
T148	0	35	0	0
T167	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	41	0	0
T4	314500	1	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7580728	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	4	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7583015	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	4	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	44	0	0
T4	314500	1	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	42	0	0
T4	314500	1	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	41	0	0
T4	314500	1	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	41	0	0
T4	314500	1	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3416	0	0
T4	314500	51	0	0
T6	497	41	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	69	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	268	0	0
T33	0	43	0	0
T36	0	112	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T146	0	108	0	0
T147	0	8	0	0
T148	0	34	0	0
T167	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	19	0	0
T32	81711	1	0	0
T33	962	0	0	0
T36	834	1	0	0
T75	465	0	0	0
T78	1329	0	0	0
T87	0	1	0	0
T94	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T160	0	1	0	0
T167	0	1	0	0
T180	0	1	0	0
T181	78489	0	0	0
T182	410	0	0	0
T183	8427	0	0	0
T184	420	0	0	0
T185	416	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T6,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T6,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T9
1	0	Covered	T5,T1,T2
1	1	Covered	T6,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T87,T164,T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T4,T9,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T11
1	-	Covered	T4,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T4,T9
DetectSt	168	Covered	T4,T9,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T11
DebounceSt->IdleSt	163	Covered	T6,T82,T93
DetectSt->IdleSt	186	Covered	T87,T164,T144
DetectSt->StableSt	191	Covered	T4,T9,T11
IdleSt->DebounceSt	148	Covered	T6,T4,T9
StableSt->IdleSt	206	Covered	T4,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T4,T9
0	1	Covered	T6,T4,T9
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T87,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T87,T164,T144
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	130	0	0
CntIncr_A	8390318	46055	0	0
CntNoWrap_A	8390318	7715078	0	0
DetectStDropOut_A	8390318	3	0	0
DetectedOut_A	8390318	15098	0	0
DetectedPulseOut_A	8390318	58	0	0
DisabledIdleSt_A	8390318	7597269	0	0
DisabledNoDetection_A	8390318	7599570	0	0
EnterDebounceSt_A	8390318	70	0	0
EnterDetectSt_A	8390318	61	0	0
EnterStableSt_A	8390318	58	0	0
PulseIsPulse_A	8390318	58	0	0
StayInStableSt	8390318	15011	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	3200	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	130	0	0
T4	314500	2	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	4	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	4	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	1	0	0
T147	0	6	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	46055	0	0
T4	314500	87	0	0
T6	497	24	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	94	0	0
T11	0	107	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	95	0	0
T35	0	73	0	0
T36	0	140	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	20	0	0
T147	0	45	0	0
T168	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715078	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	95	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3	0	0
T87	67705	1	0	0
T144	0	1	0	0
T164	0	1	0	0
T187	1289	0	0	0
T188	497	0	0	0
T189	504	0	0	0
T190	753	0	0	0
T191	504	0	0	0
T192	490	0	0	0
T193	9157	0	0	0
T194	402	0	0	0
T195	624	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	15098	0	0
T4	314500	162	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	75	0	0
T11	0	248	0	0
T22	518	0	0	0
T30	0	134	0	0
T33	0	213	0	0
T35	0	337	0	0
T36	0	100	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	148	0	0
T168	0	116	0	0
T178	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	58	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T22	518	0	0	0
T30	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	3	0	0
T168	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7597269	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	4	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7599570	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	4	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	70	0	0
T4	314500	1	0	0
T6	497	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	1	0	0
T147	0	3	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	61	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T22	518	0	0	0
T30	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	3	0	0
T168	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	58	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T22	518	0	0	0
T30	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	3	0	0
T168	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	58	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T22	518	0	0	0
T30	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	3	0	0
T168	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	15011	0	0
T4	314500	161	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	74	0	0
T11	0	244	0	0
T22	518	0	0	0
T30	0	131	0	0
T33	0	212	0	0
T35	0	336	0	0
T36	0	97	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	144	0	0
T168	0	115	0	0
T178	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3200	0	0
T1	7528	26	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	0	57	0	0
T6	497	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	6	0	0
T17	414	0	0	0
T22	0	5	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	0	3	0	0
T52	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	29	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T22	518	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T147	0	2	0	0
T168	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Covered	T5,T1,T12
1	1	Covered	T2,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T11
0	1	Covered	T2,T147,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T11
1	-	Covered	T2,T147,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T11
DetectSt	168	Covered	T2,T6,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T11
DebounceSt->IdleSt	163	Covered	T82,T93,T196
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T6,T11
IdleSt->DebounceSt	148	Covered	T2,T6,T11
StableSt->IdleSt	206	Covered	T2,T11,T147

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T11
0	1	Covered	T2,T6,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T196,T197,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T147,T30
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	119	0	0
CntIncr_A	8390318	45559	0	0
CntNoWrap_A	8390318	7715089	0	0
DetectStDropOut_A	8390318	0	0	0
DetectedOut_A	8390318	14502	0	0
DetectedPulseOut_A	8390318	56	0	0
DisabledIdleSt_A	8390318	7600683	0	0
DisabledNoDetection_A	8390318	7602983	0	0
EnterDebounceSt_A	8390318	65	0	0
EnterDetectSt_A	8390318	56	0	0
EnterStableSt_A	8390318	56	0	0
PulseIsPulse_A	8390318	56	0	0
StayInStableSt	8390318	14419	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	119	0	0
T2	928	2	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	2	0	0
T11	0	4	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	4	0	0
T82	0	1	0	0
T91	0	2	0	0
T93	0	2	0	0
T147	0	2	0	0
T178	0	2	0	0
T199	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	45559	0	0
T2	928	90	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	24	0	0
T11	0	98	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	102	0	0
T82	0	19	0	0
T91	0	97	0	0
T93	0	41954	0	0
T147	0	15	0	0
T178	0	10	0	0
T199	0	174	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715089	0	0
T1	7528	1705	0	0
T2	928	525	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	94	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	14502	0	0
T2	928	29	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	43	0	0
T11	0	337	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	172	0	0
T87	0	174	0	0
T91	0	94	0	0
T93	0	9495	0	0
T147	0	4	0	0
T178	0	6	0	0
T199	0	203	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	56	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	1	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	2	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T147	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7600683	0	0
T1	7528	1705	0	0
T2	928	4	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	4	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7602983	0	0
T1	7528	1719	0	0
T2	928	4	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	4	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	65	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	1	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	2	0	0
T82	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T147	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	56	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	1	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	2	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T147	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	56	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	1	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	2	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T147	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	56	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	1	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	2	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T147	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	14419	0	0
T2	928	28	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	41	0	0
T11	0	333	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	170	0	0
T87	0	172	0	0
T91	0	93	0	0
T93	0	9494	0	0
T147	0	3	0	0
T178	0	5	0	0
T199	0	200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	29	0	0
T2	928	1	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	0	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	2	0	0
T91	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T147	0	1	0	0
T178	0	1	0	0
T180	0	1	0	0
T199	0	1	0	0
T200	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T11,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T11,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T11,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T67,T11
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T11,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T32
0	1	Covered	T32,T35,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T32
1	-	Covered	T32,T35,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T32
DetectSt	168	Covered	T4,T11,T32
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T11,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T32
DebounceSt->IdleSt	163	Covered	T82,T180,T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T11,T32
IdleSt->DebounceSt	148	Covered	T4,T11,T32
StableSt->IdleSt	206	Covered	T4,T11,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T32
0	1	Covered	T4,T11,T32
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T32
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T32
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T180
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T35,T30
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	75	0	0
CntIncr_A	8390318	44065	0	0
CntNoWrap_A	8390318	7715133	0	0
DetectStDropOut_A	8390318	0	0	0
DetectedOut_A	8390318	3673	0	0
DetectedPulseOut_A	8390318	36	0	0
DisabledIdleSt_A	8390318	7489768	0	0
DisabledNoDetection_A	8390318	7492069	0	0
EnterDebounceSt_A	8390318	39	0	0
EnterDetectSt_A	8390318	36	0	0
EnterStableSt_A	8390318	36	0	0
PulseIsPulse_A	8390318	36	0	0
StayInStableSt	8390318	3614	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6611	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	75	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	2	0	0
T22	518	0	0	0
T30	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T35	0	4	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	2	0	0
T168	0	2	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	44065	0	0
T4	314500	56	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	72	0	0
T22	518	0	0	0
T30	0	102	0	0
T32	0	194	0	0
T33	0	95	0	0
T35	0	146	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	19	0	0
T146	0	94	0	0
T168	0	44	0	0
T178	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715133	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3673	0	0
T4	314500	48	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	45	0	0
T22	518	0	0	0
T30	0	43	0	0
T31	0	135	0	0
T32	0	172	0	0
T33	0	214	0	0
T35	0	83	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	105	0	0
T168	0	47	0	0
T178	0	112	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	36	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7489768	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7492069	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	39	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	36	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	36	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	36	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	1	0	0
T22	518	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3614	0	0
T4	314500	46	0	0
T7	13513	0	0	0
T8	947	0	0	0
T11	0	43	0	0
T22	518	0	0	0
T30	0	40	0	0
T31	0	133	0	0
T32	0	169	0	0
T33	0	212	0	0
T35	0	80	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	103	0	0
T168	0	45	0	0
T178	0	110	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6611	0	0
T1	7528	29	0	0
T2	928	1	0	0
T3	33469	28	0	0
T4	0	93	0	0
T5	27545	10	0	0
T6	497	0	0	0
T7	0	27	0	0
T8	0	8	0	0
T12	5216	27	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T49	0	1	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	13	0	0
T30	0	1	0	0
T32	81711	1	0	0
T33	962	0	0	0
T35	0	1	0	0
T36	834	0	0	0
T75	465	0	0	0
T78	1329	0	0	0
T87	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	2	0	0
T144	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T181	78489	0	0	0
T182	410	0	0	0
T183	8427	0	0	0
T184	420	0	0	0
T185	416	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T11,T34,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T11,T34,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T11,T32,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T34
1	0	Covered	T5,T1,T2
1	1	Covered	T11,T34,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T32,T35
0	1	Covered	T94,T201,T202
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T32,T35
0	1	Covered	T11,T32,T146
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T32,T35
1	-	Covered	T11,T32,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T34,T32
DetectSt	168	Covered	T11,T32,T35
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T11,T32,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T32,T35
DebounceSt->IdleSt	163	Covered	T34,T32,T82
DetectSt->IdleSt	186	Covered	T94,T201,T202
DetectSt->StableSt	191	Covered	T11,T32,T35
IdleSt->DebounceSt	148	Covered	T11,T34,T32
StableSt->IdleSt	206	Covered	T11,T32,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T34,T32
0	1	Covered	T11,T34,T32
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T32,T35
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T34,T32
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T32,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T180,T132
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T34,T32
DetectSt	-	-	-	-	1	-	-	Covered	T94,T201,T202
DetectSt	-	-	-	-	0	1	-	Covered	T11,T32,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T32,T146
StableSt	-	-	-	-	-	-	0	Covered	T11,T32,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	139	0	0
CntIncr_A	8390318	48329	0	0
CntNoWrap_A	8390318	7715069	0	0
DetectStDropOut_A	8390318	5	0	0
DetectedOut_A	8390318	73647	0	0
DetectedPulseOut_A	8390318	60	0	0
DisabledIdleSt_A	8390318	7584102	0	0
DisabledNoDetection_A	8390318	7586394	0	0
EnterDebounceSt_A	8390318	76	0	0
EnterDetectSt_A	8390318	65	0	0
EnterStableSt_A	8390318	60	0	0
PulseIsPulse_A	8390318	60	0	0
StayInStableSt	8390318	73555	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	139	0	0
T11	24210	6	0	0
T32	0	4	0	0
T34	0	1	0	0
T35	0	2	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T82	0	1	0	0
T91	0	2	0	0
T146	0	2	0	0
T147	0	4	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	2	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	48329	0	0
T11	24210	158	0	0
T32	0	199	0	0
T34	0	25	0	0
T35	0	73	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T82	0	20	0	0
T91	0	97	0	0
T146	0	94	0	0
T147	0	30	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	44	0	0
T178	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715069	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	5	0	0
T94	1938	1	0	0
T164	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	443	0	0	0
T205	686	0	0	0
T206	413	0	0	0
T207	592	0	0	0
T208	665	0	0	0
T209	479	0	0	0
T210	4020	0	0	0
T211	527	0	0	0
T212	683	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	73647	0	0
T11	24210	421	0	0
T32	0	275	0	0
T35	0	150	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T91	0	245	0	0
T146	0	43	0	0
T147	0	127	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	4	0	0
T178	0	46	0	0
T199	0	329	0	0
T213	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	60	0	0
T11	24210	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T91	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7584102	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	4	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7586394	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	4	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	76	0	0
T11	24210	3	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T82	0	1	0	0
T91	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	1	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	65	0	0
T11	24210	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T91	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	60	0	0
T11	24210	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T91	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	60	0	0
T11	24210	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T91	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	1	0	0
T178	0	1	0	0
T199	0	2	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	73555	0	0
T11	24210	416	0	0
T32	0	272	0	0
T35	0	148	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T91	0	243	0	0
T146	0	42	0	0
T147	0	124	0	0
T149	492	0	0	0
T150	502	0	0	0
T168	0	3	0	0
T178	0	44	0	0
T199	0	326	0	0
T213	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	28	0	0
T11	24210	1	0	0
T32	0	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	4	0	0
T94	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0
T160	0	1	0	0
T168	0	1	0	0
T180	0	3	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T33,T82

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T33,T82

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T33,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Covered	T5,T1,T12
1	1	Covered	T4,T33,T82

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T33,T30
0	1	Covered	T214
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T33,T30
0	1	Covered	T30,T179,T199
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T33,T30
1	-	Covered	T30,T179,T199

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T33,T82
DetectSt	168	Covered	T4,T33,T30
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T33,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T33,T30
DebounceSt->IdleSt	163	Covered	T82,T215,T84
DetectSt->IdleSt	186	Covered	T214
DetectSt->StableSt	191	Covered	T4,T33,T30
IdleSt->DebounceSt	148	Covered	T4,T33,T82
StableSt->IdleSt	206	Covered	T4,T30,T179

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T33,T82
0	1	Covered	T4,T33,T82
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T33,T30
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T33,T82
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T33,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T215
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T33,T82
DetectSt	-	-	-	-	1	-	-	Covered	T214
DetectSt	-	-	-	-	0	1	-	Covered	T4,T33,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T179,T199
StableSt	-	-	-	-	-	-	0	Covered	T4,T33,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	55	0	0
CntIncr_A	8390318	1649	0	0
CntNoWrap_A	8390318	7715153	0	0
DetectStDropOut_A	8390318	1	0	0
DetectedOut_A	8390318	1857	0	0
DetectedPulseOut_A	8390318	25	0	0
DisabledIdleSt_A	8390318	7687541	0	0
DisabledNoDetection_A	8390318	7689849	0	0
EnterDebounceSt_A	8390318	29	0	0
EnterDetectSt_A	8390318	26	0	0
EnterStableSt_A	8390318	25	0	0
PulseIsPulse_A	8390318	25	0	0
StayInStableSt	8390318	1819	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6266	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	55	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	2	0	0
T33	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T87	0	2	0	0
T160	0	2	0	0
T179	0	4	0	0
T199	0	2	0	0
T216	0	2	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1649	0	0
T4	314500	56	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	51	0	0
T33	0	95	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	18	0	0
T87	0	80	0	0
T160	0	74	0	0
T179	0	114	0	0
T199	0	87	0	0
T216	0	24	0	0
T217	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715153	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1	0	0
T214	1017	1	0	0
T218	456	0	0	0
T219	8369	0	0	0
T220	51677	0	0	0
T221	494	0	0	0
T222	1202	0	0	0
T223	4721	0	0	0
T224	19144	0	0	0
T225	491	0	0	0
T226	19834	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1857	0	0
T4	314500	139	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	41	0	0
T33	0	354	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	34	0	0
T160	0	38	0	0
T179	0	41	0	0
T180	0	185	0	0
T199	0	42	0	0
T216	0	41	0	0
T217	0	247	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	25	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	1	0	0
T160	0	1	0	0
T179	0	2	0	0
T180	0	4	0	0
T199	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7687541	0	0
T1	7528	1705	0	0
T2	928	4	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7689849	0	0
T1	7528	1719	0	0
T2	928	4	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	29	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T87	0	1	0	0
T160	0	1	0	0
T179	0	2	0	0
T199	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	26	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	1	0	0
T160	0	1	0	0
T179	0	2	0	0
T180	0	4	0	0
T199	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	25	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	1	0	0
T160	0	1	0	0
T179	0	2	0	0
T180	0	4	0	0
T199	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	25	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	1	0	0
T160	0	1	0	0
T179	0	2	0	0
T180	0	4	0	0
T199	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1819	0	0
T4	314500	137	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	40	0	0
T33	0	352	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	33	0	0
T160	0	36	0	0
T179	0	39	0	0
T180	0	180	0	0
T199	0	41	0	0
T216	0	39	0	0
T217	0	245	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6266	0	0
T1	7528	25	0	0
T2	928	0	0	0
T3	33469	31	0	0
T4	0	76	0	0
T5	27545	10	0	0
T6	497	0	0	0
T7	0	29	0	0
T12	5216	29	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T22	0	3	0	0
T49	0	2	0	0
T52	0	7	0	0
T53	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	12	0	0
T30	14181	1	0	0
T87	0	1	0	0
T91	34241	0	0	0
T94	0	1	0	0
T144	0	1	0	0
T178	622	0	0	0
T179	0	2	0	0
T180	0	3	0	0
T199	0	1	0	0
T202	0	1	0	0
T227	0	1	0	0
T228	2262	0	0	0
T229	439	0	0	0
T230	41851	0	0	0
T231	502	0	0	0
T232	672	0	0	0
T233	690	0	0	0
T234	25500	0	0	0