Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T1,T9,T67

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T9,T11,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T5,T1,T12
1	1	Covered	T1,T9,T67

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T34
0	1	Covered	T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T34
0	1	Covered	T32,T33,T146
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T34
1	-	Covered	T32,T33,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T67
DetectSt	168	Covered	T9,T11,T34
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T9,T11,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T34
DebounceSt->IdleSt	163	Covered	T1,T67,T35
DetectSt->IdleSt	186	Covered	T94
DetectSt->StableSt	191	Covered	T9,T11,T34
IdleSt->DebounceSt	148	Covered	T1,T9,T67
StableSt->IdleSt	206	Covered	T11,T34,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T67
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T34
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T67
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T35,T213
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T67
DetectSt	-	-	-	-	1	-	-	Covered	T94
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T146
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	132	0	0
CntIncr_A	8390318	11779	0	0
CntNoWrap_A	8390318	7715076	0	0
DetectStDropOut_A	8390318	1	0	0
DetectedOut_A	8390318	6365	0	0
DetectedPulseOut_A	8390318	61	0	0
DisabledIdleSt_A	8390318	7680934	0	0
DisabledNoDetection_A	8390318	7683227	0	0
EnterDebounceSt_A	8390318	73	0	0
EnterDetectSt_A	8390318	62	0	0
EnterStableSt_A	8390318	61	0	0
PulseIsPulse_A	8390318	61	0	0
StayInStableSt	8390318	6273	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	132	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	4	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	3	0	0
T82	0	1	0	0
T146	0	4	0	0
T148	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	11779	0	0
T1	7528	84	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T9	0	94	0	0
T11	0	55	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	194	0	0
T33	0	190	0	0
T34	0	25	0	0
T35	0	146	0	0
T67	0	591	0	0
T116	0	5623	0	0
T146	0	188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715076	0	0
T1	7528	1704	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1	0	0
T94	1938	1	0	0
T204	443	0	0	0
T205	686	0	0	0
T206	413	0	0	0
T207	592	0	0	0
T208	665	0	0	0
T209	479	0	0	0
T210	4020	0	0	0
T211	527	0	0	0
T212	683	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6365	0	0
T9	2993	507	0	0
T10	13620	0	0	0
T11	0	197	0	0
T23	679	0	0	0
T30	0	228	0	0
T32	0	274	0	0
T33	0	53	0	0
T34	0	66	0	0
T35	0	151	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T146	0	148	0	0
T148	0	142	0	0
T199	0	296	0	0
T235	430	0	0	0
T236	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	61	0	0
T9	2993	1	0	0
T10	13620	0	0	0
T11	0	1	0	0
T23	679	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T146	0	2	0	0
T148	0	2	0	0
T199	0	1	0	0
T235	430	0	0	0
T236	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7680934	0	0
T1	7528	1513	0	0
T2	928	4	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	4	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7683227	0	0
T1	7528	1526	0	0
T2	928	4	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	4	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	73	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T67	0	1	0	0
T116	0	1	0	0
T146	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	62	0	0
T9	2993	1	0	0
T10	13620	0	0	0
T11	0	1	0	0
T23	679	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T146	0	2	0	0
T148	0	2	0	0
T199	0	1	0	0
T235	430	0	0	0
T236	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	61	0	0
T9	2993	1	0	0
T10	13620	0	0	0
T11	0	1	0	0
T23	679	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T146	0	2	0	0
T148	0	2	0	0
T199	0	1	0	0
T235	430	0	0	0
T236	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	61	0	0
T9	2993	1	0	0
T10	13620	0	0	0
T11	0	1	0	0
T23	679	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T146	0	2	0	0
T148	0	2	0	0
T199	0	1	0	0
T235	430	0	0	0
T236	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6273	0	0
T9	2993	505	0	0
T10	13620	0	0	0
T11	0	195	0	0
T23	679	0	0	0
T30	0	225	0	0
T32	0	271	0	0
T33	0	50	0	0
T34	0	64	0	0
T35	0	149	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T146	0	145	0	0
T148	0	139	0	0
T199	0	294	0	0
T235	430	0	0	0
T236	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	30	0	0
T30	0	1	0	0
T32	81711	1	0	0
T33	962	1	0	0
T36	834	0	0	0
T75	465	0	0	0
T78	1329	0	0	0
T87	0	3	0	0
T146	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0
T180	0	1	0	0
T181	78489	0	0	0
T182	410	0	0	0
T183	8427	0	0	0
T184	420	0	0	0
T185	416	0	0	0
T215	0	1	0	0
T237	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T12
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T12
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T11,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T1,T11,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T11,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T11
1	0	Covered	T5,T1,T12
1	1	Covered	T1,T11,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T32
0	1	Covered	T32,T33,T147
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T32
1	-	Covered	T32,T33,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T32
DetectSt	168	Covered	T1,T11,T32
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T1,T11,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T32
DebounceSt->IdleSt	163	Covered	T82,T93,T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T11,T32
IdleSt->DebounceSt	148	Covered	T1,T11,T32
StableSt->IdleSt	206	Covered	T1,T11,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T32
0	1	Covered	T1,T11,T32
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T32
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T32
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T238
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T147
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	79	0	0
CntIncr_A	8390318	2899	0	0
CntNoWrap_A	8390318	7715129	0	0
DetectStDropOut_A	8390318	0	0	0
DetectedOut_A	8390318	3277	0	0
DetectedPulseOut_A	8390318	38	0	0
DisabledIdleSt_A	8390318	7592526	0	0
DisabledNoDetection_A	8390318	7594828	0	0
EnterDebounceSt_A	8390318	42	0	0
EnterDetectSt_A	8390318	38	0	0
EnterStableSt_A	8390318	38	0	0
PulseIsPulse_A	8390318	38	0	0
StayInStableSt	8390318	3219	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6213	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	79	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T82	0	1	0	0
T87	0	8	0	0
T147	0	4	0	0
T148	0	2	0	0
T168	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2899	0	0
T1	7528	84	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	51	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	97	0	0
T33	0	95	0	0
T82	0	20	0	0
T93	0	341	0	0
T147	0	30	0	0
T148	0	36	0	0
T168	0	44	0	0
T213	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715129	0	0
T1	7528	1703	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3277	0	0
T1	7528	38	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	42	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	268	0	0
T33	0	213	0	0
T87	0	618	0	0
T147	0	101	0	0
T148	0	44	0	0
T168	0	32	0	0
T213	0	38	0	0
T217	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	38	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T87	0	4	0	0
T147	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T213	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7592526	0	0
T1	7528	1513	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7594828	0	0
T1	7528	1526	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	42	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T82	0	1	0	0
T93	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	38	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T87	0	4	0	0
T147	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T213	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	38	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T87	0	4	0	0
T147	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T213	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	38	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T87	0	4	0	0
T147	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T213	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3219	0	0
T1	7528	36	0	0
T2	928	0	0	0
T3	33469	0	0	0
T6	497	0	0	0
T11	0	40	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T32	0	267	0	0
T33	0	212	0	0
T87	0	613	0	0
T147	0	99	0	0
T148	0	43	0	0
T168	0	31	0	0
T213	0	36	0	0
T217	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6213	0	0
T1	7528	24	0	0
T2	928	0	0	0
T3	33469	35	0	0
T4	0	73	0	0
T5	27545	8	0	0
T6	497	0	0	0
T7	0	28	0	0
T12	5216	28	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T22	0	4	0	0
T49	0	2	0	0
T52	0	6	0	0
T53	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	18	0	0
T32	81711	1	0	0
T33	962	1	0	0
T36	834	0	0	0
T75	465	0	0	0
T78	1329	0	0	0
T87	0	3	0	0
T147	0	2	0	0
T148	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T168	0	1	0	0
T181	78489	0	0	0
T182	410	0	0	0
T183	8427	0	0	0
T184	420	0	0	0
T185	416	0	0	0
T239	0	1	0	0
T240	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T67
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T4,T36,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T11
1	-	Covered	T4,T36,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T11
DetectSt	168	Covered	T4,T9,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T11
DebounceSt->IdleSt	163	Covered	T11,T82,T132
DetectSt->IdleSt	186	Covered	T93
DetectSt->StableSt	191	Covered	T4,T9,T11
IdleSt->DebounceSt	148	Covered	T4,T9,T11
StableSt->IdleSt	206	Covered	T4,T11,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T11
0	1	Covered	T4,T9,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T132,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T93
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T36,T35
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	107	0	0
CntIncr_A	8390318	3476	0	0
CntNoWrap_A	8390318	7715101	0	0
DetectStDropOut_A	8390318	1	0	0
DetectedOut_A	8390318	4708	0	0
DetectedPulseOut_A	8390318	49	0	0
DisabledIdleSt_A	8390318	7697037	0	0
DisabledNoDetection_A	8390318	7699341	0	0
EnterDebounceSt_A	8390318	57	0	0
EnterDetectSt_A	8390318	50	0	0
EnterStableSt_A	8390318	49	0	0
PulseIsPulse_A	8390318	49	0	0
StayInStableSt	8390318	4633	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	107	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T22	518	0	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	4	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	4	0	0
T147	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	3476	0	0
T4	314500	56	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	94	0	0
T11	0	106	0	0
T22	518	0	0	0
T32	0	97	0	0
T34	0	25	0	0
T35	0	73	0	0
T36	0	140	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	19	0	0
T146	0	188	0	0
T147	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715101	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1	0	0
T87	67705	0	0	0
T88	17975	0	0	0
T93	207810	1	0	0
T187	1289	0	0	0
T188	497	0	0	0
T189	504	0	0	0
T190	753	0	0	0
T191	504	0	0	0
T192	490	0	0	0
T193	9157	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	4708	0	0
T4	314500	190	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	507	0	0
T11	0	41	0	0
T22	518	0	0	0
T32	0	410	0	0
T34	0	66	0	0
T35	0	114	0	0
T36	0	212	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	113	0	0
T147	0	47	0	0
T168	0	256	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	49	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7697037	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7699341	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	57	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T22	518	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	50	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	49	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	49	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T22	518	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	4633	0	0
T4	314500	189	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	505	0	0
T11	0	39	0	0
T22	518	0	0	0
T32	0	408	0	0
T34	0	64	0	0
T35	0	113	0	0
T36	0	209	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T146	0	110	0	0
T147	0	45	0	0
T168	0	254	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	23	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T160	0	1	0	0
T178	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T82,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T82,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T82,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T30,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T30,T31
0	1	Covered	T87,T180,T161
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T30,T31
1	-	Covered	T87,T180,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T82,T30
DetectSt	168	Covered	T4,T30,T31
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T30,T31
DebounceSt->IdleSt	163	Covered	T82,T180,T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T30,T31
IdleSt->DebounceSt	148	Covered	T4,T82,T30
StableSt->IdleSt	206	Covered	T4,T30,T93

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T82,T30
0	1	Covered	T4,T82,T30
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T30,T31
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T82,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T180
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T82,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T87,T180,T161
StableSt	-	-	-	-	-	-	0	Covered	T4,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	51	0	0
CntIncr_A	8390318	1537	0	0
CntNoWrap_A	8390318	7715157	0	0
DetectStDropOut_A	8390318	0	0	0
DetectedOut_A	8390318	1930	0	0
DetectedPulseOut_A	8390318	24	0	0
DisabledIdleSt_A	8390318	7598521	0	0
DisabledNoDetection_A	8390318	7600824	0	0
EnterDebounceSt_A	8390318	27	0	0
EnterDetectSt_A	8390318	24	0	0
EnterStableSt_A	8390318	24	0	0
PulseIsPulse_A	8390318	24	0	0
StayInStableSt	8390318	1892	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6343	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	51	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T87	0	12	0	0
T93	0	2	0	0
T94	0	2	0	0
T132	0	2	0	0
T161	0	2	0	0
T180	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1537	0	0
T4	314500	56	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	51	0	0
T31	0	35	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	18	0	0
T87	0	386	0	0
T93	0	44	0	0
T94	0	77	0	0
T132	0	26	0	0
T161	0	59	0	0
T180	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715157	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1930	0	0
T4	314500	47	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	372	0	0
T31	0	56	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	252	0	0
T93	0	37	0	0
T94	0	42	0	0
T132	0	42	0	0
T161	0	42	0	0
T180	0	76	0	0
T219	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	24	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0
T132	0	1	0	0
T161	0	1	0	0
T180	0	1	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7598521	0	0
T1	7528	1513	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7600824	0	0
T1	7528	1526	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	27	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T87	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0
T132	0	1	0	0
T161	0	1	0	0
T180	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	24	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0
T132	0	1	0	0
T161	0	1	0	0
T180	0	1	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	24	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0
T132	0	1	0	0
T161	0	1	0	0
T180	0	1	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	24	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0
T132	0	1	0	0
T161	0	1	0	0
T180	0	1	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1892	0	0
T4	314500	45	0	0
T7	13513	0	0	0
T8	947	0	0	0
T22	518	0	0	0
T30	0	370	0	0
T31	0	54	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	244	0	0
T93	0	35	0	0
T94	0	40	0	0
T132	0	40	0	0
T161	0	41	0	0
T180	0	75	0	0
T219	0	118	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6343	0	0
T1	7528	31	0	0
T2	928	1	0	0
T3	33469	37	0	0
T4	0	70	0	0
T5	27545	11	0	0
T6	497	1	0	0
T7	0	27	0	0
T12	5216	22	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T49	0	1	0	0
T52	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	10	0	0
T87	67705	4	0	0
T144	0	2	0	0
T161	0	1	0	0
T180	0	1	0	0
T187	1289	0	0	0
T188	497	0	0	0
T189	504	0	0	0
T190	753	0	0	0
T191	504	0	0	0
T192	490	0	0	0
T193	9157	0	0	0
T194	402	0	0	0
T195	624	0	0	0
T227	0	1	0	0
T238	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T11
1	0	Covered	T5,T1,T2
1	1	Covered	T4,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T9,T11,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T11
1	-	Covered	T9,T11,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T11
DetectSt	168	Covered	T4,T9,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T11
DebounceSt->IdleSt	163	Covered	T82,T87,T195
DetectSt->IdleSt	186	Covered	T144
DetectSt->StableSt	191	Covered	T4,T9,T11
IdleSt->DebounceSt	148	Covered	T4,T9,T11
StableSt->IdleSt	206	Covered	T4,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T11
0	1	Covered	T4,T9,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T195,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T144
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T36
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	130	0	0
CntIncr_A	8390318	45614	0	0
CntNoWrap_A	8390318	7715078	0	0
DetectStDropOut_A	8390318	2	0	0
DetectedOut_A	8390318	5609	0	0
DetectedPulseOut_A	8390318	59	0	0
DisabledIdleSt_A	8390318	7604766	0	0
DisabledNoDetection_A	8390318	7607072	0	0
EnterDebounceSt_A	8390318	69	0	0
EnterDetectSt_A	8390318	61	0	0
EnterStableSt_A	8390318	59	0	0
PulseIsPulse_A	8390318	59	0	0
StayInStableSt	8390318	5524	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	130	0	0
T4	314500	2	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	4	0	0
T11	0	6	0	0
T22	518	0	0	0
T36	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	2	0	0
T147	0	4	0	0
T167	0	2	0	0
T178	0	2	0	0
T179	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	45614	0	0
T4	314500	87	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	188	0	0
T11	0	142	0	0
T22	518	0	0	0
T36	0	70	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	18	0	0
T146	0	94	0	0
T147	0	30	0	0
T167	0	90	0	0
T178	0	10	0	0
T179	0	171	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715078	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2	0	0
T144	879	2	0	0
T241	970	0	0	0
T242	522	0	0	0
T243	15000	0	0	0
T244	693	0	0	0
T245	503	0	0	0
T246	505	0	0	0
T247	618	0	0	0
T248	13143	0	0	0
T249	19486	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	5609	0	0
T4	314500	302	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	240	0	0
T11	0	252	0	0
T22	518	0	0	0
T36	0	171	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T93	0	43	0	0
T146	0	372	0	0
T147	0	150	0	0
T167	0	192	0	0
T178	0	57	0	0
T179	0	212	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	59	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T22	518	0	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T93	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7604766	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7607072	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	69	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T22	518	0	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T82	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	61	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T22	518	0	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T93	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	59	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T22	518	0	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T93	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	59	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T22	518	0	0	0
T36	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T93	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	5524	0	0
T4	314500	300	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	237	0	0
T11	0	247	0	0
T22	518	0	0	0
T36	0	170	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T93	0	42	0	0
T146	0	371	0	0
T147	0	147	0	0
T167	0	191	0	0
T178	0	55	0	0
T179	0	208	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	33	0	0
T9	2993	1	0	0
T10	13620	0	0	0
T11	0	1	0	0
T23	679	0	0	0
T36	0	1	0	0
T37	12734	0	0	0
T41	4818	0	0	0
T65	496	0	0	0
T73	508	0	0	0
T74	506	0	0	0
T87	0	4	0	0
T93	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T167	0	1	0	0
T179	0	2	0	0
T180	0	1	0	0
T235	430	0	0	0
T236	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T1,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T4,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T2
1	1	Covered	T1,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T9
0	1	Covered	T11,T87,T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T9
0	1	Covered	T4,T9,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T9
1	-	Covered	T4,T9,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T9
DetectSt	168	Covered	T1,T4,T9
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T1,T4,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T9
DebounceSt->IdleSt	163	Covered	T82,T199,T93
DetectSt->IdleSt	186	Covered	T11,T87,T164
DetectSt->StableSt	191	Covered	T1,T4,T9
IdleSt->DebounceSt	148	Covered	T1,T4,T9
StableSt->IdleSt	206	Covered	T1,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T9
0	1	Covered	T1,T4,T9
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T9
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T199
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T11,T87,T164
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	91	0	0
CntIncr_A	8390318	8450	0	0
CntNoWrap_A	8390318	7715117	0	0
DetectStDropOut_A	8390318	4	0	0
DetectedOut_A	8390318	2774	0	0
DetectedPulseOut_A	8390318	40	0	0
DisabledIdleSt_A	8390318	7494874	0	0
DisabledNoDetection_A	8390318	7497171	0	0
EnterDebounceSt_A	8390318	49	0	0
EnterDetectSt_A	8390318	44	0	0
EnterStableSt_A	8390318	40	0	0
PulseIsPulse_A	8390318	40	0	0
StayInStableSt	8390318	2716	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8390318	6998	0	0
gen_low_level_sva.LowLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	91	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	2	0	0
T6	497	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T82	0	1	0	0
T146	0	2	0	0
T148	0	2	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	8450	0	0
T1	7528	84	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	56	0	0
T6	497	0	0	0
T9	0	94	0	0
T11	0	35	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	95	0	0
T35	0	146	0	0
T82	0	20	0	0
T146	0	94	0	0
T148	0	36	0	0
T167	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7715117	0	0
T1	7528	1703	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	4	0	0
T11	24210	1	0	0
T43	731	0	0	0
T55	1289	0	0	0
T56	38296	0	0	0
T57	1605	0	0	0
T58	14652	0	0	0
T60	3466	0	0	0
T68	497	0	0	0
T87	0	1	0	0
T149	492	0	0	0
T150	502	0	0	0
T164	0	1	0	0
T165	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2774	0	0
T1	7528	39	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	35	0	0
T6	497	0	0	0
T9	0	76	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	279	0	0
T33	0	43	0	0
T35	0	82	0	0
T146	0	39	0	0
T148	0	112	0	0
T167	0	42	0	0
T168	0	117	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	40	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	1	0	0
T6	497	0	0	0
T9	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7494874	0	0
T1	7528	1513	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7497171	0	0
T1	7528	1526	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	49	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	1	0	0
T6	497	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T82	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	44	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	1	0	0
T6	497	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	40	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	1	0	0
T6	497	0	0	0
T9	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	40	0	0
T1	7528	1	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	1	0	0
T6	497	0	0	0
T9	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2716	0	0
T1	7528	37	0	0
T2	928	0	0	0
T3	33469	0	0	0
T4	0	34	0	0
T6	497	0	0	0
T9	0	75	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T30	0	277	0	0
T33	0	42	0	0
T35	0	79	0	0
T146	0	37	0	0
T148	0	110	0	0
T167	0	40	0	0
T168	0	116	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	6998	0	0
T1	7528	24	0	0
T2	928	1	0	0
T3	33469	25	0	0
T4	0	87	0	0
T5	27545	9	0	0
T6	497	0	0	0
T7	0	35	0	0
T8	0	8	0	0
T12	5216	23	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	3	0	0
T16	616	0	0	0
T49	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	22	0	0
T4	314500	1	0	0
T7	13513	0	0	0
T8	947	0	0	0
T9	0	1	0	0
T22	518	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T87	0	2	0	0
T161	0	2	0	0
T168	0	1	0	0
T180	0	1	0	0
T200	0	1	0	0