Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T3,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T3,T7
1	0	Covered	T3,T7,T38
1	1	Covered	T12,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T3,T7
0	1	Covered	T12,T41,T42
1	0	Covered	T38,T29,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T37
0	1	Covered	T3,T7,T37
1	0	Covered	T89,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T37
1	-	Covered	T3,T7,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T3,T7
DetectSt	168	Covered	T12,T3,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T7,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T3,T7
DebounceSt->IdleSt	163	Covered	T82,T250,T210
DetectSt->IdleSt	186	Covered	T12,T38,T41
DetectSt->StableSt	191	Covered	T3,T7,T37
IdleSt->DebounceSt	148	Covered	T12,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T3,T7
0	1	Covered	T12,T3,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T3,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T12,T3,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T250,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T12,T38,T41
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T37
DetectSt	-	-	-	-	0	0	-	Covered	T12,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	2938	0	0
CntIncr_A	8390318	108691	0	0
CntNoWrap_A	8390318	7712270	0	0
DetectStDropOut_A	8390318	412	0	0
DetectedOut_A	8390318	72489	0	0
DetectedPulseOut_A	8390318	864	0	0
DisabledIdleSt_A	8390318	7242424	0	0
DisabledNoDetection_A	8390318	7244571	0	0
EnterDebounceSt_A	8390318	1479	0	0
EnterDetectSt_A	8390318	1461	0	0
EnterStableSt_A	8390318	864	0	0
PulseIsPulse_A	8390318	864	0	0
StayInStableSt	8390318	71506	0	0
gen_high_event_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	741	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2938	0	0
T3	33469	26	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	12	0	0
T12	5216	10	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	60	0	0
T37	0	6	0	0
T38	0	20	0	0
T39	0	4	0	0
T41	0	14	0	0
T42	0	25	0	0
T49	418	0	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	108691	0	0
T3	33469	1235	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	498	0	0
T12	5216	258	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	2265	0	0
T37	0	105	0	0
T38	0	518	0	0
T39	0	132	0	0
T41	0	302	0	0
T42	0	3505	0	0
T49	418	0	0	0
T75	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7712270	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32961	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4805	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	412	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	0	0	0
T12	5216	5	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	16	0	0
T41	0	7	0	0
T42	0	12	0	0
T49	418	0	0	0
T82	0	1	0	0
T99	0	5	0	0
T100	0	4	0	0
T102	0	26	0	0
T103	0	10	0	0
T251	0	25	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	72489	0	0
T3	33469	3410	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	98	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	73	0	0
T39	0	54	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T75	0	39	0	0
T76	0	3864	0	0
T115	0	615	0	0
T117	0	2538	0	0
T252	0	76	0	0
T253	0	3246	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	864	0	0
T3	33469	13	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	6	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	3	0	0
T39	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T75	0	1	0	0
T76	0	18	0	0
T115	0	13	0	0
T117	0	12	0	0
T252	0	1	0	0
T253	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7242424	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	22587	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	2014	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7244571	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	22592	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	2014	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1479	0	0
T3	33469	13	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	6	0	0
T12	5216	5	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	30	0	0
T37	0	3	0	0
T38	0	10	0	0
T39	0	2	0	0
T41	0	7	0	0
T42	0	13	0	0
T49	418	0	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1461	0	0
T3	33469	13	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	6	0	0
T12	5216	5	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	30	0	0
T37	0	3	0	0
T38	0	10	0	0
T39	0	2	0	0
T41	0	7	0	0
T42	0	13	0	0
T49	418	0	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	864	0	0
T3	33469	13	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	6	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	3	0	0
T39	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T75	0	1	0	0
T76	0	18	0	0
T115	0	13	0	0
T117	0	12	0	0
T252	0	1	0	0
T253	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	864	0	0
T3	33469	13	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	6	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	3	0	0
T39	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T75	0	1	0	0
T76	0	18	0	0
T115	0	13	0	0
T117	0	12	0	0
T252	0	1	0	0
T253	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	71506	0	0
T3	33469	3393	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	92	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	70	0	0
T39	0	52	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T75	0	37	0	0
T76	0	3840	0	0
T115	0	602	0	0
T117	0	2521	0	0
T252	0	74	0	0
T253	0	3219	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	741	0	0
T3	33469	9	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	6	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	3	0	0
T39	0	2	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	12	0	0
T82	0	5	0	0
T115	0	13	0	0
T117	0	7	0	0
T253	0	19	0	0
T254	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T12
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T12
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T5,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T40,T80,T81
1	0	Covered	T82,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
1	0	Covered	T82

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T3
1	-	Covered	T5,T1,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T3
DetectSt	168	Covered	T5,T1,T3
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T5,T1,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T3
DebounceSt->IdleSt	163	Covered	T4,T67,T98
DetectSt->IdleSt	186	Covered	T40,T80,T81
DetectSt->StableSt	191	Covered	T5,T1,T3
IdleSt->DebounceSt	148	Covered	T5,T1,T3
StableSt->IdleSt	206	Covered	T5,T1,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T3
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T67,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T40,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	814	0	0
CntIncr_A	8390318	41797	0	0
CntNoWrap_A	8390318	7714394	0	0
DetectStDropOut_A	8390318	18	0	0
DetectedOut_A	8390318	12971	0	0
DetectedPulseOut_A	8390318	350	0	0
DisabledIdleSt_A	8390318	7365329	0	0
DisabledNoDetection_A	8390318	7366989	0	0
EnterDebounceSt_A	8390318	443	0	0
EnterDetectSt_A	8390318	372	0	0
EnterStableSt_A	8390318	350	0	0
PulseIsPulse_A	8390318	350	0	0
StayInStableSt	8390318	12578	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	305	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	814	0	0
T1	7528	4	0	0
T2	928	0	0	0
T3	33469	8	0	0
T4	0	3	0	0
T5	27545	20	0	0
T6	497	0	0	0
T10	0	6	0	0
T11	0	4	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T40	0	4	0	0
T58	0	8	0	0
T67	0	1	0	0
T98	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	41797	0	0
T1	7528	50	0	0
T2	928	0	0	0
T3	33469	344	0	0
T4	0	45	0	0
T5	27545	1790	0	0
T6	497	0	0	0
T10	0	342	0	0
T11	0	227	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T40	0	137	0	0
T58	0	172	0	0
T67	0	20	0	0
T98	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7714394	0	0
T1	7528	1701	0	0
T2	928	527	0	0
T3	33469	32979	0	0
T5	27545	27064	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	18	0	0
T9	2993	0	0	0
T28	2851	0	0	0
T40	24615	2	0	0
T63	493	0	0	0
T64	492	0	0	0
T71	526	0	0	0
T72	523	0	0	0
T80	0	7	0	0
T81	0	1	0	0
T101	0	1	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	2	0	0
T111	405	0	0	0
T112	412	0	0	0
T113	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	12971	0	0
T1	7528	7	0	0
T2	928	0	0	0
T3	33469	705	0	0
T4	0	3	0	0
T5	27545	166	0	0
T6	497	0	0	0
T10	0	77	0	0
T11	0	49	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T58	0	105	0	0
T76	0	338	0	0
T121	0	21	0	0
T122	0	121	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	350	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	4	0	0
T4	0	1	0	0
T5	27545	10	0	0
T6	497	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T58	0	4	0	0
T76	0	5	0	0
T121	0	3	0	0
T122	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7365329	0	0
T1	7528	1546	0	0
T2	928	527	0	0
T3	33469	29581	0	0
T5	27545	22161	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7366989	0	0
T1	7528	1558	0	0
T2	928	528	0	0
T3	33469	29587	0	0
T5	27545	22161	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	443	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	4	0	0
T4	0	2	0	0
T5	27545	10	0	0
T6	497	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T40	0	2	0	0
T58	0	4	0	0
T67	0	1	0	0
T98	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	372	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	4	0	0
T4	0	1	0	0
T5	27545	10	0	0
T6	497	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T40	0	2	0	0
T58	0	4	0	0
T121	0	3	0	0
T122	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	350	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	4	0	0
T4	0	1	0	0
T5	27545	10	0	0
T6	497	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T58	0	4	0	0
T76	0	5	0	0
T121	0	3	0	0
T122	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	350	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	4	0	0
T4	0	1	0	0
T5	27545	10	0	0
T6	497	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T58	0	4	0	0
T76	0	5	0	0
T121	0	3	0	0
T122	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	12578	0	0
T1	7528	5	0	0
T2	928	0	0	0
T3	33469	701	0	0
T4	0	2	0	0
T5	27545	155	0	0
T6	497	0	0	0
T10	0	74	0	0
T11	0	48	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T58	0	101	0	0
T76	0	328	0	0
T121	0	18	0	0
T122	0	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	305	0	0
T1	7528	2	0	0
T2	928	0	0	0
T3	33469	4	0	0
T4	0	1	0	0
T5	27545	8	0	0
T6	497	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T58	0	4	0	0
T121	0	3	0	0
T122	0	3	0	0
T124	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T3,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T3,T7
1	0	Covered	T3,T7,T38
1	1	Covered	T12,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T3,T7
0	1	Covered	T12,T41,T76
1	0	Covered	T76,T117,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T38
0	1	Covered	T3,T7,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T38
1	-	Covered	T3,T7,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T3,T7
DetectSt	168	Covered	T12,T3,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T7,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T3,T7
DebounceSt->IdleSt	163	Covered	T82,T250,T210
DetectSt->IdleSt	186	Covered	T12,T41,T76
DetectSt->StableSt	191	Covered	T3,T7,T38
IdleSt->DebounceSt	148	Covered	T12,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T3,T7
0	1	Covered	T12,T3,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T3,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T12,T3,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T250,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T12,T41,T76
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T38
DetectSt	-	-	-	-	0	0	-	Covered	T12,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	2792	0	0
CntIncr_A	8390318	103030	0	0
CntNoWrap_A	8390318	7712416	0	0
DetectStDropOut_A	8390318	309	0	0
DetectedOut_A	8390318	80184	0	0
DetectedPulseOut_A	8390318	970	0	0
DisabledIdleSt_A	8390318	7238253	0	0
DisabledNoDetection_A	8390318	7240381	0	0
EnterDebounceSt_A	8390318	1412	0	0
EnterDetectSt_A	8390318	1380	0	0
EnterStableSt_A	8390318	970	0	0
PulseIsPulse_A	8390318	970	0	0
StayInStableSt	8390318	79076	0	0
gen_high_event_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	831	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2792	0	0
T3	33469	40	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	52	0	0
T12	5216	28	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	24	0	0
T37	0	54	0	0
T38	0	20	0	0
T39	0	58	0	0
T41	0	24	0	0
T42	0	46	0	0
T49	418	0	0	0
T76	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	103030	0	0
T3	33469	1800	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	1690	0	0
T12	5216	725	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	888	0	0
T37	0	1107	0	0
T38	0	470	0	0
T39	0	2204	0	0
T41	0	529	0	0
T42	0	5750	0	0
T49	418	0	0	0
T76	0	4205	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7712416	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32947	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4787	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	309	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	0	0	0
T12	5216	14	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T41	0	12	0	0
T49	418	0	0	0
T76	0	5	0	0
T82	0	1	0	0
T99	0	12	0	0
T100	0	7	0	0
T102	0	10	0	0
T103	0	13	0	0
T117	0	9	0	0
T251	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	80184	0	0
T3	33469	3647	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	2150	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	323	0	0
T37	0	1611	0	0
T38	0	1518	0	0
T39	0	523	0	0
T42	0	465	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	290	0	0
T115	0	1659	0	0
T253	0	1566	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	970	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	12	0	0
T37	0	27	0	0
T38	0	10	0	0
T39	0	29	0	0
T42	0	23	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	5	0	0
T115	0	12	0	0
T253	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7238253	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	22831	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	2014	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7240381	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	22835	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	2014	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1412	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	26	0	0
T12	5216	14	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	12	0	0
T37	0	27	0	0
T38	0	10	0	0
T39	0	29	0	0
T41	0	12	0	0
T42	0	23	0	0
T49	418	0	0	0
T76	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1380	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	26	0	0
T12	5216	14	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	12	0	0
T37	0	27	0	0
T38	0	10	0	0
T39	0	29	0	0
T41	0	12	0	0
T42	0	23	0	0
T49	418	0	0	0
T76	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	970	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	12	0	0
T37	0	27	0	0
T38	0	10	0	0
T39	0	29	0	0
T42	0	23	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	5	0	0
T115	0	12	0	0
T253	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	970	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	12	0	0
T37	0	27	0	0
T38	0	10	0	0
T39	0	29	0	0
T42	0	23	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	5	0	0
T115	0	12	0	0
T253	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	79076	0	0
T3	33469	3622	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	2123	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	310	0	0
T37	0	1581	0	0
T38	0	1501	0	0
T39	0	494	0	0
T42	0	442	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	285	0	0
T115	0	1647	0	0
T253	0	1552	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	831	0	0
T3	33469	15	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	25	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	11	0	0
T37	0	24	0	0
T38	0	3	0	0
T39	0	29	0	0
T42	0	22	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T82	0	5	0	0
T115	0	12	0	0
T253	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T5,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T255,T30,T256
1	0	Covered	T82,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T82,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T7
1	-	Covered	T3,T4,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T3,T4
DetectSt	168	Covered	T3,T4,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T7
DebounceSt->IdleSt	163	Covered	T5,T40,T11
DetectSt->IdleSt	186	Covered	T82,T255,T30
DetectSt->StableSt	191	Covered	T3,T4,T7
IdleSt->DebounceSt	148	Covered	T5,T3,T4
StableSt->IdleSt	206	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T3,T4
0	1	Covered	T5,T3,T4
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T40,T11
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T82,T255,T30
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	830	0	0
CntIncr_A	8390318	42675	0	0
CntNoWrap_A	8390318	7714378	0	0
DetectStDropOut_A	8390318	74	0	0
DetectedOut_A	8390318	17323	0	0
DetectedPulseOut_A	8390318	318	0	0
DisabledIdleSt_A	8390318	7364714	0	0
DisabledNoDetection_A	8390318	7366419	0	0
EnterDebounceSt_A	8390318	434	0	0
EnterDetectSt_A	8390318	398	0	0
EnterStableSt_A	8390318	318	0	0
PulseIsPulse_A	8390318	318	0	0
StayInStableSt	8390318	16938	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	246	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	830	0	0
T1	7528	0	0	0
T2	928	0	0	0
T3	33469	10	0	0
T4	0	4	0	0
T5	27545	1	0	0
T6	497	0	0	0
T7	0	6	0	0
T11	0	3	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T29	0	2	0	0
T37	0	6	0	0
T38	0	14	0	0
T40	0	1	0	0
T121	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	42675	0	0
T1	7528	0	0	0
T2	928	0	0	0
T3	33469	360	0	0
T4	0	244	0	0
T5	27545	79	0	0
T6	497	0	0	0
T7	0	150	0	0
T11	0	183	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T29	0	96	0	0
T37	0	159	0	0
T38	0	357	0	0
T40	0	38	0	0
T121	0	596	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7714378	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32977	0	0
T5	27545	27083	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	74	0	0
T30	0	1	0	0
T87	0	3	0	0
T100	5066	0	0	0
T101	10721	0	0	0
T107	0	2	0	0
T255	10988	2	0	0
T256	0	1	0	0
T257	0	1	0	0
T258	0	8	0	0
T259	0	6	0	0
T260	0	13	0	0
T261	0	9	0	0
T262	2097	0	0	0
T263	502	0	0	0
T264	34111	0	0	0
T265	61649	0	0	0
T266	25651	0	0	0
T267	529	0	0	0
T268	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	17323	0	0
T3	33469	944	0	0
T4	314500	53	0	0
T6	497	0	0	0
T7	13513	294	0	0
T11	0	73	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	40	0	0
T37	0	85	0	0
T38	0	473	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T121	0	45	0	0
T122	0	188	0	0
T124	0	416	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	318	0	0
T3	33469	5	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	3	0	0
T11	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	1	0	0
T37	0	3	0	0
T38	0	7	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T121	0	3	0	0
T122	0	2	0	0
T124	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7364714	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	29345	0	0
T5	27545	22161	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7366419	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	29350	0	0
T5	27545	22161	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	434	0	0
T1	7528	0	0	0
T2	928	0	0	0
T3	33469	5	0	0
T4	0	2	0	0
T5	27545	1	0	0
T6	497	0	0	0
T7	0	3	0	0
T11	0	2	0	0
T12	5216	0	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T29	0	1	0	0
T37	0	3	0	0
T38	0	7	0	0
T40	0	1	0	0
T121	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	398	0	0
T3	33469	5	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	3	0	0
T11	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	1	0	0
T37	0	3	0	0
T38	0	7	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T121	0	3	0	0
T122	0	2	0	0
T124	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	318	0	0
T3	33469	5	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	3	0	0
T11	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	1	0	0
T37	0	3	0	0
T38	0	7	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T121	0	3	0	0
T122	0	2	0	0
T124	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	318	0	0
T3	33469	5	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	3	0	0
T11	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	1	0	0
T37	0	3	0	0
T38	0	7	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T121	0	3	0	0
T122	0	2	0	0
T124	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	16938	0	0
T3	33469	936	0	0
T4	314500	51	0	0
T6	497	0	0	0
T7	13513	291	0	0
T11	0	72	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	39	0	0
T37	0	79	0	0
T38	0	459	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T121	0	42	0	0
T122	0	186	0	0
T124	0	411	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	246	0	0
T3	33469	2	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	3	0	0
T11	0	1	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	1	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T80	0	1	0	0
T121	0	3	0	0
T122	0	2	0	0
T124	0	5	0	0
T253	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T3,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T3,T7
1	0	Covered	T3,T7,T38
1	1	Covered	T12,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T3,T7
0	1	Covered	T12,T38,T41
1	0	Covered	T38,T37,T29

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T39
0	1	Covered	T3,T7,T39
1	0	Covered	T88,T90,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T39
1	-	Covered	T3,T7,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T3,T7
DetectSt	168	Covered	T12,T3,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T7,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T3,T7
DebounceSt->IdleSt	163	Covered	T82,T250,T210
DetectSt->IdleSt	186	Covered	T12,T38,T37
DetectSt->StableSt	191	Covered	T3,T7,T39
IdleSt->DebounceSt	148	Covered	T12,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T3,T7
0	1	Covered	T12,T3,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T3,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T12,T3,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T250,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T12,T38,T37
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T39
DetectSt	-	-	-	-	0	0	-	Covered	T12,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	2921	0	0
CntIncr_A	8390318	115514	0	0
CntNoWrap_A	8390318	7712287	0	0
DetectStDropOut_A	8390318	334	0	0
DetectedOut_A	8390318	79671	0	0
DetectedPulseOut_A	8390318	876	0	0
DisabledIdleSt_A	8390318	7241558	0	0
DisabledNoDetection_A	8390318	7243709	0	0
EnterDebounceSt_A	8390318	1467	0	0
EnterDetectSt_A	8390318	1454	0	0
EnterStableSt_A	8390318	876	0	0
PulseIsPulse_A	8390318	876	0	0
StayInStableSt	8390318	78680	0	0
gen_high_event_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	717	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2921	0	0
T3	33469	40	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	52	0	0
T12	5216	22	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	56	0	0
T37	0	20	0	0
T38	0	46	0	0
T39	0	58	0	0
T41	0	52	0	0
T42	0	44	0	0
T49	418	0	0	0
T76	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	115514	0	0
T3	33469	1660	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	1352	0	0
T12	5216	569	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	2122	0	0
T37	0	579	0	0
T38	0	1178	0	0
T39	0	2117	0	0
T41	0	1145	0	0
T42	0	5944	0	0
T49	418	0	0	0
T76	0	4301	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7712287	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32947	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4793	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	334	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	0	0	0
T12	5216	11	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T38	0	20	0	0
T41	0	26	0	0
T42	0	22	0	0
T49	418	0	0	0
T82	0	1	0	0
T99	0	16	0	0
T100	0	19	0	0
T102	0	24	0	0
T103	0	24	0	0
T251	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	79671	0	0
T3	33469	3787	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	2340	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	2114	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	5015	0	0
T82	0	314	0	0
T115	0	91	0	0
T117	0	844	0	0
T253	0	3818	0	0
T254	0	860	0	0
T269	0	2492	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	876	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	29	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	17	0	0
T82	0	5	0	0
T115	0	3	0	0
T117	0	3	0	0
T253	0	24	0	0
T254	0	13	0	0
T269	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7241558	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	22831	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	2014	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7243709	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	22835	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	2014	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1467	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	26	0	0
T12	5216	11	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T37	0	10	0	0
T38	0	23	0	0
T39	0	29	0	0
T41	0	26	0	0
T42	0	22	0	0
T49	418	0	0	0
T76	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1454	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	26	0	0
T12	5216	11	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T37	0	10	0	0
T38	0	23	0	0
T39	0	29	0	0
T41	0	26	0	0
T42	0	22	0	0
T49	418	0	0	0
T76	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	876	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	29	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	17	0	0
T82	0	5	0	0
T115	0	3	0	0
T117	0	3	0	0
T253	0	24	0	0
T254	0	13	0	0
T269	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	876	0	0
T3	33469	20	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	29	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	17	0	0
T82	0	5	0	0
T115	0	3	0	0
T117	0	3	0	0
T253	0	24	0	0
T254	0	13	0	0
T269	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	78680	0	0
T3	33469	3762	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	2312	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	2085	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	4992	0	0
T82	0	309	0	0
T115	0	88	0	0
T117	0	838	0	0
T253	0	3791	0	0
T254	0	845	0	0
T269	0	2459	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	717	0	0
T3	33469	15	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	24	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	29	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	11	0	0
T82	0	5	0	0
T115	0	3	0	0
T253	0	21	0	0
T254	0	11	0	0
T269	0	13	0	0
T270	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T12
1	1	Covered	T3,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T91,T256,T271
1	0	Covered	T82,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T7
1	-	Covered	T3,T4,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T7
DetectSt	168	Covered	T3,T4,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T7
DebounceSt->IdleSt	163	Covered	T4,T40,T124
DetectSt->IdleSt	186	Covered	T82,T91,T256
DetectSt->StableSt	191	Covered	T3,T4,T7
IdleSt->DebounceSt	148	Covered	T3,T4,T7
StableSt->IdleSt	206	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T40,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	1	-	-	Covered	T82,T91,T256
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	799	0	0
CntIncr_A	8390318	46483	0	0
CntNoWrap_A	8390318	7714409	0	0
DetectStDropOut_A	8390318	62	0	0
DetectedOut_A	8390318	12051	0	0
DetectedPulseOut_A	8390318	308	0	0
DisabledIdleSt_A	8390318	7357654	0	0
DisabledNoDetection_A	8390318	7359378	0	0
EnterDebounceSt_A	8390318	425	0	0
EnterDetectSt_A	8390318	376	0	0
EnterStableSt_A	8390318	308	0	0
PulseIsPulse_A	8390318	308	0	0
StayInStableSt	8390318	11709	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	799	0	0
T3	33469	8	0	0
T4	314500	5	0	0
T6	497	0	0	0
T7	13513	4	0	0
T10	0	16	0	0
T11	0	4	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	2	0	0
T40	0	21	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	2	0	0
T121	0	4	0	0
T122	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	46483	0	0
T3	33469	384	0	0
T4	314500	291	0	0
T6	497	0	0	0
T7	13513	184	0	0
T10	0	864	0	0
T11	0	342	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	65	0	0
T40	0	528	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	60	0	0
T121	0	362	0	0
T122	0	220	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7714409	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32979	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	62	0	0
T87	0	6	0	0
T91	34241	5	0	0
T108	0	4	0	0
T126	2146	0	0	0
T226	0	1	0	0
T254	12648	0	0	0
T256	5544	8	0	0
T257	7732	0	0	0
T258	0	3	0	0
T271	0	2	0	0
T272	0	2	0	0
T273	0	2	0	0
T274	0	12	0	0
T275	564	0	0	0
T276	402	0	0	0
T277	493	0	0	0
T278	540	0	0	0
T279	500	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	12051	0	0
T3	33469	662	0	0
T4	314500	90	0	0
T6	497	0	0	0
T7	13513	110	0	0
T10	0	253	0	0
T11	0	17	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	83	0	0
T40	0	197	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	9	0	0
T121	0	9	0	0
T122	0	167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	308	0	0
T3	33469	4	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	2	0	0
T10	0	8	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	1	0	0
T40	0	10	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7357654	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	29205	0	0
T5	27545	22161	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7359378	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	29210	0	0
T5	27545	22161	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	425	0	0
T3	33469	4	0	0
T4	314500	3	0	0
T6	497	0	0	0
T7	13513	2	0	0
T10	0	8	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	1	0	0
T40	0	11	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	376	0	0
T3	33469	4	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	2	0	0
T10	0	8	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	1	0	0
T40	0	10	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	308	0	0
T3	33469	4	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	2	0	0
T10	0	8	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	1	0	0
T40	0	10	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	308	0	0
T3	33469	4	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	2	0	0
T10	0	8	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	1	0	0
T40	0	10	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	11709	0	0
T3	33469	658	0	0
T4	314500	88	0	0
T6	497	0	0	0
T7	13513	108	0	0
T10	0	245	0	0
T11	0	15	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	82	0	0
T40	0	187	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	8	0	0
T121	0	7	0	0
T122	0	165	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	272	0	0
T3	33469	4	0	0
T4	314500	2	0	0
T6	497	0	0	0
T7	13513	2	0	0
T10	0	8	0	0
T11	0	2	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T39	0	1	0	0
T40	0	10	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T58	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0