Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T3,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T12,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T3,T7
1	0	Covered	T3,T7,T38
1	1	Covered	T12,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T3,T7
0	1	Covered	T12,T38,T37
1	0	Covered	T38,T37,T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T29
0	1	Covered	T3,T7,T29
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T29
1	-	Covered	T3,T7,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T3,T7
DetectSt	168	Covered	T12,T3,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T7,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T3,T7
DebounceSt->IdleSt	163	Covered	T82,T250,T210
DetectSt->IdleSt	186	Covered	T12,T38,T37
DetectSt->StableSt	191	Covered	T3,T7,T29
IdleSt->DebounceSt	148	Covered	T12,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T3,T7
0	1	Covered	T12,T3,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T3,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T12,T3,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T250,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T12,T38,T37
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T29
DetectSt	-	-	-	-	0	0	-	Covered	T12,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T29
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	2664	0	0
CntIncr_A	8390318	111477	0	0
CntNoWrap_A	8390318	7712544	0	0
DetectStDropOut_A	8390318	310	0	0
DetectedOut_A	8390318	68455	0	0
DetectedPulseOut_A	8390318	804	0	0
DisabledIdleSt_A	8390318	7241976	0	0
DisabledNoDetection_A	8390318	7244151	0	0
EnterDebounceSt_A	8390318	1347	0	0
EnterDetectSt_A	8390318	1317	0	0
EnterStableSt_A	8390318	804	0	0
PulseIsPulse_A	8390318	804	0	0
StayInStableSt	8390318	67560	0	0
gen_high_event_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	713	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	2664	0	0
T3	33469	10	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	52	0	0
T12	5216	14	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	56	0	0
T37	0	28	0	0
T38	0	8	0	0
T39	0	20	0	0
T41	0	18	0	0
T42	0	6	0	0
T49	418	0	0	0
T76	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	111477	0	0
T3	33469	445	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	1820	0	0
T12	5216	357	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	1988	0	0
T37	0	807	0	0
T38	0	203	0	0
T39	0	916	0	0
T41	0	393	0	0
T42	0	809	0	0
T49	418	0	0	0
T76	0	7392	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7712544	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32977	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4801	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	310	0	0
T3	33469	0	0	0
T4	314500	0	0	0
T6	497	0	0	0
T12	5216	7	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T37	0	5	0	0
T38	0	3	0	0
T39	0	1	0	0
T41	0	9	0	0
T42	0	3	0	0
T49	418	0	0	0
T82	0	1	0	0
T99	0	16	0	0
T100	0	11	0	0
T117	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	68455	0	0
T3	33469	310	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	2020	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	2107	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	7130	0	0
T82	0	268	0	0
T115	0	269	0	0
T253	0	2993	0	0
T254	0	717	0	0
T269	0	1070	0	0
T270	0	996	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	804	0	0
T3	33469	5	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	28	0	0
T82	0	5	0	0
T115	0	7	0	0
T253	0	23	0	0
T254	0	11	0	0
T269	0	10	0	0
T270	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7241976	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	25284	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	2014	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7244151	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	25293	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	2014	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1347	0	0
T3	33469	5	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	26	0	0
T12	5216	7	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T37	0	14	0	0
T38	0	4	0	0
T39	0	10	0	0
T41	0	9	0	0
T42	0	3	0	0
T49	418	0	0	0
T76	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	1317	0	0
T3	33469	5	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	0	26	0	0
T12	5216	7	0	0
T13	409	0	0	0
T14	402	0	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T37	0	14	0	0
T38	0	4	0	0
T39	0	10	0	0
T41	0	9	0	0
T42	0	3	0	0
T49	418	0	0	0
T76	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	804	0	0
T3	33469	5	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	28	0	0
T82	0	5	0	0
T115	0	7	0	0
T253	0	23	0	0
T254	0	11	0	0
T269	0	10	0	0
T270	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	804	0	0
T3	33469	5	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	26	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	28	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	28	0	0
T82	0	5	0	0
T115	0	7	0	0
T253	0	23	0	0
T254	0	11	0	0
T269	0	10	0	0
T270	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	67560	0	0
T3	33469	305	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	1993	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	2075	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	7093	0	0
T82	0	263	0	0
T115	0	262	0	0
T253	0	2966	0	0
T254	0	705	0	0
T269	0	1054	0	0
T270	0	983	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	713	0	0
T3	33469	5	0	0
T4	314500	0	0	0
T6	497	0	0	0
T7	13513	25	0	0
T15	703	0	0	0
T16	616	0	0	0
T17	414	0	0	0
T29	0	24	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T76	0	19	0	0
T82	0	5	0	0
T115	0	7	0	0
T253	0	19	0	0
T254	0	10	0	0
T269	0	4	0	0
T270	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T7,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T4,T7,T40

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T7,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T12
1	1	Covered	T4,T7,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T40
0	1	Covered	T264,T101,T257
1	0	Covered	T82,T83,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T40
0	1	Covered	T4,T7,T40
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T40
1	-	Covered	T4,T7,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T40
DetectSt	168	Covered	T4,T7,T40
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T4,T7,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T40
DebounceSt->IdleSt	163	Covered	T40,T121,T81
DetectSt->IdleSt	186	Covered	T82,T264,T101
DetectSt->StableSt	191	Covered	T4,T7,T40
IdleSt->DebounceSt	148	Covered	T4,T7,T40
StableSt->IdleSt	206	Covered	T4,T7,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T40
0	1	Covered	T4,T7,T40
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T40
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T121,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T40
DetectSt	-	-	-	-	1	-	-	Covered	T82,T264,T101
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T40
DetectSt	-	-	-	-	0	0	-	Covered	T4,T7,T40
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T40
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8390318	720	0	0
CntIncr_A	8390318	38513	0	0
CntNoWrap_A	8390318	7714488	0	0
DetectStDropOut_A	8390318	49	0	0
DetectedOut_A	8390318	12613	0	0
DetectedPulseOut_A	8390318	285	0	0
DisabledIdleSt_A	8390318	7378225	0	0
DisabledNoDetection_A	8390318	7379988	0	0
EnterDebounceSt_A	8390318	381	0	0
EnterDetectSt_A	8390318	340	0	0
EnterStableSt_A	8390318	285	0	0
PulseIsPulse_A	8390318	285	0	0
StayInStableSt	8390318	12298	0	0
gen_high_level_sva.HighLevelEvent_A	8390318	7717563	0	0
gen_not_sticky_sva.StableStDropOut_A	8390318	252	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	720	0	0
T4	314500	6	0	0
T7	13513	6	0	0
T8	947	0	0	0
T10	0	6	0	0
T11	0	4	0	0
T22	518	0	0	0
T29	0	6	0	0
T40	0	11	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	2	0	0
T76	0	6	0	0
T121	0	1	0	0
T122	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	38513	0	0
T4	314500	207	0	0
T7	13513	213	0	0
T8	947	0	0	0
T10	0	258	0	0
T11	0	288	0	0
T22	518	0	0	0
T29	0	282	0	0
T40	0	293	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	65	0	0
T76	0	840	0	0
T121	0	86	0	0
T122	0	356	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7714488	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32987	0	0
T5	27545	27084	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	49	0	0
T83	0	2	0	0
T100	5066	0	0	0
T101	10721	1	0	0
T108	0	2	0	0
T180	0	5	0	0
T257	0	1	0	0
T264	34111	1	0	0
T265	61649	0	0	0
T266	25651	0	0	0
T267	529	0	0	0
T268	495	0	0	0
T272	0	4	0	0
T280	0	11	0	0
T281	0	4	0	0
T282	0	10	0	0
T283	423	0	0	0
T284	521	0	0	0
T285	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	12613	0	0
T4	314500	170	0	0
T7	13513	230	0	0
T8	947	0	0	0
T10	0	161	0	0
T11	0	71	0	0
T22	518	0	0	0
T29	0	118	0	0
T40	0	86	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	4	0	0
T76	0	194	0	0
T122	0	30	0	0
T124	0	23	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	285	0	0
T4	314500	3	0	0
T7	13513	3	0	0
T8	947	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T29	0	3	0	0
T40	0	5	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	1	0	0
T76	0	3	0	0
T122	0	2	0	0
T124	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7378225	0	0
T1	7528	1705	0	0
T2	928	527	0	0
T3	33469	32677	0	0
T5	27545	22161	0	0
T6	497	96	0	0
T12	5216	4815	0	0
T13	409	8	0	0
T14	402	1	0	0
T15	703	302	0	0
T16	616	215	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7379988	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32687	0	0
T5	27545	22161	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	381	0	0
T4	314500	3	0	0
T7	13513	3	0	0
T8	947	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T29	0	3	0	0
T40	0	6	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	1	0	0
T76	0	3	0	0
T121	0	1	0	0
T122	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	340	0	0
T4	314500	3	0	0
T7	13513	3	0	0
T8	947	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T29	0	3	0	0
T40	0	5	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	1	0	0
T76	0	3	0	0
T122	0	2	0	0
T124	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	285	0	0
T4	314500	3	0	0
T7	13513	3	0	0
T8	947	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T29	0	3	0	0
T40	0	5	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	1	0	0
T76	0	3	0	0
T122	0	2	0	0
T124	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	285	0	0
T4	314500	3	0	0
T7	13513	3	0	0
T8	947	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T29	0	3	0	0
T40	0	5	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	1	0	0
T76	0	3	0	0
T122	0	2	0	0
T124	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	12298	0	0
T4	314500	166	0	0
T7	13513	227	0	0
T8	947	0	0	0
T10	0	158	0	0
T11	0	69	0	0
T22	518	0	0	0
T29	0	112	0	0
T40	0	81	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	3	0	0
T76	0	188	0	0
T122	0	28	0	0
T124	0	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	7717563	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8390318	252	0	0
T4	314500	2	0	0
T7	13513	3	0	0
T8	947	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T22	518	0	0	0
T40	0	5	0	0
T49	418	0	0	0
T50	811	0	0	0
T51	687	0	0	0
T52	452	0	0	0
T53	422	0	0	0
T54	442	0	0	0
T58	0	1	0	0
T80	0	8	0	0
T81	0	12	0	0
T122	0	2	0	0
T124	0	3	0	0