Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1150775352	10873	0	0
auto_block_debounce_ctl_rd_A	1150775352	2146	0	0
auto_block_out_ctl_rd_A	1150775352	2579	0	0
com_det_ctl_0_rd_A	1150775352	3469	0	0
com_det_ctl_1_rd_A	1150775352	3432	0	0
com_det_ctl_2_rd_A	1150775352	3535	0	0
com_det_ctl_3_rd_A	1150775352	3371	0	0
com_out_ctl_0_rd_A	1150775352	3972	0	0
com_out_ctl_1_rd_A	1150775352	4006	0	0
com_out_ctl_2_rd_A	1150775352	3943	0	0
com_out_ctl_3_rd_A	1150775352	4017	0	0
com_pre_det_ctl_0_rd_A	1150775352	1504	0	0
com_pre_det_ctl_1_rd_A	1150775352	1715	0	0
com_pre_det_ctl_2_rd_A	1150775352	1569	0	0
com_pre_det_ctl_3_rd_A	1150775352	1584	0	0
com_pre_sel_ctl_0_rd_A	1150775352	4092	0	0
com_pre_sel_ctl_1_rd_A	1150775352	4208	0	0
com_pre_sel_ctl_2_rd_A	1150775352	4187	0	0
com_pre_sel_ctl_3_rd_A	1150775352	4215	0	0
com_sel_ctl_0_rd_A	1150775352	3958	0	0
com_sel_ctl_1_rd_A	1150775352	4252	0	0
com_sel_ctl_2_rd_A	1150775352	4235	0	0
com_sel_ctl_3_rd_A	1150775352	4244	0	0
ec_rst_ctl_rd_A	1150775352	2440	0	0
intr_enable_rd_A	1150775352	2643	0	0
key_intr_ctl_rd_A	1150775352	3636	0	0
key_intr_debounce_ctl_rd_A	1150775352	1653	0	0
key_invert_ctl_rd_A	1150775352	5300	0	0
pin_allowed_ctl_rd_A	1150775352	6301	0	0
pin_out_ctl_rd_A	1150775352	4630	0	0
pin_out_value_rd_A	1150775352	4484	0	0
regwen_rd_A	1150775352	1858	0	0
ulp_ac_debounce_ctl_rd_A	1150775352	1746	0	0
ulp_ctl_rd_A	1150775352	1782	0	0
ulp_lid_debounce_ctl_rd_A	1150775352	1644	0	0
ulp_pwrb_debounce_ctl_rd_A	1150775352	1802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	10873	0	0
T1	361370	18	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	8	0	0
T6	108455	0	0	0
T11	0	15	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T32	0	5	0	0
T34	0	7	0	0
T67	0	7	0	0
T101	0	7	0	0
T116	0	11	0	0
T120	0	4	0	0
T147	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	2146	0	0
T43	175474	10	0	0
T47	0	14	0	0
T61	227165	0	0	0
T62	276001	0	0	0
T77	121921	0	0	0
T87	0	23	0	0
T93	0	45	0	0
T120	0	23	0	0
T121	430410	0	0	0
T136	10735	0	0	0
T137	217207	0	0	0
T138	251187	0	0	0
T139	201082	0	0	0
T147	0	1	0	0
T212	0	6	0	0
T230	0	12	0	0
T232	0	5	0	0
T308	0	18	0	0
T309	34363	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	2579	0	0
T43	175474	7	0	0
T47	0	19	0	0
T61	227165	0	0	0
T62	276001	0	0	0
T77	121921	0	0	0
T87	0	26	0	0
T93	0	34	0	0
T120	0	7	0	0
T121	430410	0	0	0
T136	10735	0	0	0
T137	217207	0	0	0
T138	251187	0	0	0
T139	201082	0	0	0
T212	0	6	0	0
T230	0	7	0	0
T232	0	8	0	0
T308	0	20	0	0
T309	34363	0	0	0
T310	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3469	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	86	0	0
T6	108455	0	0	0
T10	0	80	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	16	0	0
T147	0	4	0	0
T255	0	43	0	0
T257	0	90	0	0
T270	0	110	0	0
T311	0	58	0	0
T312	0	55	0	0
T313	0	31	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3432	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	79	0	0
T6	108455	0	0	0
T10	0	81	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	17	0	0
T147	0	8	0	0
T255	0	41	0	0
T257	0	58	0	0
T270	0	99	0	0
T311	0	42	0	0
T312	0	81	0	0
T313	0	40	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3535	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	65	0	0
T6	108455	0	0	0
T10	0	60	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	15	0	0
T147	0	6	0	0
T255	0	53	0	0
T257	0	71	0	0
T270	0	87	0	0
T311	0	48	0	0
T312	0	68	0	0
T313	0	25	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3371	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	72	0	0
T6	108455	0	0	0
T10	0	60	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	15	0	0
T147	0	1	0	0
T255	0	40	0	0
T257	0	69	0	0
T270	0	98	0	0
T311	0	50	0	0
T312	0	57	0	0
T313	0	20	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3972	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	70	0	0
T6	108455	0	0	0
T10	0	67	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	26	0	0
T147	0	8	0	0
T255	0	43	0	0
T257	0	71	0	0
T270	0	76	0	0
T311	0	47	0	0
T312	0	73	0	0
T313	0	24	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4006	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	59	0	0
T6	108455	0	0	0
T10	0	63	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	23	0	0
T147	0	3	0	0
T255	0	31	0	0
T257	0	59	0	0
T270	0	91	0	0
T311	0	67	0	0
T312	0	65	0	0
T313	0	37	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3943	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	85	0	0
T6	108455	0	0	0
T10	0	82	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	11	0	0
T147	0	7	0	0
T255	0	31	0	0
T257	0	75	0	0
T270	0	69	0	0
T311	0	56	0	0
T312	0	51	0	0
T313	0	33	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4017	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	72	0	0
T6	108455	0	0	0
T10	0	81	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	18	0	0
T147	0	2	0	0
T255	0	56	0	0
T257	0	65	0	0
T270	0	73	0	0
T311	0	50	0	0
T312	0	63	0	0
T313	0	28	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1504	0	0
T82	291721	0	0	0
T87	0	4	0	0
T93	0	46	0	0
T120	285962	22	0	0
T147	142349	10	0	0
T148	71031	0	0	0
T163	0	12	0	0
T168	72412	0	0	0
T239	0	9	0	0
T291	0	23	0	0
T310	0	6	0	0
T314	0	6	0	0
T315	0	30	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1715	0	0
T82	291721	0	0	0
T87	0	9	0	0
T93	0	20	0	0
T120	285962	19	0	0
T147	142349	3	0	0
T148	71031	0	0	0
T163	0	22	0	0
T168	72412	0	0	0
T239	0	11	0	0
T291	0	16	0	0
T310	0	22	0	0
T314	0	1	0	0
T315	0	13	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1569	0	0
T82	291721	0	0	0
T87	0	10	0	0
T93	0	18	0	0
T120	285962	16	0	0
T147	142349	1	0	0
T148	71031	0	0	0
T163	0	20	0	0
T168	72412	0	0	0
T239	0	12	0	0
T291	0	10	0	0
T310	0	2	0	0
T314	0	7	0	0
T315	0	11	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1584	0	0
T82	291721	0	0	0
T87	0	13	0	0
T93	0	53	0	0
T120	285962	10	0	0
T147	142349	4	0	0
T148	71031	0	0	0
T163	0	21	0	0
T168	72412	0	0	0
T239	0	13	0	0
T291	0	23	0	0
T310	0	5	0	0
T314	0	5	0	0
T315	0	19	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4092	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	73	0	0
T6	108455	0	0	0
T10	0	62	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	20	0	0
T147	0	3	0	0
T255	0	33	0	0
T257	0	69	0	0
T270	0	102	0	0
T311	0	49	0	0
T312	0	63	0	0
T313	0	36	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4208	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	61	0	0
T6	108455	0	0	0
T10	0	49	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	19	0	0
T147	0	4	0	0
T255	0	13	0	0
T257	0	52	0	0
T270	0	89	0	0
T311	0	59	0	0
T312	0	67	0	0
T313	0	37	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4187	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	62	0	0
T6	108455	0	0	0
T10	0	76	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	14	0	0
T147	0	5	0	0
T255	0	47	0	0
T257	0	63	0	0
T270	0	100	0	0
T311	0	54	0	0
T312	0	64	0	0
T313	0	32	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4215	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	65	0	0
T6	108455	0	0	0
T10	0	79	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	22	0	0
T147	0	5	0	0
T255	0	50	0	0
T257	0	72	0	0
T270	0	69	0	0
T311	0	40	0	0
T312	0	67	0	0
T313	0	25	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3958	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	58	0	0
T6	108455	0	0	0
T10	0	73	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	11	0	0
T147	0	9	0	0
T255	0	44	0	0
T257	0	58	0	0
T270	0	94	0	0
T311	0	69	0	0
T312	0	56	0	0
T313	0	22	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4252	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	65	0	0
T6	108455	0	0	0
T10	0	68	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	9	0	0
T147	0	3	0	0
T255	0	40	0	0
T257	0	71	0	0
T270	0	119	0	0
T311	0	51	0	0
T312	0	66	0	0
T313	0	39	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4235	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	78	0	0
T6	108455	0	0	0
T10	0	57	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	11	0	0
T147	0	2	0	0
T255	0	39	0	0
T257	0	72	0	0
T270	0	114	0	0
T311	0	49	0	0
T312	0	96	0	0
T313	0	25	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4244	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	69	0	0
T6	108455	0	0	0
T10	0	90	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T120	0	20	0	0
T147	0	2	0	0
T255	0	40	0	0
T257	0	69	0	0
T270	0	90	0	0
T311	0	41	0	0
T312	0	79	0	0
T313	0	40	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	2440	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T5	330545	29	0	0
T6	108455	0	0	0
T10	0	9	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T50	0	1	0	0
T51	0	6	0	0
T82	0	2	0	0
T99	0	6	0	0
T100	0	7	0	0
T120	0	39	0	0
T147	0	2	0	0
T255	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	2643	0	0
T82	291721	0	0	0
T87	0	7	0	0
T93	0	61	0	0
T120	285962	32	0	0
T147	142349	71	0	0
T148	71031	0	0	0
T163	0	41	0	0
T168	72412	0	0	0
T199	0	6	0	0
T239	0	24	0	0
T291	0	44	0	0
T310	0	32	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0
T321	0	21	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3636	0	0
T4	230093	0	0	0
T6	108455	4	0	0
T7	162156	0	0	0
T8	32821	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T31	0	8	0	0
T35	0	2	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T82	0	127	0	0
T93	0	32	0	0
T120	0	14	0	0
T147	0	3	0	0
T179	0	2	0	0
T199	0	4	0	0
T216	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1653	0	0
T82	291721	0	0	0
T87	0	12	0	0
T93	0	22	0	0
T120	285962	18	0	0
T147	142349	2	0	0
T148	71031	0	0	0
T163	0	15	0	0
T168	72412	0	0	0
T239	0	18	0	0
T291	0	19	0	0
T310	0	21	0	0
T314	0	3	0	0
T315	0	15	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5300	0	0
T10	681049	0	0	0
T23	329520	0	0	0
T35	0	52	0	0
T41	939622	0	0	0
T47	0	74	0	0
T65	248002	45	0	0
T66	52227	0	0	0
T74	60713	0	0	0
T87	0	224	0	0
T93	0	38	0	0
T120	0	14	0	0
T147	0	2	0	0
T149	0	44	0	0
T236	204660	0	0	0
T268	0	69	0	0
T322	0	68	0	0
T323	25569	0	0	0
T324	53646	0	0	0
T325	50526	0	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6301	0	0
T11	222019	0	0	0
T42	805795	0	0	0
T55	244132	0	0	0
T56	35816	0	0	0
T62	0	62	0	0
T67	206185	0	0	0
T93	0	35	0	0
T98	22536	0	0	0
T120	0	77	0	0
T138	0	54	0	0
T147	0	82	0	0
T199	0	67	0	0
T263	0	71	0	0
T318	0	44	0	0
T325	50526	39	0	0
T326	0	28	0	0
T327	16617	0	0	0
T328	250671	0	0	0
T329	64810	0	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4630	0	0
T11	222019	0	0	0
T42	805795	0	0	0
T55	244132	0	0	0
T56	35816	0	0	0
T62	0	74	0	0
T67	206185	0	0	0
T93	0	29	0	0
T98	22536	0	0	0
T120	0	60	0	0
T138	0	34	0	0
T147	0	85	0	0
T199	0	69	0	0
T263	0	49	0	0
T318	0	51	0	0
T325	50526	47	0	0
T326	0	42	0	0
T327	16617	0	0	0
T328	250671	0	0	0
T329	64810	0	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	4484	0	0
T11	222019	0	0	0
T42	805795	0	0	0
T55	244132	0	0	0
T56	35816	0	0	0
T62	0	79	0	0
T67	206185	0	0	0
T93	0	26	0	0
T98	22536	0	0	0
T120	0	104	0	0
T138	0	31	0	0
T147	0	70	0	0
T199	0	79	0	0
T263	0	57	0	0
T318	0	28	0	0
T325	50526	26	0	0
T326	0	40	0	0
T327	16617	0	0	0
T328	250671	0	0	0
T329	64810	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1858	0	0
T82	291721	0	0	0
T87	0	5	0	0
T93	0	32	0	0
T120	285962	8	0	0
T147	142349	5	0	0
T148	71031	0	0	0
T163	0	18	0	0
T168	72412	0	0	0
T239	0	18	0	0
T291	0	11	0	0
T310	0	6	0	0
T314	0	14	0	0
T315	0	21	0	0
T316	198846	0	0	0
T317	28871	0	0	0
T318	63058	0	0	0
T319	202631	0	0	0
T320	36979	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1746	0	0
T8	32821	10	0	0
T22	18134	0	0	0
T47	0	3	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T59	132081	0	0	0
T61	0	3	0	0
T62	0	3	0	0
T69	98405	0	0	0
T77	0	11	0	0
T87	0	30	0	0
T93	0	38	0	0
T96	0	2	0	0
T120	0	31	0	0
T123	53093	0	0	0
T147	0	5	0	0
T288	156475	0	0	0
T330	48037	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1782	0	0
T8	32821	7	0	0
T22	18134	0	0	0
T47	0	7	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T59	132081	0	0	0
T61	0	8	0	0
T62	0	1	0	0
T69	98405	0	0	0
T77	0	2	0	0
T93	0	42	0	0
T96	0	1	0	0
T120	0	26	0	0
T123	53093	0	0	0
T125	0	12	0	0
T147	0	4	0	0
T288	156475	0	0	0
T330	48037	0	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1644	0	0
T8	32821	10	0	0
T22	18134	0	0	0
T47	0	3	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T59	132081	0	0	0
T61	0	4	0	0
T62	0	3	0	0
T69	98405	0	0	0
T77	0	11	0	0
T93	0	31	0	0
T96	0	1	0	0
T120	0	20	0	0
T123	53093	0	0	0
T125	0	3	0	0
T147	0	5	0	0
T288	156475	0	0	0
T330	48037	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1802	0	0
T8	32821	5	0	0
T22	18134	0	0	0
T47	0	9	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T59	132081	0	0	0
T61	0	4	0	0
T62	0	4	0	0
T69	98405	0	0	0
T77	0	9	0	0
T93	0	33	0	0
T96	0	2	0	0
T120	0	26	0	0
T123	53093	0	0	0
T125	0	10	0	0
T147	0	4	0	0
T288	156475	0	0	0
T330	48037	0	0	0