Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T3,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T11
1	-	Covered	T3,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	94114209	0	0
DstReqKnown_A	294271496	264835826	0	0
SrcAckBusyChk_A	2147483647	116198	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	94114209	0	0
T1	6866030	5736	0	0
T2	4410299	0	0	0
T3	12651471	38567	0	0
T4	2531023	13839	0	0
T5	4958175	32129	0	0
T6	2928285	0	0	0
T7	486468	10524	0	0
T8	98463	0	0	0
T10	0	3614	0	0
T11	0	4924	0	0
T12	6759855	12200	0	0
T13	607311	0	0	0
T14	5329989	0	0	0
T15	2449485	3217	0	0
T16	8583797	0	0	0
T17	347830	0	0	0
T22	18134	0	0	0
T23	0	14053	0	0
T37	0	53534	0	0
T38	0	55538	0	0
T40	0	144336	0	0
T41	0	6851	0	0
T42	0	1992	0	0
T43	0	6204	0	0
T44	0	3701	0	0
T45	0	12450	0	0
T46	0	13487	0	0
T47	0	1673	0	0
T48	0	2961	0	0
T49	1105500	0	0	0
T50	280056	0	0	0
T51	123807	0	0	0
T52	135735	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294271496	264835826	0	0
T1	255952	58446	0	0
T2	31552	17952	0	0
T3	1137946	1121898	0	0
T5	936530	921230	0	0
T6	16898	3298	0	0
T12	177344	163744	0	0
T13	13906	306	0	0
T14	13668	68	0	0
T15	23902	10302	0	0
T16	20944	7344	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116198	0	0
T1	6866030	4	0	0
T2	4410299	0	0	0
T3	12651471	90	0	0
T4	2531023	66	0	0
T5	4958175	88	0	0
T6	2928285	0	0	0
T7	486468	27	0	0
T8	98463	0	0	0
T10	0	24	0	0
T11	0	14	0	0
T12	6759855	9	0	0
T13	607311	0	0	0
T14	5329989	0	0	0
T15	2449485	8	0	0
T16	8583797	0	0	0
T17	347830	0	0	0
T22	18134	0	0	0
T23	0	8	0	0
T37	0	36	0	0
T38	0	72	0	0
T40	0	88	0	0
T41	0	9	0	0
T42	0	1	0	0
T43	0	7	0	0
T44	0	9	0	0
T45	0	7	0	0
T46	0	8	0	0
T47	0	7	0	0
T48	0	7	0	0
T49	1105500	0	0	0
T50	280056	0	0	0
T51	123807	0	0	0
T52	135735	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12286580	12225074	0	0
T2	7892114	7890312	0	0
T3	15931482	15896870	0	0
T5	11238530	11217824	0	0
T6	3687470	3685736	0	0
T12	8512410	8512138	0	0
T13	764762	762110	0	0
T14	6711838	6709594	0	0
T15	2871810	2869940	0	0
T16	10063762	10060362	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T3,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T24,T25,T26
1	-	Covered	T3,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T3,T4,T7
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T3,T4,T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	877304	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1031	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	877304	0	0
T3	468573	3471	0	0
T4	230093	786	0	0
T6	108455	0	0	0
T7	162156	2087	0	0
T8	0	227	0	0
T10	0	471	0	0
T11	0	1501	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T55	0	3866	0	0
T56	0	200	0	0
T57	0	449	0	0
T58	0	9039	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1031	0	0
T3	468573	8	0	0
T4	230093	4	0	0
T6	108455	0	0	0
T7	162156	5	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	4	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1606039	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	2002	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1606039	0	0
T1	361370	2862	0	0
T2	232121	0	0	0
T3	468573	4083	0	0
T4	0	1721	0	0
T5	330545	4532	0	0
T6	108455	0	0	0
T7	0	1251	0	0
T12	250365	1285	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	1901	0	0
T50	0	325	0	0
T51	0	153	0	0
T59	0	495	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	2002	0	0
T1	361370	2	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	8	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T8,T28
1	1	Covered	T4,T8,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T28
1	1	Covered	T4,T8,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T28
0	0	1	Covered	T4,T8,T28
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T28
0	0	1	Covered	T4,T8,T28
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	874913	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1129	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	874913	0	0
T4	230093	856	0	0
T7	162156	0	0	0
T8	32821	531	0	0
T11	0	378	0	0
T22	18134	0	0	0
T28	0	4750	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	3874	0	0
T56	0	725	0	0
T57	0	1415	0	0
T60	0	97	0	0
T61	0	3406	0	0
T62	0	360	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1129	0	0
T4	230093	4	0	0
T7	162156	0	0	0
T8	32821	2	0	0
T11	0	1	0	0
T22	18134	0	0	0
T28	0	3	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	2	0	0
T56	0	3	0	0
T57	0	3	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T8,T28
1	1	Covered	T4,T8,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T28
1	1	Covered	T4,T8,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T28
0	0	1	Covered	T4,T8,T28
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T28
0	0	1	Covered	T4,T8,T28
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	863231	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1086	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	863231	0	0
T4	230093	817	0	0
T7	162156	0	0	0
T8	32821	516	0	0
T11	0	376	0	0
T22	18134	0	0	0
T28	0	4744	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	3870	0	0
T56	0	704	0	0
T57	0	1388	0	0
T60	0	89	0	0
T61	0	3385	0	0
T62	0	343	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1086	0	0
T4	230093	4	0	0
T7	162156	0	0	0
T8	32821	2	0	0
T11	0	1	0	0
T22	18134	0	0	0
T28	0	3	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	2	0	0
T56	0	3	0	0
T57	0	3	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T8,T28
1	1	Covered	T4,T8,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T28
1	1	Covered	T4,T8,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T28
0	0	1	Covered	T4,T8,T28
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T28
0	0	1	Covered	T4,T8,T28
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	867770	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1094	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	867770	0	0
T4	230093	795	0	0
T7	162156	0	0	0
T8	32821	485	0	0
T11	0	374	0	0
T22	18134	0	0	0
T28	0	4738	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	3866	0	0
T56	0	677	0	0
T57	0	1369	0	0
T60	0	84	0	0
T61	0	3376	0	0
T62	0	327	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1094	0	0
T4	230093	4	0	0
T7	162156	0	0	0
T8	32821	2	0	0
T11	0	1	0	0
T22	18134	0	0	0
T28	0	3	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	2	0	0
T56	0	3	0	0
T57	0	3	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T4,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T4,T21
1	1	Covered	T1,T4,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T4,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T21
1	1	Covered	T1,T4,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T4,T21
0	0	1	Covered	T1,T4,T21
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T4,T21
0	0	1	Covered	T1,T4,T21
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	2853605	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	3349	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	2853605	0	0
T1	361370	33602	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	9583	0	0
T6	108455	0	0	0
T11	0	26419	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T21	0	34678	0	0
T63	0	35051	0	0
T64	0	16117	0	0
T65	0	36871	0	0
T66	0	7220	0	0
T67	0	68608	0	0
T68	0	7346	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	3349	0	0
T1	361370	20	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	40	0	0
T6	108455	0	0	0
T11	0	80	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T21	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	40	0	0
T68	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T4,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T4,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T4,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T4,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T4,T22
0	0	1	Covered	T1,T4,T22
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T4,T22
0	0	1	Covered	T1,T4,T22
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	5603404	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	6922	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5603404	0	0
T1	361370	100130	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	32316	0	0
T6	108455	0	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T21	0	1946	0	0
T22	0	1932	0	0
T63	0	1972	0	0
T64	0	685	0	0
T69	0	13971	0	0
T70	0	17449	0	0
T71	0	9054	0	0
T72	0	15108	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6922	0	0
T1	361370	59	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	142	0	0
T6	108455	0	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T21	0	1	0	0
T22	0	20	0	0
T63	0	1	0	0
T64	0	1	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	6647275	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	8053	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6647275	0	0
T1	361370	108496	0	0
T2	232121	0	0	0
T3	468573	4443	0	0
T4	0	36583	0	0
T5	330545	4444	0	0
T6	108455	0	0	0
T7	0	1281	0	0
T12	250365	1423	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	1910	0	0
T22	0	2206	0	0
T50	0	335	0	0
T51	0	165	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	8053	0	0
T1	361370	64	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	152	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	1	0	0
T22	0	20	0	0
T50	0	1	0	0
T51	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T4,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T4,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T4,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T4,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T4,T22
0	0	1	Covered	T1,T4,T22
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T4,T22
0	0	1	Covered	T1,T4,T22
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	5540879	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	6832	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5540879	0	0
T1	361370	98815	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	32901	0	0
T6	108455	0	0	0
T9	0	7780	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T22	0	2055	0	0
T69	0	14011	0	0
T70	0	17489	0	0
T71	0	9094	0	0
T72	0	15148	0	0
T73	0	5312	0	0
T74	0	8367	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6832	0	0
T1	361370	58	0	0
T2	232121	0	0	0
T3	468573	0	0	0
T4	0	140	0	0
T6	108455	0	0	0
T9	0	60	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T22	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	888265	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1121	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	888265	0	0
T1	361370	1436	0	0
T2	232121	992	0	0
T3	468573	0	0	0
T4	0	473	0	0
T6	108455	976	0	0
T9	0	141	0	0
T11	0	1891	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T32	0	991	0	0
T34	0	698	0	0
T36	0	746	0	0
T67	0	1469	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1121	0	0
T1	361370	1	0	0
T2	232121	1	0	0
T3	468573	0	0	0
T4	0	2	0	0
T6	108455	1	0	0
T9	0	1	0	0
T11	0	5	0	0
T12	250365	0	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1602149	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1996	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1602149	0	0
T1	361370	4773	0	0
T2	232121	980	0	0
T3	468573	4063	0	0
T4	0	2180	0	0
T5	330545	4543	0	0
T6	108455	963	0	0
T7	0	1224	0	0
T12	250365	1279	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T38	0	5534	0	0
T40	0	17921	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1996	0	0
T1	361370	3	0	0
T2	232121	1	0	0
T3	468573	10	0	0
T4	0	10	0	0
T5	330545	11	0	0
T6	108455	1	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T38	0	8	0	0
T40	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T15,T4,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T15,T4,T23
1	1	Covered	T15,T4,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T15,T4,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T4,T23
1	1	Covered	T15,T4,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T15,T4,T23
0	0	1	Covered	T15,T4,T23
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T15,T4,T23
0	0	1	Covered	T15,T4,T23
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1162595	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1429	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1162595	0	0
T4	230093	1701	0	0
T7	162156	0	0	0
T8	32821	0	0	0
T11	0	2753	0	0
T15	84465	2032	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T23	0	8727	0	0
T43	0	3594	0	0
T44	0	2514	0	0
T45	0	6985	0	0
T46	0	8497	0	0
T47	0	938	0	0
T48	0	1732	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1429	0	0
T4	230093	8	0	0
T7	162156	0	0	0
T8	32821	0	0	0
T11	0	8	0	0
T15	84465	5	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T23	0	5	0	0
T43	0	4	0	0
T44	0	6	0	0
T45	0	4	0	0
T46	0	5	0	0
T47	0	4	0	0
T48	0	4	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T15,T4,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T15,T4,T23
1	1	Covered	T15,T4,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T15,T4,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T4,T23
1	1	Covered	T15,T4,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T15,T4,T23
0	0	1	Covered	T15,T4,T23
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T15,T4,T23
0	0	1	Covered	T15,T4,T23
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1018910	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1266	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1018910	0	0
T4	230093	1260	0	0
T7	162156	0	0	0
T8	32821	0	0	0
T11	0	2171	0	0
T15	84465	1185	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T23	0	5326	0	0
T43	0	2610	0	0
T44	0	1187	0	0
T45	0	5465	0	0
T46	0	4990	0	0
T47	0	735	0	0
T48	0	1229	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1266	0	0
T4	230093	6	0	0
T7	162156	0	0	0
T8	32821	0	0	0
T11	0	6	0	0
T15	84465	3	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T23	0	3	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	5682262	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	6938	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5682262	0	0
T3	468573	36070	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	34944	0	0
T12	250365	85878	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	145254	0	0
T37	0	131422	0	0
T38	0	58495	0	0
T39	0	70001	0	0
T41	0	36203	0	0
T42	0	88406	0	0
T49	100500	0	0	0
T75	0	551	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6938	0	0
T3	468573	75	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	85	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	83	0	0
T37	0	78	0	0
T38	0	68	0	0
T39	0	92	0	0
T41	0	51	0	0
T42	0	51	0	0
T49	100500	0	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	5594488	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	6861	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5594488	0	0
T3	468573	32422	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	25501	0	0
T12	250365	85099	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	122379	0	0
T37	0	90028	0	0
T38	0	49121	0	0
T39	0	48589	0	0
T41	0	35993	0	0
T42	0	87483	0	0
T49	100500	0	0	0
T76	0	18052	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6861	0	0
T3	468573	68	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	65	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	71	0	0
T37	0	54	0	0
T38	0	58	0	0
T39	0	65	0	0
T41	0	51	0	0
T42	0	51	0	0
T49	100500	0	0	0
T76	0	88	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	5509585	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	6980	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5509585	0	0
T3	468573	32090	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	24888	0	0
T12	250365	84366	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	143041	0	0
T37	0	135291	0	0
T38	0	56328	0	0
T39	0	47949	0	0
T41	0	35783	0	0
T42	0	86556	0	0
T49	100500	0	0	0
T76	0	14046	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6980	0	0
T3	468573	68	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	65	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	83	0	0
T37	0	81	0	0
T38	0	68	0	0
T39	0	65	0	0
T41	0	51	0	0
T42	0	51	0	0
T49	100500	0	0	0
T76	0	71	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	5627855	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	7048	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	5627855	0	0
T3	468573	38890	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	23871	0	0
T12	250365	83682	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	93206	0	0
T37	0	134095	0	0
T38	0	55206	0	0
T39	0	68554	0	0
T41	0	35573	0	0
T42	0	85554	0	0
T49	100500	0	0	0
T76	0	11478	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	7048	0	0
T3	468573	83	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	65	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	55	0	0
T37	0	81	0	0
T38	0	68	0	0
T39	0	94	0	0
T41	0	51	0	0
T42	0	51	0	0
T49	100500	0	0	0
T76	0	60	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1044573	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1315	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1044573	0	0
T3	468573	4463	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	1273	0	0
T12	250365	1426	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	8429	0	0
T37	0	6188	0	0
T38	0	6672	0	0
T39	0	853	0	0
T41	0	779	0	0
T42	0	1992	0	0
T49	100500	0	0	0
T75	0	548	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1315	0	0
T3	468573	10	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	5	0	0
T37	0	4	0	0
T38	0	8	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	100500	0	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1028410	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1324	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1028410	0	0
T3	468573	4363	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	1174	0	0
T12	250365	1376	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	8243	0	0
T37	0	6039	0	0
T38	0	6403	0	0
T39	0	812	0	0
T41	0	769	0	0
T42	0	1952	0	0
T49	100500	0	0	0
T76	0	1863	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1324	0	0
T3	468573	10	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	5	0	0
T37	0	4	0	0
T38	0	8	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	100500	0	0	0
T76	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1021855	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1307	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1021855	0	0
T3	468573	4263	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	1094	0	0
T12	250365	1343	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	8095	0	0
T37	0	5899	0	0
T38	0	6095	0	0
T39	0	787	0	0
T41	0	759	0	0
T42	0	1909	0	0
T49	100500	0	0	0
T76	0	1763	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1307	0	0
T3	468573	10	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	5	0	0
T37	0	4	0	0
T38	0	8	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	100500	0	0	0
T76	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	999724	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1311	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	999724	0	0
T3	468573	4163	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	1106	0	0
T12	250365	1314	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	7949	0	0
T37	0	5795	0	0
T38	0	5840	0	0
T39	0	749	0	0
T41	0	749	0	0
T42	0	1859	0	0
T49	100500	0	0	0
T76	0	1663	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1311	0	0
T3	468573	10	0	0
T4	230093	0	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T17	24845	0	0	0
T29	0	5	0	0
T37	0	4	0	0
T38	0	8	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	100500	0	0	0
T76	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	6212637	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	7518	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6212637	0	0
T1	361370	2874	0	0
T2	232121	0	0	0
T3	468573	36160	0	0
T4	0	1908	0	0
T5	330545	4742	0	0
T6	108455	0	0	0
T7	0	35476	0	0
T12	250365	86200	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	131911	0	0
T38	0	58835	0	0
T40	0	18207	0	0
T41	0	36299	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	7518	0	0
T1	361370	2	0	0
T2	232121	0	0	0
T3	468573	75	0	0
T4	0	8	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	85	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	78	0	0
T38	0	68	0	0
T40	0	11	0	0
T41	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	6083528	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	7371	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6083528	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	32498	0	0
T4	0	1400	0	0
T5	330545	4626	0	0
T6	108455	0	0	0
T7	0	25908	0	0
T10	0	638	0	0
T12	250365	85465	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	90302	0	0
T38	0	49391	0	0
T40	0	18185	0	0
T41	0	36089	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	7371	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	68	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	65	0	0
T10	0	4	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	54	0	0
T38	0	58	0	0
T40	0	11	0	0
T41	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	6047761	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	7537	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6047761	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	32166	0	0
T4	0	1348	0	0
T5	330545	4499	0	0
T6	108455	0	0	0
T7	0	25195	0	0
T10	0	601	0	0
T12	250365	84704	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	135825	0	0
T38	0	56675	0	0
T40	0	18163	0	0
T41	0	35879	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	7537	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	68	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	65	0	0
T10	0	4	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	81	0	0
T38	0	68	0	0
T40	0	11	0	0
T41	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	6082110	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	7508	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	6082110	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	38996	0	0
T4	0	1287	0	0
T5	330545	4374	0	0
T6	108455	0	0	0
T7	0	24495	0	0
T10	0	556	0	0
T12	250365	84008	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	134545	0	0
T38	0	55535	0	0
T40	0	18141	0	0
T41	0	35669	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	7508	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	83	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	65	0	0
T10	0	4	0	0
T12	250365	51	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	81	0	0
T38	0	68	0	0
T40	0	11	0	0
T41	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1542746	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1895	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1542746	0	0
T1	361370	2870	0	0
T2	232121	0	0	0
T3	468573	4423	0	0
T4	0	1697	0	0
T5	330545	4246	0	0
T6	108455	0	0	0
T7	0	1232	0	0
T12	250365	1404	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	6124	0	0
T38	0	6552	0	0
T40	0	18119	0	0
T41	0	775	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1895	0	0
T1	361370	2	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	8	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1475263	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1811	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1475263	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	4323	0	0
T4	0	1211	0	0
T5	330545	4133	0	0
T6	108455	0	0	0
T7	0	1144	0	0
T10	0	610	0	0
T12	250365	1363	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	5990	0	0
T38	0	6266	0	0
T40	0	18097	0	0
T41	0	765	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1811	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1507409	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1865	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1507409	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	4223	0	0
T4	0	1226	0	0
T5	330545	4019	0	0
T6	108455	0	0	0
T7	0	1056	0	0
T10	0	620	0	0
T12	250365	1332	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	5863	0	0
T38	0	6003	0	0
T40	0	18075	0	0
T41	0	755	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1865	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1475206	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1832	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1475206	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	4123	0	0
T4	0	1178	0	0
T5	330545	3913	0	0
T6	108455	0	0	0
T7	0	1183	0	0
T10	0	584	0	0
T12	250365	1305	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	5749	0	0
T38	0	5715	0	0
T40	0	18053	0	0
T41	0	745	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1832	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T12
1	1	Covered	T5,T1,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T12
0	0	1	Covered	T5,T1,T12
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1521869	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1879	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1521869	0	0
T1	361370	2866	0	0
T2	232121	0	0	0
T3	468573	4403	0	0
T4	0	1629	0	0
T5	330545	3795	0	0
T6	108455	0	0	0
T7	0	1212	0	0
T12	250365	1392	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	6103	0	0
T38	0	6501	0	0
T40	0	18031	0	0
T41	0	773	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1879	0	0
T1	361370	2	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	8	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1465241	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1827	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1465241	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	4303	0	0
T4	0	1289	0	0
T5	330545	3792	0	0
T6	108455	0	0	0
T7	0	1120	0	0
T10	0	640	0	0
T12	250365	1354	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	5953	0	0
T38	0	6212	0	0
T40	0	18009	0	0
T41	0	763	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1827	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1493719	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1863	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1493719	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	4203	0	0
T4	0	1309	0	0
T5	330545	4056	0	0
T6	108455	0	0	0
T7	0	1029	0	0
T10	0	599	0	0
T12	250365	1330	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	5842	0	0
T38	0	5955	0	0
T40	0	17987	0	0
T41	0	753	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1863	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T12,T3
1	1	Covered	T5,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T12,T3
0	0	1	Covered	T5,T12,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	1460035	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1835	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1460035	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	4103	0	0
T4	0	1339	0	0
T5	330545	4175	0	0
T6	108455	0	0	0
T7	0	1275	0	0
T10	0	561	0	0
T12	250365	1294	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	5722	0	0
T38	0	5662	0	0
T40	0	17965	0	0
T41	0	743	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1835	0	0
T1	361370	0	0	0
T2	232121	0	0	0
T3	468573	10	0	0
T4	0	6	0	0
T5	330545	11	0	0
T6	108455	0	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	250365	1	0	0
T13	22493	0	0	0
T14	197407	0	0	0
T15	84465	0	0	0
T16	295993	0	0	0
T37	0	4	0	0
T38	0	8	0	0
T40	0	11	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T8,T11
1	1	Covered	T4,T8,T11

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T11
1	-	Covered	T4,T8,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T4,T8,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T11
1	1	Covered	T4,T8,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T11
0	0	1	Covered	T4,T8,T11
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T4,T8,T11
0	0	1	Covered	T4,T8,T11
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150775352	831594	0	0
DstReqKnown_A	8655044	7789289	0	0
SrcAckBusyChk_A	1150775352	1063	0	0
SrcBusyKnown_A	1150775352	1149002355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	831594	0	0
T4	230093	1226	0	0
T7	162156	0	0	0
T8	32821	518	0	0
T11	0	659	0	0
T22	18134	0	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	7262	0	0
T56	0	505	0	0
T57	0	936	0	0
T61	0	3395	0	0
T77	0	3492	0	0
T78	0	396	0	0
T79	0	864	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8655044	7789289	0	0
T1	7528	1719	0	0
T2	928	528	0	0
T3	33469	32997	0	0
T5	27545	27095	0	0
T6	497	97	0	0
T12	5216	4816	0	0
T13	409	9	0	0
T14	402	2	0	0
T15	703	303	0	0
T16	616	216	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1063	0	0
T4	230093	6	0	0
T7	162156	0	0	0
T8	32821	2	0	0
T11	0	2	0	0
T22	18134	0	0	0
T49	100500	0	0	0
T50	93352	0	0	0
T51	41269	0	0	0
T52	45245	0	0	0
T53	206974	0	0	0
T54	15483	0	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	2	0	0
T61	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150775352	1149002355	0	0
T1	361370	359561	0	0
T2	232121	232068	0	0
T3	468573	467555	0	0
T5	330545	329936	0	0
T6	108455	108404	0	0
T12	250365	250357	0	0
T13	22493	22415	0	0
T14	197407	197341	0	0
T15	84465	84410	0	0
T16	295993	295893	0	0