Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T2

30

T9

31

T10

7

auto[1]

567

1

T2

6

T9

1

T10

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1758

1

T2

23

T9

29

T10

8

auto[1]

621

1

T2

13

T9

3

T10

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1737

1

T2

36

T9

29

T10

8

auto[1]

642

1

T9

3

T10

2

T48

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1797

1

T2

36

T9

24

T10

3

auto[1]

582

1

T9

8

T10

7

T48

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2145

1

T2

29

T9

29

T10

10

auto[1]

234

1

T2

7

T9

3

T41

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2066

1

T2

36

T9

32

T10

10

auto[1]

313

1

T41

2

T47

2

T49

16

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2154

1

T2

23

T9

30

T10

10

auto[1]

225

1

T2

13

T9

2

T41

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2151

1

T2

30

T9

30

T10

10

auto[1]

228

1

T2

6

T9

2

T47

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2200

1

T2

36

T9

24

T10

10

auto[1]

179

1

T9

8

T75

2

T262

15

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1721

1

T2

36

T9

27

T10

7

auto[1]

658

1

T9

5

T10

3

T48

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

747

1

T10

10

T48

8

T40

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

43

1

T9

3

T41

3

T263

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

75

1

T9

8

T262

8

T362

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T278

1

T261

2

T213

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T210

8

T272

1

T186

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T262

14

T363

3

T359

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

11

1

T262

7

T364

3

T365

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T277

8

T366

16

T367

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T2

7

T107

1

T368

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T369

2

T370

4

T232

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T2

6

T9

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T361

6

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T75

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

104

1

T49

8

T263

1

T278

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

36

1

T371

2

T370

4

T361

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22

1

T85

1

T368

2

T186

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T261

1

T356

8

T372

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T47

2

T373

4

T213

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T213

5

T374

12

T375

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T366

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

18

1

T41

2

T49

8

T107

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T87

1

T376

2

T374

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T377

4

T361

5

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T38

8

T75

1

T49

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

94

1

T9

1

T47

2

T104

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

54

1

T9

1

T63

1

T113

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

118

1

T9

8

T10

7

T41

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

42

1

T39

3

T276

4

T63

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T277

4

T313

7

T112

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T48

3

T107

2

T366

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T43

11

T49

8

T85

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T57

4

T85

1

T366

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

102

1

T39

6

T262

7

T110

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

51

1

T10

1

T33

3

T276

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

89

1

T104

4

T105

1

T267

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T33

1

T263

1

T278

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T48

3

T112

1

T115

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T38

1

T105

1

T273

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

80

1

T2

7

T262

7

T261

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

63

1

T2

6

T47

1

T39

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T40

2

T312

4

T349

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T10

1

T48

2

T349

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T40

2

T41

3

T57

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T63

2

T275

5

T369

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T104

1

T313

3

T273

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T38

1

T232

5

T118

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

67

1

T33

3

T57

3

T278

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T349

2

T313

3

T274

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T9

3

T312

3

T347

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T10

1

T43

2

T39

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T39

4

T213

4

T269

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T39

2

T378

1

T97

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T43

1

T267

1

T280

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T379

1

T380

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded