Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.33	96.81	100.00	97.44	98.74	99.61	93.69

Total tests in report: 915

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.87	51.87	67.31	67.31	55.03	55.03	89.27	89.27	2.56	2.56	70.68	70.68	54.82	54.82	23.38	23.38	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.53162595
67.07	15.21	85.20	17.90	77.78	22.75	95.43	6.16	17.95	15.38	85.47	14.79	74.28	19.46	33.38	10.00	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1751766169
77.72	10.65	91.12	5.92	84.28	6.50	95.66	0.23	62.18	44.23	90.83	5.36	85.74	11.46	34.26	0.87	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.455144568
83.43	5.70	95.02	3.90	89.36	5.08	96.12	0.46	72.44	10.26	95.12	4.29	90.75	5.01	45.18	10.92	/workspace/coverage/default/27.sysrst_ctrl_stress_all.3441829501
86.87	3.45	97.20	2.18	92.11	2.76	97.49	1.37	78.21	5.77	96.64	1.52	95.18	4.43	51.28	6.10	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.972366508
88.91	2.04	97.24	0.04	92.14	0.03	97.49	0.00	78.21	0.00	96.71	0.07	95.18	0.00	65.44	14.15	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3410526903
90.35	1.44	97.78	0.54	92.16	0.03	97.49	0.00	87.18	8.97	97.23	0.52	95.18	0.00	65.44	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1238543420
91.40	1.05	97.85	0.07	93.33	1.16	98.17	0.68	87.18	0.00	97.34	0.11	95.18	0.00	70.77	5.33	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.392261273
92.38	0.98	98.04	0.19	93.73	0.40	98.17	0.00	87.18	0.00	97.45	0.11	95.18	0.00	76.92	6.15	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2127001405
93.14	0.75	98.45	0.41	94.29	0.56	98.17	0.00	89.74	2.56	97.78	0.33	96.44	1.25	77.08	0.15	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.2468925274
93.76	0.63	98.54	0.09	94.34	0.05	98.17	0.00	91.03	1.28	97.93	0.15	96.63	0.19	79.69	2.62	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3349047906
94.30	0.54	98.64	0.09	94.41	0.08	98.17	0.00	92.31	1.28	98.04	0.11	96.82	0.19	81.69	2.00	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1043283115
94.66	0.36	98.75	0.11	94.49	0.08	98.17	0.00	94.23	1.92	98.15	0.11	97.11	0.29	81.69	0.00	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3791607873
94.97	0.32	98.75	0.00	94.59	0.10	98.17	0.00	94.23	0.00	98.15	0.00	97.78	0.67	83.13	1.44	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4035711133
95.28	0.31	98.84	0.09	94.64	0.05	98.17	0.00	95.51	1.28	98.26	0.11	97.98	0.19	83.54	0.41	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2222650152
95.56	0.28	98.84	0.00	94.67	0.03	99.77	1.60	95.51	0.00	98.26	0.00	98.07	0.10	83.79	0.26	/workspace/coverage/default/2.sysrst_ctrl_sec_cm.118635205
95.79	0.22	98.86	0.02	94.79	0.13	99.77	0.00	95.51	0.00	98.26	0.00	98.17	0.10	85.13	1.33	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1978135104
95.98	0.20	98.86	0.00	94.79	0.00	99.77	0.00	95.51	0.00	98.26	0.00	98.17	0.00	86.51	1.38	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.4053522285
96.16	0.18	98.92	0.06	94.79	0.00	99.77	0.00	95.51	0.00	98.26	0.00	98.55	0.39	87.33	0.82	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3249620970
96.34	0.17	98.96	0.04	95.20	0.40	99.77	0.00	96.15	0.64	98.30	0.04	98.65	0.10	87.33	0.00	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.936651797
96.49	0.16	98.96	0.00	95.98	0.78	99.77	0.00	96.15	0.00	98.30	0.00	98.65	0.00	87.64	0.31	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3377284927
96.63	0.14	98.99	0.04	96.06	0.08	99.77	0.00	96.79	0.64	98.34	0.04	98.84	0.19	87.64	0.00	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.1804127717
96.77	0.14	99.07	0.07	96.08	0.03	99.77	0.00	97.44	0.64	98.45	0.11	98.94	0.10	87.64	0.00	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1333054899
96.89	0.12	99.07	0.00	96.08	0.00	99.77	0.00	97.44	0.00	98.45	0.00	98.94	0.00	88.51	0.87	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.3611312486
97.00	0.10	99.07	0.00	96.08	0.00	99.77	0.00	97.44	0.00	98.45	0.00	98.94	0.00	89.23	0.72	/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2840153792
97.08	0.08	99.09	0.02	96.08	0.00	99.77	0.00	97.44	0.00	98.45	0.00	98.94	0.00	89.79	0.56	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2248117238
97.14	0.06	99.10	0.02	96.08	0.00	99.77	0.00	97.44	0.00	98.45	0.00	98.94	0.00	90.21	0.41	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1298760261
97.20	0.06	99.10	0.00	96.21	0.13	99.77	0.00	97.44	0.00	98.45	0.00	99.13	0.19	90.31	0.10	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.623555542
97.26	0.06	99.10	0.00	96.21	0.00	99.77	0.00	97.44	0.00	98.45	0.00	99.13	0.00	90.72	0.41	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.1234838315
97.31	0.05	99.16	0.06	96.28	0.08	100.00	0.23	97.44	0.00	98.45	0.00	99.13	0.00	90.72	0.00	/workspace/coverage/default/13.sysrst_ctrl_alert_test.1991704058
97.36	0.05	99.20	0.04	96.44	0.15	100.00	0.00	97.44	0.00	98.52	0.07	99.23	0.10	90.72	0.00	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2722267108
97.41	0.05	99.20	0.00	96.44	0.00	100.00	0.00	97.44	0.00	98.52	0.00	99.23	0.00	91.08	0.36	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2493194773
97.47	0.05	99.22	0.02	96.44	0.00	100.00	0.00	97.44	0.00	98.52	0.00	99.52	0.29	91.13	0.05	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3056193935
97.50	0.04	99.22	0.00	96.71	0.28	100.00	0.00	97.44	0.00	98.52	0.00	99.52	0.00	91.13	0.00	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.570433518
97.54	0.04	99.22	0.00	96.74	0.03	100.00	0.00	97.44	0.00	98.52	0.00	99.61	0.10	91.28	0.15	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1100476760
97.58	0.04	99.22	0.00	96.74	0.00	100.00	0.00	97.44	0.00	98.52	0.00	99.61	0.00	91.54	0.26	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2950441430
97.61	0.03	99.22	0.00	96.74	0.00	100.00	0.00	97.44	0.00	98.52	0.00	99.61	0.00	91.74	0.21	/workspace/coverage/default/18.sysrst_ctrl_stress_all.4201705620
97.64	0.03	99.22	0.00	96.74	0.00	100.00	0.00	97.44	0.00	98.52	0.00	99.61	0.00	91.95	0.21	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1500049665
97.66	0.02	99.23	0.02	96.74	0.00	100.00	0.00	97.44	0.00	98.56	0.04	99.61	0.00	92.05	0.10	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1786101639
97.68	0.02	99.23	0.00	96.74	0.00	100.00	0.00	97.44	0.00	98.56	0.00	99.61	0.00	92.21	0.15	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.533249185
97.71	0.02	99.23	0.00	96.74	0.00	100.00	0.00	97.44	0.00	98.56	0.00	99.61	0.00	92.36	0.15	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3388890756
97.73	0.02	99.23	0.00	96.74	0.00	100.00	0.00	97.44	0.00	98.56	0.00	99.61	0.00	92.51	0.15	/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1800972529
97.75	0.02	99.23	0.00	96.76	0.03	100.00	0.00	97.44	0.00	98.56	0.00	99.61	0.00	92.62	0.10	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1223403832
97.76	0.02	99.27	0.04	96.76	0.00	100.00	0.00	97.44	0.00	98.63	0.07	99.61	0.00	92.62	0.00	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.186787249
97.78	0.01	99.27	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.63	0.00	99.61	0.00	92.72	0.10	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1169511501
97.79	0.01	99.27	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.63	0.00	99.61	0.00	92.82	0.10	/workspace/coverage/default/26.sysrst_ctrl_stress_all.3238693049
97.81	0.01	99.27	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.63	0.00	99.61	0.00	92.92	0.10	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3062123340
97.82	0.01	99.27	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.63	0.00	99.61	0.00	93.03	0.10	/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1167166986
97.83	0.01	99.29	0.02	96.76	0.00	100.00	0.00	97.44	0.00	98.67	0.04	99.61	0.00	93.03	0.00	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.840827969
97.84	0.01	99.31	0.02	96.76	0.00	100.00	0.00	97.44	0.00	98.71	0.04	99.61	0.00	93.03	0.00	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3960169689
97.84	0.01	99.33	0.02	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.04	99.61	0.00	93.03	0.00	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1807949255
97.85	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.08	0.05	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.4126292606
97.86	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.13	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3848788944
97.87	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.18	0.05	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.4262239868
97.87	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.23	0.05	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.2102976011
97.88	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.28	0.05	/workspace/coverage/default/17.sysrst_ctrl_combo_detect.2315591725
97.89	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.33	0.05	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.584594091
97.90	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.38	0.05	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.589657312
97.90	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.44	0.05	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.2788221974
97.91	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.49	0.05	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.464576053
97.92	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.54	0.05	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1733127040
97.93	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.59	0.05	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2379106538
97.93	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.64	0.05	/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4071814000
97.94	0.01	99.33	0.00	96.76	0.00	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.69	0.05	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2398662903
97.94	0.01	99.33	0.00	96.79	0.03	100.00	0.00	97.44	0.00	98.74	0.00	99.61	0.00	93.69	0.00	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1255584654

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3380295605
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3103670255
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3722089949
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3944368412
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.268193336
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2620508193
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3225375639
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2420701214
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2902912050
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1074983042
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.298525024
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3237356717
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2140814023
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4026611120
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1382290554
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.455315456
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.625384372
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1354159347
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.432631532
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.550626457
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.86312792
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3039705472
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2504074377
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2679431287
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.307942758
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3896780408
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.688094186
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3174558337
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1917594908
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.955917414
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4226681269
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1462045191
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.4013834976
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3207146789
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1952852912
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3306172777
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1195147539
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3308976932
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1190409975
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3465243637
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2950028129
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.922715697
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.225232490
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2199224532
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2395771474
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2362261765
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3872035221
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.416963514
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3153944695
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.261277686
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2979396458
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4014062445
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3628699066
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2550456593
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2085844172
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/workspace/coverage/default/4.sysrst_ctrl_edge_detect.531116250
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.666291502
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.755697591
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3226643313
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2134791296
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.855901920
/workspace/coverage/default/4.sysrst_ctrl_smoke.140080192
/workspace/coverage/default/4.sysrst_ctrl_stress_all.752023742
/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1044726239
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4052226354
/workspace/coverage/default/40.sysrst_ctrl_alert_test.1048537475
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3100814596
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.364301100
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2159668941
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2615853918
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3247606120
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2994412010
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3997084980
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.154461095
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1419161494
/workspace/coverage/default/40.sysrst_ctrl_smoke.2777595107
/workspace/coverage/default/40.sysrst_ctrl_stress_all.209705315
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3605929170
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2873446563
/workspace/coverage/default/41.sysrst_ctrl_alert_test.4248722542
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1438748688
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2292367384
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4207614360
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.3369262413
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1405426431
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3250904003
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1795472152
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3391744938
/workspace/coverage/default/41.sysrst_ctrl_smoke.508145614
/workspace/coverage/default/41.sysrst_ctrl_stress_all.109569376
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.294439988
/workspace/coverage/default/42.sysrst_ctrl_alert_test.1169205525
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2102282196
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2646551930
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3887726626
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.668797497
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3184124904
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2098192117
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4263662333
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.924579118
/workspace/coverage/default/42.sysrst_ctrl_smoke.4251655293
/workspace/coverage/default/42.sysrst_ctrl_stress_all.250577417
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.605963547
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1819560657
/workspace/coverage/default/43.sysrst_ctrl_alert_test.213626117
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3209116611
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3750734877
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1373921454
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4199645369
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.185579095
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2334740475
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3491633147
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2782058722
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2092050719
/workspace/coverage/default/43.sysrst_ctrl_smoke.453940363
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1995617516
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1263314690
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3235052190
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3026713538
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2580968294
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.701817009
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.858657720
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2818256180
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1924301149
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.361907889
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3467644174
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2354260538
/workspace/coverage/default/44.sysrst_ctrl_smoke.2876610660
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2471390248
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4080936151
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3790394373
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3975344705
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2638634960
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2405004908
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.111983167
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1262630176
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4008015732
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2199954177
/workspace/coverage/default/45.sysrst_ctrl_smoke.1935938591
/workspace/coverage/default/45.sysrst_ctrl_stress_all.258793267
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4192672650
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2145407573
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2616800172
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1725382713
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.231216969
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3141565391
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2112684803
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3542976665
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2379410487
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4109888243
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3818726376
/workspace/coverage/default/46.sysrst_ctrl_smoke.3793626142
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3365652709
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3666131212
/workspace/coverage/default/47.sysrst_ctrl_alert_test.575159520
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3489468657
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3914977282
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1839943794
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3316712649
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2651556071
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.4235902997
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2312076925
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3455140168
/workspace/coverage/default/47.sysrst_ctrl_smoke.1545615711
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1371967652
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1683372340
/workspace/coverage/default/48.sysrst_ctrl_alert_test.1334091705
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.18697470
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.383606042
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3911626265
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2466416702
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.95180430
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1691565472
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2844736887
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1176494786
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1672495484
/workspace/coverage/default/48.sysrst_ctrl_smoke.1245292382
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2359676562
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1563271766
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2553757081
/workspace/coverage/default/49.sysrst_ctrl_alert_test.829720982
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2225354816
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3844442959
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3020222480
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.261426418
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3445556561
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1459593520
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3315412099
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.965254997
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.544771509
/workspace/coverage/default/49.sysrst_ctrl_smoke.2585437456
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3241815908
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1602360612
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.487755841
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1070715883
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1620030185
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2715202819
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.4237874919
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2423975038
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.4262163584
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1595486616
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3951015777
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3553909415
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2897031010
/workspace/coverage/default/5.sysrst_ctrl_smoke.2362348230
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3581740081
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2594483734
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2090632587
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.402985592
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.16087339
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.142605311
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2877798846
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2651904154
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.129855884
/workspace/coverage/default/6.sysrst_ctrl_alert_test.996418161
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.366899086
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1160573619
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2868704692
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.551928223
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2128261774
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3748854741
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1668420064
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3678973020
/workspace/coverage/default/6.sysrst_ctrl_smoke.3605764417
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1179410305
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2258206876
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.359293426
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3680643646
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1151842466
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.88757901
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4265930899
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.910051439
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3023005135
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.608056820
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3863994951
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.896552928
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3976853655
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.318670192
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3858459721
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1961317256
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3807123750
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.825348231
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.916760302
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3331049835
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1233089918
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.427185617
/workspace/coverage/default/7.sysrst_ctrl_smoke.2968880355
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3517738680
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1116054915
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.411519103
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2912319818
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1638535656
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1633176424
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.879020630
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3556624332
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1166254426
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3925202208
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3561002339
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2028319609
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.677767791
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.744127370
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.107811275
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1097183688
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1328763816
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1220352210
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2182521021
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3985709505
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.714840831
/workspace/coverage/default/8.sysrst_ctrl_smoke.3881858421
/workspace/coverage/default/8.sysrst_ctrl_stress_all.406496537
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.802064185
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2881582739
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.73844877
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3150883175
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.110627486
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2707581483
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.810365329
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3917551603
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.4063694490
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3598529998
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2625803905
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1823956481
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1004348450
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.595035059
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.4071410156
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2938123663
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.379958477
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1512631939
/workspace/coverage/default/9.sysrst_ctrl_smoke.2279508496
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1040619426
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.4191029125
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3631840700
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1439384887
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1785524177
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1406645078
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.475475099
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4152821258

Total test records in report: 915

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1556045337	Apr 23 02:23:06 PM PDT 24	Apr 23 02:23:07 PM PDT 24	6813887473 ps
T5	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1490114340	Apr 23 02:23:40 PM PDT 24	Apr 23 02:23:43 PM PDT 24	3429923758 ps
T6	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.53162595	Apr 23 02:22:54 PM PDT 24	Apr 23 02:23:50 PM PDT 24	22462592700 ps
T22	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.74879735	Apr 23 02:23:25 PM PDT 24	Apr 23 02:23:37 PM PDT 24	3516403583 ps
T23	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3056193935	Apr 23 02:24:06 PM PDT 24	Apr 23 02:24:09 PM PDT 24	2544906761 ps
T24	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.280044476	Apr 23 02:22:53 PM PDT 24	Apr 23 02:22:57 PM PDT 24	4575532568 ps
T25	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.910051439	Apr 23 02:24:28 PM PDT 24	Apr 23 02:24:57 PM PDT 24	21087802232 ps
T26	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3336398007	Apr 23 02:23:49 PM PDT 24	Apr 23 02:23:56 PM PDT 24	2129538394 ps
T27	/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3994408147	Apr 23 02:23:09 PM PDT 24	Apr 23 02:23:17 PM PDT 24	2610343317 ps
T28	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1334317172	Apr 23 02:22:44 PM PDT 24	Apr 23 02:22:47 PM PDT 24	3461899651 ps
T1	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.4262163584	Apr 23 02:22:30 PM PDT 24	Apr 23 02:22:41 PM PDT 24	4545083224 ps
T14	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.4262239868	Apr 23 02:22:21 PM PDT 24	Apr 23 02:22:25 PM PDT 24	2483236481 ps
T15	/workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1026989146	Apr 23 02:23:48 PM PDT 24	Apr 23 02:23:55 PM PDT 24	2615335952 ps
T2	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3368926906	Apr 23 02:23:52 PM PDT 24	Apr 23 02:25:18 PM PDT 24	117888265323 ps
T3	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.2563241447	Apr 23 02:22:28 PM PDT 24	Apr 23 02:22:32 PM PDT 24	3223924141 ps
T16	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2938123663	Apr 23 02:22:47 PM PDT 24	Apr 23 02:22:49 PM PDT 24	2539973246 ps
T17	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3243919363	Apr 23 02:23:52 PM PDT 24	Apr 23 02:23:54 PM PDT 24	2538397873 ps
T18	/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3391744938	Apr 23 02:23:56 PM PDT 24	Apr 23 02:23:59 PM PDT 24	2524786952 ps
T19	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.841127116	Apr 23 02:23:09 PM PDT 24	Apr 23 02:23:13 PM PDT 24	2464823933 ps
T20	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2625803905	Apr 23 02:22:45 PM PDT 24	Apr 23 02:26:57 PM PDT 24	196808759743 ps
T7	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.1292204478	Apr 23 02:23:14 PM PDT 24	Apr 23 02:23:20 PM PDT 24	4606802057 ps
T8	/workspace/coverage/default/21.sysrst_ctrl_stress_all.3073168810	Apr 23 02:23:10 PM PDT 24	Apr 23 02:29:33 PM PDT 24	556980858260 ps
T58	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2797372506	Apr 23 02:23:27 PM PDT 24	Apr 23 02:23:29 PM PDT 24	2177989221 ps
T103	/workspace/coverage/default/42.sysrst_ctrl_smoke.4251655293	Apr 23 02:23:59 PM PDT 24	Apr 23 02:24:06 PM PDT 24	2111025050 ps
T67	/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2379410487	Apr 23 02:24:17 PM PDT 24	Apr 23 02:24:21 PM PDT 24	2461246131 ps
T9	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1751766169	Apr 23 02:23:20 PM PDT 24	Apr 23 02:31:57 PM PDT 24	180439602711 ps
T72	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3406163432	Apr 23 02:22:40 PM PDT 24	Apr 23 02:22:42 PM PDT 24	2576685132 ps
T68	/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.4191029125	Apr 23 02:22:45 PM PDT 24	Apr 23 02:23:59 PM PDT 24	29141381660 ps
T10	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.487323114	Apr 23 02:23:36 PM PDT 24	Apr 23 02:24:48 PM PDT 24	106914887771 ps
T59	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1206422357	Apr 23 02:22:19 PM PDT 24	Apr 23 02:22:22 PM PDT 24	2682576260 ps
T73	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.63828843	Apr 23 02:23:50 PM PDT 24	Apr 23 02:23:53 PM PDT 24	2730388881 ps
T50	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3561002339	Apr 23 02:24:31 PM PDT 24	Apr 23 02:25:40 PM PDT 24	27081104069 ps
T134	/workspace/coverage/default/0.sysrst_ctrl_smoke.397422477	Apr 23 02:22:39 PM PDT 24	Apr 23 02:22:42 PM PDT 24	2125498866 ps
T74	/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2088154784	Apr 23 02:23:03 PM PDT 24	Apr 23 02:23:10 PM PDT 24	2510068548 ps
T60	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2984692380	Apr 23 02:23:21 PM PDT 24	Apr 23 02:23:29 PM PDT 24	5043091211 ps
T11	/workspace/coverage/default/38.sysrst_ctrl_edge_detect.823845003	Apr 23 02:23:55 PM PDT 24	Apr 23 02:24:05 PM PDT 24	3258548617 ps
T135	/workspace/coverage/default/33.sysrst_ctrl_alert_test.2655561460	Apr 23 02:25:03 PM PDT 24	Apr 23 02:25:06 PM PDT 24	2037837452 ps
T51	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.626980467	Apr 23 02:22:42 PM PDT 24	Apr 23 02:22:47 PM PDT 24	2169313232 ps
T236	/workspace/coverage/default/29.sysrst_ctrl_smoke.4256883637	Apr 23 02:23:42 PM PDT 24	Apr 23 02:23:49 PM PDT 24	2112229362 ps
T237	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3467644174	Apr 23 02:24:06 PM PDT 24	Apr 23 02:24:09 PM PDT 24	2066142404 ps
T238	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3678597992	Apr 23 02:23:28 PM PDT 24	Apr 23 02:23:31 PM PDT 24	2036957596 ps
T12	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.2468925274	Apr 23 02:23:14 PM PDT 24	Apr 23 02:23:18 PM PDT 24	3943864326 ps
T189	/workspace/coverage/default/15.sysrst_ctrl_smoke.3025605445	Apr 23 02:23:00 PM PDT 24	Apr 23 02:23:02 PM PDT 24	2137295378 ps
T13	/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2507392371	Apr 23 02:22:33 PM PDT 24	Apr 23 02:23:22 PM PDT 24	18899267626 ps
T48	/workspace/coverage/default/22.sysrst_ctrl_stress_all.595776278	Apr 23 02:23:15 PM PDT 24	Apr 23 02:23:32 PM PDT 24	71903942445 ps
T190	/workspace/coverage/default/24.sysrst_ctrl_smoke.4265476126	Apr 23 02:23:24 PM PDT 24	Apr 23 02:23:26 PM PDT 24	2132127015 ps
T21	/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2553757081	Apr 23 02:24:17 PM PDT 24	Apr 23 02:24:27 PM PDT 24	4030355287 ps
T52	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1169511501	Apr 23 02:23:27 PM PDT 24	Apr 23 02:23:38 PM PDT 24	3734357855 ps
T40	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3858459721	Apr 23 02:22:43 PM PDT 24	Apr 23 02:23:48 PM PDT 24	71258017724 ps
T43	/workspace/coverage/default/27.sysrst_ctrl_stress_all.3441829501	Apr 23 02:23:24 PM PDT 24	Apr 23 02:30:06 PM PDT 24	161046713498 ps
T80	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2181318191	Apr 23 02:22:44 PM PDT 24	Apr 23 02:22:52 PM PDT 24	2610983466 ps
T81	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1668420064	Apr 23 02:22:33 PM PDT 24	Apr 23 02:22:36 PM PDT 24	2226101789 ps
T33	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2127001405	Apr 23 02:24:17 PM PDT 24	Apr 23 02:24:43 PM PDT 24	151709144445 ps
T82	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1849078520	Apr 23 02:23:37 PM PDT 24	Apr 23 02:23:39 PM PDT 24	2665500136 ps
T38	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.744127370	Apr 23 02:22:42 PM PDT 24	Apr 23 02:23:58 PM PDT 24	110906571215 ps
T83	/workspace/coverage/default/32.sysrst_ctrl_alert_test.2926303742	Apr 23 02:23:34 PM PDT 24	Apr 23 02:23:41 PM PDT 24	2012910272 ps
T41	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3020222480	Apr 23 02:24:19 PM PDT 24	Apr 23 02:27:03 PM PDT 24	66303050796 ps
T69	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.4235902997	Apr 23 02:24:19 PM PDT 24	Apr 23 02:24:25 PM PDT 24	2466959547 ps
T204	/workspace/coverage/default/5.sysrst_ctrl_stress_all.3581740081	Apr 23 02:22:28 PM PDT 24	Apr 23 02:22:32 PM PDT 24	7278501761 ps
T46	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.1774352842	Apr 23 02:22:40 PM PDT 24	Apr 23 02:22:44 PM PDT 24	4820467609 ps
T395	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1176494786	Apr 23 02:24:17 PM PDT 24	Apr 23 02:24:20 PM PDT 24	2042696764 ps
T394	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2354260538	Apr 23 02:24:07 PM PDT 24	Apr 23 02:24:10 PM PDT 24	2525989918 ps
T396	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.759712535	Apr 23 02:23:02 PM PDT 24	Apr 23 02:23:05 PM PDT 24	2626809300 ps
T397	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2128261774	Apr 23 02:22:32 PM PDT 24	Apr 23 02:22:36 PM PDT 24	2615879859 ps
T70	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2969156814	Apr 23 02:23:17 PM PDT 24	Apr 23 02:23:25 PM PDT 24	2457981449 ps
T398	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2502487619	Apr 23 02:22:44 PM PDT 24	Apr 23 02:22:49 PM PDT 24	2620328749 ps
T61	/workspace/coverage/default/35.sysrst_ctrl_stress_all.2540938370	Apr 23 02:23:47 PM PDT 24	Apr 23 02:23:59 PM PDT 24	19364915907 ps
T42	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.2543903072	Apr 23 02:23:27 PM PDT 24	Apr 23 02:23:29 PM PDT 24	3229768827 ps
T298	/workspace/coverage/default/35.sysrst_ctrl_alert_test.2401221129	Apr 23 02:23:50 PM PDT 24	Apr 23 02:23:51 PM PDT 24	2126453504 ps
T399	/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3184124904	Apr 23 02:23:58 PM PDT 24	Apr 23 02:24:03 PM PDT 24	2614734899 ps
T45	/workspace/coverage/default/40.sysrst_ctrl_stress_all.209705315	Apr 23 02:23:56 PM PDT 24	Apr 23 02:24:00 PM PDT 24	14983461591 ps
T47	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3249620970	Apr 23 02:24:33 PM PDT 24	Apr 23 02:25:20 PM PDT 24	65569684212 ps
T222	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.2453631159	Apr 23 02:23:37 PM PDT 24	Apr 23 02:23:41 PM PDT 24	2650326016 ps
T400	/workspace/coverage/default/43.sysrst_ctrl_smoke.453940363	Apr 23 02:24:03 PM PDT 24	Apr 23 02:24:09 PM PDT 24	2112057929 ps
T316	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2609354830	Apr 23 02:22:47 PM PDT 24	Apr 23 02:22:51 PM PDT 24	2902353355 ps
T401	/workspace/coverage/default/18.sysrst_ctrl_smoke.3213570168	Apr 23 02:22:56 PM PDT 24	Apr 23 02:23:03 PM PDT 24	2112864287 ps
T402	/workspace/coverage/default/13.sysrst_ctrl_alert_test.1991704058	Apr 23 02:22:44 PM PDT 24	Apr 23 02:22:51 PM PDT 24	2008410888 ps
T403	/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1405426431	Apr 23 02:23:54 PM PDT 24	Apr 23 02:23:57 PM PDT 24	2625110710 ps
T404	/workspace/coverage/default/19.sysrst_ctrl_smoke.2584421924	Apr 23 02:22:57 PM PDT 24	Apr 23 02:23:00 PM PDT 24	2132166987 ps
T405	/workspace/coverage/default/29.sysrst_ctrl_stress_all.2201133386	Apr 23 02:23:27 PM PDT 24	Apr 23 02:23:52 PM PDT 24	9085501796 ps
T34	/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2879389002	Apr 23 02:23:02 PM PDT 24	Apr 23 02:23:07 PM PDT 24	4194615044 ps
T101	/workspace/coverage/default/17.sysrst_ctrl_stress_all.149150694	Apr 23 02:23:13 PM PDT 24	Apr 23 02:23:24 PM PDT 24	13659088219 ps
T57	/workspace/coverage/default/16.sysrst_ctrl_stress_all.3134357083	Apr 23 02:22:56 PM PDT 24	Apr 23 02:28:56 PM PDT 24	141693606407 ps
T158	/workspace/coverage/default/10.sysrst_ctrl_smoke.953856256	Apr 23 02:22:41 PM PDT 24	Apr 23 02:22:43 PM PDT 24	2149705094 ps
T159	/workspace/coverage/default/30.sysrst_ctrl_stress_all.1051190054	Apr 23 02:23:23 PM PDT 24	Apr 23 02:23:33 PM PDT 24	6545727356 ps
T53	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1673325364	Apr 23 02:22:43 PM PDT 24	Apr 23 02:22:52 PM PDT 24	3328518029 ps
T160	/workspace/coverage/default/9.sysrst_ctrl_stress_all.1040619426	Apr 23 02:22:30 PM PDT 24	Apr 23 02:27:59 PM PDT 24	470267173418 ps
T62	/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1772178524	Apr 23 02:23:02 PM PDT 24	Apr 23 02:23:04 PM PDT 24	7263777414 ps
T133	/workspace/coverage/default/4.sysrst_ctrl_combo_detect.2880318020	Apr 23 02:22:30 PM PDT 24	Apr 23 02:23:09 PM PDT 24	29834516281 ps
T71	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2087794000	Apr 23 02:23:16 PM PDT 24	Apr 23 02:23:23 PM PDT 24	2459015192 ps
T104	/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3914977282	Apr 23 02:24:19 PM PDT 24	Apr 23 02:26:27 PM PDT 24	135445941733 ps
T120	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1000822484	Apr 23 02:25:26 PM PDT 24	Apr 23 02:25:32 PM PDT 24	2512013152 ps
T121	/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.47579933	Apr 23 02:22:43 PM PDT 24	Apr 23 02:22:47 PM PDT 24	2203725984 ps
T54	/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.760891751	Apr 23 02:23:23 PM PDT 24	Apr 23 02:23:26 PM PDT 24	3778402722 ps
T122	/workspace/coverage/default/47.sysrst_ctrl_smoke.1545615711	Apr 23 02:24:19 PM PDT 24	Apr 23 02:24:27 PM PDT 24	2113439823 ps
T44	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3316712649	Apr 23 02:24:15 PM PDT 24	Apr 23 02:24:22 PM PDT 24	4387798626 ps
T123	/workspace/coverage/default/36.sysrst_ctrl_alert_test.209117191	Apr 23 02:23:51 PM PDT 24	Apr 23 02:23:54 PM PDT 24	2024349269 ps
T124	/workspace/coverage/default/49.sysrst_ctrl_smoke.2585437456	Apr 23 02:24:20 PM PDT 24	Apr 23 02:24:27 PM PDT 24	2111695739 ps
T125	/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2182521021	Apr 23 02:22:39 PM PDT 24	Apr 23 02:22:42 PM PDT 24	2472104197 ps
T39	/workspace/coverage/default/33.sysrst_ctrl_stress_all.3191893594	Apr 23 02:24:55 PM PDT 24	Apr 23 02:33:19 PM PDT 24	195351709693 ps
T173	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.2540458348	Apr 23 02:23:28 PM PDT 24	Apr 23 02:23:33 PM PDT 24	2794837692 ps
T75	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.589657312	Apr 23 02:23:14 PM PDT 24	Apr 23 02:24:50 PM PDT 24	40866042336 ps
T76	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3023005135	Apr 23 02:24:29 PM PDT 24	Apr 23 02:24:49 PM PDT 24	40561481465 ps
T102	/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1625087937	Apr 23 02:23:50 PM PDT 24	Apr 23 02:23:53 PM PDT 24	3592365163 ps
T276	/workspace/coverage/default/31.sysrst_ctrl_combo_detect.1953877809	Apr 23 02:23:30 PM PDT 24	Apr 23 02:24:13 PM PDT 24	75888293117 ps
T406	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1898379205	Apr 23 02:23:35 PM PDT 24	Apr 23 02:23:38 PM PDT 24	2090426237 ps
T63	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.972366508	Apr 23 02:22:56 PM PDT 24	Apr 23 02:24:17 PM PDT 24	124387095308 ps
T325	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3181502287	Apr 23 02:23:36 PM PDT 24	Apr 23 02:23:42 PM PDT 24	2616835764 ps
T99	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.840827969	Apr 23 02:22:19 PM PDT 24	Apr 23 02:22:29 PM PDT 24	4456015540 ps
T312	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.1582722925	Apr 23 02:23:00 PM PDT 24	Apr 23 02:24:10 PM PDT 24	107976244401 ps
T105	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1978135104	Apr 23 02:22:39 PM PDT 24	Apr 23 02:23:55 PM PDT 24	95378923658 ps
T100	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3806914783	Apr 23 02:22:44 PM PDT 24	Apr 23 02:23:18 PM PDT 24	12853568998 ps
T49	/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.359293426	Apr 23 02:24:23 PM PDT 24	Apr 23 02:24:45 PM PDT 24	48129355591 ps
T326	/workspace/coverage/default/41.sysrst_ctrl_stress_all.109569376	Apr 23 02:24:08 PM PDT 24	Apr 23 02:24:14 PM PDT 24	7975670775 ps
T327	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.378783242	Apr 23 02:23:27 PM PDT 24	Apr 23 02:23:30 PM PDT 24	3471682307 ps
T64	/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4071814000	Apr 23 02:22:28 PM PDT 24	Apr 23 02:23:23 PM PDT 24	605216684762 ps
T407	/workspace/coverage/default/19.sysrst_ctrl_stress_all.120438924	Apr 23 02:23:04 PM PDT 24	Apr 23 02:23:15 PM PDT 24	10358469655 ps
T174	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.531116250	Apr 23 02:22:36 PM PDT 24	Apr 23 02:22:39 PM PDT 24	3459498729 ps
T77	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.879020630	Apr 23 02:24:27 PM PDT 24	Apr 23 02:24:49 PM PDT 24	38834412859 ps
T408	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2167320123	Apr 23 02:23:14 PM PDT 24	Apr 23 02:23:19 PM PDT 24	2522315634 ps
T318	/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3519040795	Apr 23 02:22:47 PM PDT 24	Apr 23 02:22:55 PM PDT 24	2513566097 ps
T409	/workspace/coverage/default/6.sysrst_ctrl_smoke.3605764417	Apr 23 02:22:43 PM PDT 24	Apr 23 02:22:50 PM PDT 24	2110241561 ps
T65	/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4080936151	Apr 23 02:24:08 PM PDT 24	Apr 23 02:24:10 PM PDT 24	2746777070 ps
T66	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.584594091	Apr 23 02:23:07 PM PDT 24	Apr 23 02:26:26 PM PDT 24	1839809804075 ps
T141	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.546173827	Apr 23 02:23:19 PM PDT 24	Apr 23 02:23:50 PM PDT 24	17377160499 ps
T317	/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3450564055	Apr 23 02:23:13 PM PDT 24	Apr 23 02:23:17 PM PDT 24	2452646822 ps
T410	/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4263662333	Apr 23 02:23:57 PM PDT 24	Apr 23 02:24:01 PM PDT 24	2193012397 ps
T411	/workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.746497003	Apr 23 02:22:32 PM PDT 24	Apr 23 02:22:45 PM PDT 24	4255687803 ps
T262	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1298760261	Apr 23 02:24:29 PM PDT 24	Apr 23 02:26:55 PM PDT 24	102565648274 ps
T412	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2811092163	Apr 23 02:22:44 PM PDT 24	Apr 23 02:22:47 PM PDT 24	2545132819 ps
T413	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2248235339	Apr 23 02:23:04 PM PDT 24	Apr 23 02:23:08 PM PDT 24	3024546296 ps
T414	/workspace/coverage/default/5.sysrst_ctrl_smoke.2362348230	Apr 23 02:22:40 PM PDT 24	Apr 23 02:22:47 PM PDT 24	2112035695 ps
T142	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2580968294	Apr 23 02:24:05 PM PDT 24	Apr 23 02:24:15 PM PDT 24	3805467336 ps
T415	/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.4183945400	Apr 23 02:23:23 PM PDT 24	Apr 23 02:23:25 PM PDT 24	2595501431 ps
T416	/workspace/coverage/default/4.sysrst_ctrl_alert_test.3108276507	Apr 23 02:22:41 PM PDT 24	Apr 23 02:22:44 PM PDT 24	2033903296 ps
T349	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.3611312486	Apr 23 02:23:58 PM PDT 24	Apr 23 02:24:23 PM PDT 24	49317292374 ps
T319	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2804677937	Apr 23 02:23:36 PM PDT 24	Apr 23 02:23:40 PM PDT 24	2526441877 ps
T417	/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3474997683	Apr 23 02:22:16 PM PDT 24	Apr 23 02:22:23 PM PDT 24	4088828413 ps
T263	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1116054915	Apr 23 02:24:27 PM PDT 24	Apr 23 02:26:08 PM PDT 24	151785314888 ps
T418	/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.4253338599	Apr 23 02:23:02 PM PDT 24	Apr 23 02:23:05 PM PDT 24	3929084032 ps
T419	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.2026379829	Apr 23 02:23:50 PM PDT 24	Apr 23 02:25:46 PM PDT 24	187145027267 ps
T310	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.318670192	Apr 23 02:22:44 PM PDT 24	Apr 23 02:30:02 PM PDT 24	169046076158 ps
T235	/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2818256180	Apr 23 02:24:06 PM PDT 24	Apr 23 02:24:13 PM PDT 24	2452261478 ps
T311	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.850435955	Apr 23 02:22:41 PM PDT 24	Apr 23 02:35:29 PM PDT 24	305874755614 ps
T55	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.455144568	Apr 23 02:22:38 PM PDT 24	Apr 23 02:23:06 PM PDT 24	41522774779 ps
T420	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1262630176	Apr 23 02:24:09 PM PDT 24	Apr 23 02:24:17 PM PDT 24	2611796684 ps
T421	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2197655211	Apr 23 02:23:45 PM PDT 24	Apr 23 02:23:48 PM PDT 24	3450105818 ps
T422	/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3582776487	Apr 23 02:23:16 PM PDT 24	Apr 23 02:23:20 PM PDT 24	2512080904 ps
T423	/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3568718227	Apr 23 02:22:29 PM PDT 24	Apr 23 02:22:36 PM PDT 24	2047852900 ps
T424	/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2134058446	Apr 23 02:23:50 PM PDT 24	Apr 23 02:23:56 PM PDT 24	4498186522 ps
T425	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.577212556	Apr 23 02:22:39 PM PDT 24	Apr 23 02:22:44 PM PDT 24	10394673645 ps
T106	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1348667322	Apr 23 02:23:12 PM PDT 24	Apr 23 02:23:31 PM PDT 24	26355403395 ps
T107	/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.110627486	Apr 23 02:24:27 PM PDT 24	Apr 23 02:24:53 PM PDT 24	53913373273 ps
T426	/workspace/coverage/default/32.sysrst_ctrl_smoke.3175686996	Apr 23 02:23:32 PM PDT 24	Apr 23 02:23:38 PM PDT 24	2110244971 ps
T277	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1439384887	Apr 23 02:24:29 PM PDT 24	Apr 23 02:25:04 PM PDT 24	45688650285 ps
T266	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.119416293	Apr 23 02:22:49 PM PDT 24	Apr 23 02:23:45 PM PDT 24	21331285897 ps
T313	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.2102976011	Apr 23 02:22:47 PM PDT 24	Apr 23 02:24:27 PM PDT 24	157413063327 ps
T427	/workspace/coverage/default/28.sysrst_ctrl_smoke.3763013845	Apr 23 02:23:21 PM PDT 24	Apr 23 02:23:28 PM PDT 24	2113110693 ps
T428	/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4207614360	Apr 23 02:24:02 PM PDT 24	Apr 23 02:24:14 PM PDT 24	4092143081 ps
T429	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.427474827	Apr 23 02:22:19 PM PDT 24	Apr 23 02:22:24 PM PDT 24	2549949003 ps
T267	/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3750734877	Apr 23 02:24:07 PM PDT 24	Apr 23 02:25:37 PM PDT 24	165383613005 ps
T202	/workspace/coverage/default/31.sysrst_ctrl_stress_all.3917444644	Apr 23 02:23:29 PM PDT 24	Apr 23 02:23:59 PM PDT 24	15778347562 ps
T278	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2367027649	Apr 23 02:23:22 PM PDT 24	Apr 23 02:26:43 PM PDT 24	72416989211 ps
T430	/workspace/coverage/default/45.sysrst_ctrl_smoke.1935938591	Apr 23 02:24:09 PM PDT 24	Apr 23 02:24:16 PM PDT 24	2111271146 ps
T78	/workspace/coverage/default/1.sysrst_ctrl_stress_all.3832547183	Apr 23 02:22:45 PM PDT 24	Apr 23 02:22:55 PM PDT 24	17744807197 ps
T431	/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2326593879	Apr 23 02:23:24 PM PDT 24	Apr 23 02:23:26 PM PDT 24	2710604234 ps
T432	/workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3926140715	Apr 23 02:23:16 PM PDT 24	Apr 23 02:23:19 PM PDT 24	3584453901 ps
T433	/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.294439988	Apr 23 02:23:55 PM PDT 24	Apr 23 02:23:58 PM PDT 24	3124557233 ps
T434	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1419161494	Apr 23 02:23:52 PM PDT 24	Apr 23 02:23:55 PM PDT 24	2526748857 ps
T435	/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3753666621	Apr 23 02:23:55 PM PDT 24	Apr 23 02:23:57 PM PDT 24	2657450868 ps
T436	/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1595486616	Apr 23 02:22:28 PM PDT 24	Apr 23 02:22:32 PM PDT 24	2632561366 ps
T437	/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3666131212	Apr 23 02:24:16 PM PDT 24	Apr 23 02:24:24 PM PDT 24	3827896131 ps
T438	/workspace/coverage/default/22.sysrst_ctrl_smoke.3344000998	Apr 23 02:23:10 PM PDT 24	Apr 23 02:23:12 PM PDT 24	2153313333 ps
T79	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2302655039	Apr 23 02:23:06 PM PDT 24	Apr 23 02:23:09 PM PDT 24	10566696561 ps
T439	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.456370538	Apr 23 02:23:44 PM PDT 24	Apr 23 02:23:47 PM PDT 24	2498114239 ps
T91	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3299741337	Apr 23 02:22:47 PM PDT 24	Apr 23 02:22:52 PM PDT 24	3056375865 ps
T136	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.682072471	Apr 23 02:23:35 PM PDT 24	Apr 23 02:23:44 PM PDT 24	11411956617 ps
T224	/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1924301149	Apr 23 02:24:08 PM PDT 24	Apr 23 02:24:11 PM PDT 24	2624136024 ps
T225	/workspace/coverage/default/6.sysrst_ctrl_alert_test.996418161	Apr 23 02:22:30 PM PDT 24	Apr 23 02:22:34 PM PDT 24	2028272768 ps
T108	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1992525286	Apr 23 02:23:48 PM PDT 24	Apr 23 02:25:03 PM PDT 24	27833385251 ps
T226	/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.523208340	Apr 23 02:23:51 PM PDT 24	Apr 23 02:23:59 PM PDT 24	2476275933 ps
T86	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.1127904438	Apr 23 02:22:58 PM PDT 24	Apr 23 02:23:05 PM PDT 24	2882852450 ps
T192	/workspace/coverage/default/20.sysrst_ctrl_smoke.3704253419	Apr 23 02:23:06 PM PDT 24	Apr 23 02:23:08 PM PDT 24	2125691116 ps
T193	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.916760302	Apr 23 02:22:45 PM PDT 24	Apr 23 02:22:49 PM PDT 24	2634021234 ps
T194	/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1277292900	Apr 23 02:22:48 PM PDT 24	Apr 23 02:22:56 PM PDT 24	2610866753 ps
T109	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3863994951	Apr 23 02:24:26 PM PDT 24	Apr 23 02:28:21 PM PDT 24	94001467451 ps
T195	/workspace/coverage/default/48.sysrst_ctrl_alert_test.1334091705	Apr 23 02:24:19 PM PDT 24	Apr 23 02:24:22 PM PDT 24	2033768366 ps
T196	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.1922219940	Apr 23 02:23:15 PM PDT 24	Apr 23 02:23:26 PM PDT 24	3633199139 ps
T143	/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1620030185	Apr 23 02:22:28 PM PDT 24	Apr 23 02:22:34 PM PDT 24	3211773426 ps
T197	/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3491633147	Apr 23 02:24:02 PM PDT 24	Apr 23 02:24:05 PM PDT 24	2510252596 ps
T198	/workspace/coverage/default/2.sysrst_ctrl_sec_cm.118635205	Apr 23 02:22:39 PM PDT 24	Apr 23 02:23:09 PM PDT 24	42106793838 ps
T110	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.1974336238	Apr 23 02:23:49 PM PDT 24	Apr 23 02:31:08 PM PDT 24	179089468934 ps
T309	/workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3310387029	Apr 23 02:22:57 PM PDT 24	Apr 23 02:22:59 PM PDT 24	2670857962 ps
T199	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.623555542	Apr 23 02:23:08 PM PDT 24	Apr 23 02:25:30 PM PDT 24	264691211634 ps
T241	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2972858191	Apr 23 02:22:56 PM PDT 24	Apr 23 02:23:00 PM PDT 24	3618158251 ps
T88	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3770048433	Apr 23 02:22:29 PM PDT 24	Apr 23 02:22:37 PM PDT 24	7831192575 ps
T162	/workspace/coverage/default/11.sysrst_ctrl_smoke.539366622	Apr 23 02:22:34 PM PDT 24	Apr 23 02:22:40 PM PDT 24	2113351184 ps
T111	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.147389131	Apr 23 02:23:29 PM PDT 24	Apr 23 02:24:05 PM PDT 24	25841903936 ps
T137	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3507037002	Apr 23 02:23:05 PM PDT 24	Apr 23 02:23:13 PM PDT 24	5930574968 ps
T163	/workspace/coverage/default/10.sysrst_ctrl_stress_all.3714121374	Apr 23 02:22:43 PM PDT 24	Apr 23 02:22:54 PM PDT 24	14257861410 ps
T164	/workspace/coverage/default/46.sysrst_ctrl_stress_all.3365652709	Apr 23 02:24:14 PM PDT 24	Apr 23 02:24:18 PM PDT 24	13464178090 ps
T165	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1839943794	Apr 23 02:24:17 PM PDT 24	Apr 23 02:24:20 PM PDT 24	3330297221 ps
T166	/workspace/coverage/default/33.sysrst_ctrl_smoke.806572334	Apr 23 02:23:35 PM PDT 24	Apr 23 02:23:39 PM PDT 24	2121871608 ps
T167	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2375394486	Apr 23 02:23:18 PM PDT 24	Apr 23 02:23:20 PM PDT 24	3466335532 ps
T138	/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4192672650	Apr 23 02:24:12 PM PDT 24	Apr 23 02:24:32 PM PDT 24	1057267801390 ps
T440	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1857798830	Apr 23 02:23:03 PM PDT 24	Apr 23 02:23:08 PM PDT 24	2861841137 ps
T320	/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3642192667	Apr 23 02:22:19 PM PDT 24	Apr 23 02:22:22 PM PDT 24	2536923191 ps
T441	/workspace/coverage/default/35.sysrst_ctrl_smoke.1355124806	Apr 23 02:23:36 PM PDT 24	Apr 23 02:23:39 PM PDT 24	2132325324 ps
T442	/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3825369520	Apr 23 02:23:01 PM PDT 24	Apr 23 02:23:04 PM PDT 24	2631390671 ps
T443	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.4252192270	Apr 23 02:23:33 PM PDT 24	Apr 23 02:23:36 PM PDT 24	2160125749 ps
T280	/workspace/coverage/default/18.sysrst_ctrl_stress_all.4201705620	Apr 23 02:23:09 PM PDT 24	Apr 23 02:28:37 PM PDT 24	167626834267 ps
T444	/workspace/coverage/default/3.sysrst_ctrl_smoke.4291793603	Apr 23 02:22:39 PM PDT 24	Apr 23 02:22:46 PM PDT 24	2110997437 ps
T445	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.759179586	Apr 23 02:23:12 PM PDT 24	Apr 23 02:23:15 PM PDT 24	2857523760 ps
T446	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.68152299	Apr 23 02:22:30 PM PDT 24	Apr 23 02:22:34 PM PDT 24	2436595116 ps
T218	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1563271766	Apr 23 02:24:20 PM PDT 24	Apr 23 02:24:41 PM PDT 24	29596585770 ps
T208	/workspace/coverage/default/34.sysrst_ctrl_stress_all.2051284020	Apr 23 02:23:41 PM PDT 24	Apr 23 02:23:50 PM PDT 24	7336176880 ps
T175	/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2112684803	Apr 23 02:24:14 PM PDT 24	Apr 23 02:24:18 PM PDT 24	5787847895 ps
T447	/workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2826197569	Apr 23 02:23:02 PM PDT 24	Apr 23 02:23:05 PM PDT 24	2523287194 ps
T448	/workspace/coverage/default/47.sysrst_ctrl_alert_test.575159520	Apr 23 02:24:16 PM PDT 24	Apr 23 02:24:20 PM PDT 24	2080859152 ps
T373	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1373921454	Apr 23 02:24:02 PM PDT 24	Apr 23 02:25:21 PM PDT 24	29865560578 ps
T449	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.154970370	Apr 23 02:23:50 PM PDT 24	Apr 23 02:24:01 PM PDT 24	3757737293 ps
T450	/workspace/coverage/default/36.sysrst_ctrl_smoke.3343317987	Apr 23 02:23:53 PM PDT 24	Apr 23 02:23:57 PM PDT 24	2120199041 ps
T451	/workspace/coverage/default/30.sysrst_ctrl_smoke.2532114961	Apr 23 02:23:36 PM PDT 24	Apr 23 02:23:43 PM PDT 24	2110718485 ps
T452	/workspace/coverage/default/25.sysrst_ctrl_smoke.2838438074	Apr 23 02:23:24 PM PDT 24	Apr 23 02:23:27 PM PDT 24	2133752422 ps
T453	/workspace/coverage/default/23.sysrst_ctrl_alert_test.784582504	Apr 23 02:23:20 PM PDT 24	Apr 23 02:23:22 PM PDT 24	2029359707 ps
T454	/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3348047504	Apr 23 02:23:23 PM PDT 24	Apr 23 02:23:27 PM PDT 24	4706435932 ps
T455	/workspace/coverage/default/2.sysrst_ctrl_stress_all.3740067767	Apr 23 02:22:24 PM PDT 24	Apr 23 02:22:56 PM PDT 24	12138568675 ps
T456	/workspace/coverage/default/1.sysrst_ctrl_smoke.2478889056	Apr 23 02:22:46 PM PDT 24	Apr 23 02:22:50 PM PDT 24	2119984964 ps
T251	/workspace/coverage/default/43.sysrst_ctrl_edge_detect.185579095	Apr 23 02:24:02 PM PDT 24	Apr 23 02:24:08 PM PDT 24	3341680547 ps
T219	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.3882340688	Apr 23 02:23:02 PM PDT 24	Apr 23 02:23:10 PM PDT 24	3402501305 ps
T457	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3065909534	Apr 23 02:23:53 PM PDT 24	Apr 23 02:23:57 PM PDT 24	2058950293 ps
T458	/workspace/coverage/default/17.sysrst_ctrl_alert_test.211799590	Apr 23 02:22:56 PM PDT 24	Apr 23 02:23:00 PM PDT 24	2022102178 ps
T85	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.546585548	Apr 23 02:23:38 PM PDT 24	Apr 23 02:25:05 PM PDT 24	31329272985 ps
T176	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.2855646512	Apr 23 02:23:39 PM PDT 24	Apr 23 02:23:42 PM PDT 24	3562302313 ps
T459	/workspace/coverage/default/27.sysrst_ctrl_smoke.3681644995	Apr 23 02:23:39 PM PDT 24	Apr 23 02:23:46 PM PDT 24	2110817558 ps
T460	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3850807217	Apr 23 02:23:26 PM PDT 24	Apr 23 02:23:29 PM PDT 24	2630796690 ps
T461	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2994412010	Apr 23 02:23:55 PM PDT 24	Apr 23 02:24:03 PM PDT 24	2615214181 ps
T172	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3935340879	Apr 23 02:23:37 PM PDT 24	Apr 23 02:24:17 PM PDT 24	16363611001 ps
T261	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.701817009	Apr 23 02:24:05 PM PDT 24	Apr 23 02:25:55 PM PDT 24	72932973772 ps
T462	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.379958477	Apr 23 02:22:35 PM PDT 24	Apr 23 02:22:37 PM PDT 24	2079768136 ps
T463	/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2382626913	Apr 23 02:22:39 PM PDT 24	Apr 23 02:22:47 PM PDT 24	2513473863 ps
T464	/workspace/coverage/default/8.sysrst_ctrl_alert_test.2028319609	Apr 23 02:22:32 PM PDT 24	Apr 23 02:22:39 PM PDT 24	2015819694 ps
T465	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3742230802	Apr 23 02:23:08 PM PDT 24	Apr 23 02:23:11 PM PDT 24	2541151000 ps
T466	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.915627657	Apr 23 02:25:04 PM PDT 24	Apr 23 02:25:08 PM PDT 24	7786133749 ps
T347	/workspace/coverage/default/26.sysrst_ctrl_stress_all.3238693049	Apr 23 02:23:20 PM PDT 24	Apr 23 02:29:16 PM PDT 24	1806827058369 ps
T94	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.936651797	Apr 23 02:23:32 PM PDT 24	Apr 23 02:23:34 PM PDT 24	15118269395 ps
T467	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3190814545	Apr 23 02:22:46 PM PDT 24	Apr 23 02:22:52 PM PDT 24	3725054877 ps
T468	/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3033978866	Apr 23 02:23:26 PM PDT 24	Apr 23 02:23:29 PM PDT 24	2624473974 ps
T139	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3235052190	Apr 23 02:24:05 PM PDT 24	Apr 23 02:24:13 PM PDT 24	8916485947 ps
T469	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2914221453	Apr 23 02:23:09 PM PDT 24	Apr 23 02:23:13 PM PDT 24	3862429050 ps