Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1228

1

T6

10

T23

8

T17

11

auto[1]

1123

1

T6

10

T23

12

T17

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

569

1

T6

7

T23

6

T17

5

from_0to1

573

1

T6

6

T23

5

T17

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T6

9

T23

9

T17

10

auto[1]

1172

1

T6

11

T23

11

T17

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T6

12

T23

13

T17

11

auto[1]

1164

1

T6

8

T23

7

T17

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T18

1

T72

1

T33

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T6

1

T23

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T6

2

T23

1

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

90

1

T6

1

T17

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

86

1

T6

1

T18

1

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T17

1

T33

5

T61

2

auto[0]

from_0to1

auto[1]

auto[0]

80

1

T6

1

T23

1

T17

2

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T6

1

T23

1

T18

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T6

1

T17

2

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T23

2

T18

2

T74

2

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T6

1

T23

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T6

1

T23

1

T17

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T6

1

T23

2

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T6

1

T68

2

T33

5

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T6

1

T23

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T33

5

T394

1

T159

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1183

1

T6

9

T23

13

T17

11

auto[1]

1168

1

T6

11

T23

7

T17

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

573

1

T6

4

T23

8

T17

6

from_0to1

566

1

T6

4

T23

8

T17

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T6

10

T23

12

T17

7

auto[1]

1197

1

T6

10

T23

8

T17

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T6

7

T23

11

T17

9

auto[1]

1189

1

T6

13

T23

9

T17

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T23

2

T17

1

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T6

1

T23

1

T72

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T6

1

T17

1

T18

2

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T23

2

T18

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T23

2

T72

1

T74

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T6

1

T23

1

T17

1

auto[0]

from_0to1

auto[1]

auto[0]

83

1

T23

1

T18

1

T33

4

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T23

1

T17

1

T72

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T23

1

T18

1

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T17

2

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T23

2

T17

1

T74

2

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T6

1

T17

1

T33

4

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T23

2

T18

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T6

1

T23

1

T18

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T17

2

T72

1

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T6

2

T17

2

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T6

9

T23

10

T17

11

auto[1]

1166

1

T6

11

T23

10

T17

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

558

1

T6

4

T23

5

T17

5

from_0to1

562

1

T6

5

T23

5

T17

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1212

1

T6

10

T23

12

T17

12

auto[1]

1139

1

T6

10

T23

8

T17

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T6

8

T23

11

T17

7

auto[1]

1165

1

T6

12

T23

9

T17

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T23

1

T18

3

T33

8

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T6

1

T17

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T6

1

T23

1

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T23

2

T17

2

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T6

1

T23

2

T17

3

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T18

2

T68

1

T74

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T17

1

T33

3

T204

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T68

1

T74

1

T33

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T23

1

T18

1

T74

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T17

1

T74

1

T33

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T6

2

T68

2

T74

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T18

1

T72

1

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T6

1

T23

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

86

1

T6

1

T17

1

T68

2

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T6

1

T18

2

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T6

1

T23

2

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T6

13

T23

13

T17

12

auto[1]

1188

1

T6

7

T23

7

T17

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

558

1

T6

5

T23

5

T17

6

from_0to1

570

1

T6

5

T23

5

T17

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T6

11

T23

11

T17

15

auto[1]

1159

1

T6

9

T23

9

T17

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T6

10

T23

15

T17

9

auto[1]

1197

1

T6

10

T23

5

T17

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T23

1

T17

3

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T6

2

T72

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T6

1

T23

2

T72

1

auto[0]

from_1to0

auto[1]

auto[1]

86

1

T6

1

T18

3

T68

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T6

1

T23

2

T17

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T18

2

T72

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T23

1

T17

1

T72

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T6

1

T23

1

T18

2

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T23

1

T17

1

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T23

1

T18

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T6

1

T17

1

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T17

1

T72

1

T74

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T6

1

T17

1

T72

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T17

1

T18

1

T68

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T6

2

T23

1

T33

4

auto[1]

from_0to1

auto[1]

auto[1]

85

1

T17

1

T18

1

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1199

1

T6

7

T23

11

T17

7

auto[1]

1152

1

T6

13

T23

9

T17

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T6

6

T23

5

T17

4

from_0to1

586

1

T6

7

T23

5

T17

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T6

10

T23

12

T17

12

auto[1]

1167

1

T6

10

T23

8

T17

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T6

10

T23

8

T17

11

auto[1]

1148

1

T6

10

T23

12

T17

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T6

1

T18

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T17

1

T18

2

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T6

1

T23

2

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T18

1

T72

1

T74

2

auto[0]

from_0to1

auto[0]

auto[0]

84

1

T17

1

T18

3

T72

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T23

2

T18

2

T33

4

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T6

1

T23

1

T74

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T6

1

T18

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T6

1

T18

1

T72

2

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T6

1

T23

1

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T6

1

T23

1

T17

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T6

1

T23

1

T17

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T6

1

T72

1

T33

3

auto[1]

from_0to1

auto[0]

auto[1]

84

1

T6

2

T23

2

T17

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T6

1

T17

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T6

1

T33

4

T204

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T6

13

T23

8

T17

10

auto[1]

1223

1

T6

7

T23

12

T17

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T6

4

T23

5

T17

5

from_0to1

564

1

T6

5

T23

6

T17

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T6

10

T23

11

T17

9

auto[1]

1155

1

T6

10

T23

9

T17

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T6

11

T23

9

T17

9

auto[1]

1175

1

T6

9

T23

11

T17

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T72

1

T74

2

T33

7

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T17

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T6

2

T68

2

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T6

1

T23

2

T17

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T6

2

T23

1

T17

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T23

1

T17

1

T72

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T6

1

T23

1

T72

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T17

1

T18

1

T72

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T23

2

T18

1

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T18

1

T68

1

T33

2

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T17

2

T18

2

T74

3

auto[1]

from_1to0

auto[1]

auto[1]

83

1

T23

1

T17

1

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T23

1

T18

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

78

1

T6

1

T23

1

T17

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T6

1

T17

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T23

1

T33

6

T394

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T6

7

T23

10

T17

11

auto[1]

1164

1

T6

13

T23

10

T17

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T6

5

T23

8

T17

4

from_0to1

544

1

T6

5

T23

7

T17

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1190

1

T6

12

T23

8

T17

9

auto[1]

1161

1

T6

8

T23

12

T17

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1207

1

T6

8

T23

12

T17

11

auto[1]

1144

1

T6

12

T23

8

T17

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T23

1

T68

1

T74

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T23

1

T72

2

T74

2

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T17

2

T68

1

T33

3

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T6

1

T23

2

T17

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T6

1

T23

1

T17

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T6

1

T18

1

T72

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T23

3

T72

1

T33

2

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T18

1

T68

2

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T18

1

T72

1

T74

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T6

2

T23

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T6

2

T23

2

T18

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T23

1

T17

1

T18

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T6

1

T23

1

T18

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T6

1

T17

1

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T23

1

T17

3

T74

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T6

1

T23

1

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T6

6

T23

8

T17

11

auto[1]

1181

1

T6

14

T23

12

T17

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T6

7

T23

4

T17

7

from_0to1

556

1

T6

7

T23

4

T17

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T6

12

T23

9

T17

9

auto[1]

1166

1

T6

8

T23

11

T17

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T6

4

T23

7

T17

9

auto[1]

1190

1

T6

16

T23

13

T17

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T18

2

T33

5

T394

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T72

2

T68

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T6

1

T23

1

T17

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T6

1

T17

2

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T6

1

T18

1

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T6

1

T23

1

T17

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T17

1

T74

2

T33

5

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T17

1

T74

1

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T6

1

T23

1

T17

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T6

3

T23

1

T17

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T23

1

T72

1

T74

2

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T6

1

T18

2

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

83

1

T17

2

T18

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T6

4

T23

1

T17

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T18

1

T72

1

T33

8

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T6

1

T23

2

T18

1