Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

108574

1

T4

5

T5

6

T6

186

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	129852	1			T4	9		T5	8		T6	272
values[0x0]	61141	1			T4	1		T5	3		T6	75
values[0x1]	62229	1			T4	2		T5	6		T6	97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	117150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136072

1

T4

7

T5

10

T6

241

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	707	1			T15	1		T2	8		T16	1
valid_sources[0x01]	775	1			T6	2		T25	2		T10	1
valid_sources[0x02]	710	1			T25	1		T16	5		T72	4
valid_sources[0x03]	782	1			T6	3		T25	2		T8	1
valid_sources[0x04]	886	1			T6	1		T25	2		T8	1
valid_sources[0x05]	894	1			T6	3		T25	1		T50	1
valid_sources[0x06]	1452	1			T6	8		T26	1		T72	2
valid_sources[0x07]	2436	1			T25	3		T2	14		T19	1
valid_sources[0x08]	1125	1			T6	1		T15	1		T10	10
valid_sources[0x09]	846	1			T6	1		T25	1		T2	10
valid_sources[0x0a]	961	1			T25	1		T14	1		T2	5
valid_sources[0x0b]	939	1			T23	2		T25	1		T15	1
valid_sources[0x0c]	1033	1			T6	2		T27	63		T28	1
valid_sources[0x0d]	993	1			T6	1		T25	5		T20	1
valid_sources[0x0e]	773	1			T22	2		T25	3		T15	2
valid_sources[0x0f]	919	1			T6	2		T68	4		T50	1
valid_sources[0x10]	829	1			T6	2		T25	2		T2	11
valid_sources[0x11]	875	1			T6	3		T14	1		T2	5
valid_sources[0x12]	731	1			T6	5		T25	2		T14	1
valid_sources[0x13]	1696	1			T6	5		T68	9		T50	2
valid_sources[0x14]	860	1			T6	3		T23	3		T25	2
valid_sources[0x15]	933	1			T25	4		T2	27		T50	2
valid_sources[0x16]	1213	1			T25	3		T2	3		T72	5
valid_sources[0x17]	856	1			T6	4		T25	1		T2	12
valid_sources[0x18]	881	1			T6	1		T25	2		T50	4
valid_sources[0x19]	757	1			T28	2		T8	1		T68	1
valid_sources[0x1a]	1405	1			T6	2		T25	2		T15	1
valid_sources[0x1b]	1403	1			T6	1		T25	1		T50	1
valid_sources[0x1c]	1147	1			T5	1		T25	3		T2	2
valid_sources[0x1d]	989	1			T68	4		T10	6		T43	1
valid_sources[0x1e]	937	1			T6	4		T19	2		T10	5
valid_sources[0x1f]	1155	1			T6	6		T25	1		T19	2
valid_sources[0x20]	924	1			T6	1		T25	1		T2	10
valid_sources[0x21]	677	1			T6	1		T50	1		T74	2
valid_sources[0x22]	1003	1			T6	5		T25	4		T1	9
valid_sources[0x23]	720	1			T25	3		T2	20		T10	2
valid_sources[0x24]	1229	1			T10	8		T50	1		T74	2
valid_sources[0x25]	804	1			T5	1		T6	3		T25	4
valid_sources[0x26]	933	1			T25	1		T2	17		T19	3
valid_sources[0x27]	651	1			T6	1		T2	4		T68	2
valid_sources[0x28]	825	1			T6	1		T25	3		T14	1
valid_sources[0x29]	880	1			T6	1		T23	5		T15	1
valid_sources[0x2a]	1153	1			T6	2		T24	5		T25	3
valid_sources[0x2b]	824	1			T5	1		T6	6		T25	2
valid_sources[0x2c]	758	1			T6	2		T25	1		T2	6
valid_sources[0x2d]	884	1			T6	1		T22	7		T25	2
valid_sources[0x2e]	859	1			T6	3		T25	3		T2	10
valid_sources[0x2f]	721	1			T6	2		T25	3		T14	2
valid_sources[0x30]	821	1			T25	2		T15	2		T68	7
valid_sources[0x31]	761	1			T15	1		T2	8		T8	1
valid_sources[0x32]	1190	1			T6	2		T25	2		T2	2
valid_sources[0x33]	1295	1			T6	11		T23	7		T25	2
valid_sources[0x34]	1077	1			T6	5		T25	2		T2	1
valid_sources[0x35]	714	1			T6	3		T25	1		T19	1
valid_sources[0x36]	1110	1			T25	2		T2	29		T10	1
valid_sources[0x37]	811	1			T25	2		T15	1		T8	1
valid_sources[0x38]	729	1			T6	2		T25	1		T68	2
valid_sources[0x39]	2641	1			T6	2		T25	2		T1	1
valid_sources[0x3a]	675	1			T6	1		T25	3		T26	1
valid_sources[0x3b]	929	1			T23	5		T25	2		T68	1
valid_sources[0x3c]	753	1			T25	3		T14	2		T2	44
valid_sources[0x3d]	942	1			T6	3		T25	1		T15	1
valid_sources[0x3e]	1788	1			T6	4		T23	3		T25	2
valid_sources[0x3f]	774	1			T6	5		T25	2		T14	1
valid_sources[0x40]	921	1			T5	1		T6	4		T25	3
valid_sources[0x41]	798	1			T6	2		T23	1		T2	3
valid_sources[0x42]	775	1			T6	1		T25	3		T14	1
valid_sources[0x43]	802	1			T6	3		T25	1		T16	4
valid_sources[0x44]	858	1			T6	4		T25	1		T26	1
valid_sources[0x45]	1353	1			T5	1		T6	1		T25	1
valid_sources[0x46]	1172	1			T6	5		T25	3		T68	6
valid_sources[0x47]	819	1			T6	1		T25	1		T19	1
valid_sources[0x48]	942	1			T25	4		T2	3		T68	1
valid_sources[0x49]	1618	1			T6	2		T25	4		T14	2
valid_sources[0x4a]	951	1			T6	1		T25	1		T15	1
valid_sources[0x4b]	847	1			T6	1		T23	2		T25	2
valid_sources[0x4c]	795	1			T6	6		T2	4		T68	4
valid_sources[0x4d]	1207	1			T6	4		T25	3		T14	2
valid_sources[0x4e]	864	1			T25	1		T2	16		T16	1
valid_sources[0x4f]	896	1			T6	4		T25	3		T2	6
valid_sources[0x50]	834	1			T6	3		T23	6		T25	1
valid_sources[0x51]	780	1			T6	4		T25	2		T50	2
valid_sources[0x52]	797	1			T25	2		T26	2		T14	1
valid_sources[0x53]	759	1			T25	3		T2	42		T68	1
valid_sources[0x54]	820	1			T6	1		T25	3		T2	28
valid_sources[0x55]	687	1			T25	1		T2	6		T68	3
valid_sources[0x56]	723	1			T6	2		T25	4		T2	5
valid_sources[0x57]	1047	1			T25	2		T26	1		T1	2
valid_sources[0x58]	2083	1			T6	6		T2	9		T18	122
valid_sources[0x59]	1489	1			T25	1		T7	2		T68	2
valid_sources[0x5a]	773	1			T6	3		T25	2		T68	7
valid_sources[0x5b]	754	1			T6	1		T25	2		T2	10
valid_sources[0x5c]	880	1			T6	1		T23	4		T25	1
valid_sources[0x5d]	741	1			T6	6		T25	5		T2	18
valid_sources[0x5e]	916	1			T6	3		T25	3		T68	2
valid_sources[0x5f]	778	1			T25	1		T14	1		T15	1
valid_sources[0x60]	741	1			T25	3		T14	1		T2	10
valid_sources[0x61]	855	1			T6	1		T25	4		T15	2
valid_sources[0x62]	904	1			T6	5		T25	2		T10	2
valid_sources[0x63]	941	1			T6	2		T25	1		T17	123
valid_sources[0x64]	838	1			T6	1		T25	2		T68	1
valid_sources[0x65]	813	1			T25	3		T20	1		T50	1
valid_sources[0x66]	1148	1			T6	1		T23	3		T25	1
valid_sources[0x67]	762	1			T25	1		T10	2		T50	1
valid_sources[0x68]	764	1			T25	1		T10	1		T50	3
valid_sources[0x69]	1114	1			T6	3		T25	2		T2	5
valid_sources[0x6a]	762	1			T6	3		T25	2		T2	5
valid_sources[0x6b]	700	1			T6	3		T25	1		T50	1
valid_sources[0x6c]	989	1			T6	1		T2	7		T8	1
valid_sources[0x6d]	893	1			T6	2		T25	1		T19	3
valid_sources[0x6e]	2024	1			T25	2		T15	1		T9	1164
valid_sources[0x6f]	1386	1			T6	1		T15	1		T16	17
valid_sources[0x70]	941	1			T6	2		T25	1		T8	1
valid_sources[0x71]	826	1			T25	1		T14	1		T68	2
valid_sources[0x72]	921	1			T2	27		T68	2		T10	5
valid_sources[0x73]	893	1			T25	1		T19	1		T8	1
valid_sources[0x74]	934	1			T25	1		T10	2		T50	2
valid_sources[0x75]	1083	1			T6	3		T25	1		T20	1
valid_sources[0x76]	726	1			T25	2		T15	1		T72	7
valid_sources[0x77]	854	1			T6	5		T25	2		T14	1
valid_sources[0x78]	985	1			T2	5		T72	10		T68	3
valid_sources[0x79]	789	1			T25	1		T2	3		T68	4
valid_sources[0x7a]	726	1			T25	3		T15	1		T2	17
valid_sources[0x7b]	837	1			T6	1		T25	3		T26	1
valid_sources[0x7c]	870	1			T2	10		T72	3		T68	2
valid_sources[0x7d]	744	1			T6	1		T25	3		T10	2
valid_sources[0x7e]	1232	1			T25	1		T15	2		T8	1
valid_sources[0x7f]	797	1			T6	7		T25	3		T2	9
valid_sources[0x80]	929	1			T6	1		T25	3		T2	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58831

1

T4

5

T5

2

T6

137

values[0x0]

all_enables

biggest_size

29143

1

T5

2

T6

29

T22

4

values[0x1]

all_enables

biggest_size

20600

1

T5

2

T6

20

T22

3