Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T6,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T22
0	1	Covered	T112,T97,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T22
0	1	Covered	T5,T6,T22
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T6,T22
1	-	Covered	T5,T6,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T22
DetectSt	168	Covered	T5,T6,T22
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T6,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T22
DebounceSt->IdleSt	163	Covered	T100,T141,T142
DetectSt->IdleSt	186	Covered	T112,T97,T117
DetectSt->StableSt	191	Covered	T5,T6,T22
IdleSt->DebounceSt	148	Covered	T5,T6,T22
StableSt->IdleSt	206	Covered	T5,T6,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T6,T22
0	1	Covered	T5,T6,T22
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T22
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T142,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T22
DetectSt	-	-	-	-	1	-	-	Covered	T112,T97,T117
DetectSt	-	-	-	-	0	1	-	Covered	T5,T6,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T6,T22
StableSt	-	-	-	-	-	-	0	Covered	T5,T6,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	297	0	0
CntIncr_A	6753481	211490	0	0
CntNoWrap_A	6753481	6069526	0	0
DetectStDropOut_A	6753481	3	0	0
DetectedOut_A	6753481	936	0	0
DetectedPulseOut_A	6753481	139	0	0
DisabledIdleSt_A	6753481	5829316	0	0
DisabledNoDetection_A	6753481	5831601	0	0
EnterDebounceSt_A	6753481	159	0	0
EnterDetectSt_A	6753481	142	0	0
EnterStableSt_A	6753481	139	0	0
PulseIsPulse_A	6753481	139	0	0
StayInStableSt	6753481	797	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6887	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	138	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	297	0	0
T1	909	0	0	0
T5	685	2	0	0
T6	4492	2	0	0
T13	0	6	0	0
T20	0	4	0	0
T22	703	4	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	4	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	0	4	0	0
T102	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	211490	0	0
T1	909	0	0	0
T5	685	78	0	0
T6	4492	41	0	0
T13	0	119	0	0
T20	0	84	0	0
T22	703	91	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	110	0	0
T52	0	217	0	0
T53	0	12	0	0
T54	0	160	0	0
T102	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069526	0	0
T4	1362	961	0	0
T5	685	282	0	0
T6	4492	626	0	0
T22	703	298	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3	0	0
T84	7666	0	0	0
T95	1520	0	0	0
T97	0	1	0	0
T112	435430	1	0	0
T117	0	1	0	0
T126	443	0	0	0
T127	6148	0	0	0
T128	505	0	0	0
T129	419	0	0	0
T130	491	0	0	0
T131	840	0	0	0
T132	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	936	0	0
T1	909	0	0	0
T5	685	11	0	0
T6	4492	8	0	0
T13	0	13	0	0
T20	0	21	0	0
T22	703	21	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	15	0	0
T52	0	23	0	0
T53	0	5	0	0
T54	0	17	0	0
T102	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	139	0	0
T1	909	0	0	0
T5	685	1	0	0
T6	4492	1	0	0
T13	0	3	0	0
T20	0	2	0	0
T22	703	2	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T102	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5829316	0	0
T4	1362	961	0	0
T5	685	152	0	0
T6	4492	548	0	0
T22	703	110	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5831601	0	0
T4	1362	962	0	0
T5	685	153	0	0
T6	4492	558	0	0
T22	703	111	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	159	0	0
T1	909	0	0	0
T5	685	1	0	0
T6	4492	1	0	0
T13	0	3	0	0
T20	0	2	0	0
T22	703	2	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T102	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	142	0	0
T1	909	0	0	0
T5	685	1	0	0
T6	4492	1	0	0
T13	0	3	0	0
T20	0	2	0	0
T22	703	2	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T102	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	139	0	0
T1	909	0	0	0
T5	685	1	0	0
T6	4492	1	0	0
T13	0	3	0	0
T20	0	2	0	0
T22	703	2	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T102	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	139	0	0
T1	909	0	0	0
T5	685	1	0	0
T6	4492	1	0	0
T13	0	3	0	0
T20	0	2	0	0
T22	703	2	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T102	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	797	0	0
T1	909	0	0	0
T5	685	10	0	0
T6	4492	7	0	0
T13	0	10	0	0
T20	0	19	0	0
T22	703	19	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	13	0	0
T52	0	20	0	0
T53	0	4	0	0
T54	0	15	0	0
T102	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6887	0	0
T1	0	1	0	0
T4	1362	4	0	0
T5	685	3	0	0
T6	4492	27	0	0
T14	0	8	0	0
T22	703	3	0	0
T23	508	6	0	0
T24	915	0	0	0
T25	4217	23	0	0
T26	426	2	0	0
T27	522	4	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	138	0	0
T1	909	0	0	0
T5	685	1	0	0
T6	4492	1	0	0
T13	0	3	0	0
T20	0	2	0	0
T22	703	2	0	0
T23	508	0	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T33	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T102	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T21,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T33,T34
1	0	Covered	T4,T5,T6
1	1	Covered	T21,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T33,T34
0	1	Covered	T96,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T33,T34
0	1	Unreachable
1	0	Covered	T21,T33,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T33,T34
DetectSt	168	Covered	T21,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T33,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T33,T34
DebounceSt->IdleSt	163	Covered	T33,T64,T55
DetectSt->IdleSt	186	Covered	T96,T97,T98
DetectSt->StableSt	191	Covered	T21,T33,T34
IdleSt->DebounceSt	148	Covered	T21,T33,T34
StableSt->IdleSt	206	Covered	T21,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T33,T34
0	1	Covered	T21,T33,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T33,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T64,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T96,T97,T98
DetectSt	-	-	-	-	0	1	-	Covered	T21,T33,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T33,T34
StableSt	-	-	-	-	-	-	0	Covered	T21,T33,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	160	0	0
CntIncr_A	6753481	157827	0	0
CntNoWrap_A	6753481	6069663	0	0
DetectStDropOut_A	6753481	6	0	0
DetectedOut_A	6753481	202179	0	0
DetectedPulseOut_A	6753481	48	0	0
DisabledIdleSt_A	6753481	5117958	0	0
DisabledNoDetection_A	6753481	5120301	0	0
EnterDebounceSt_A	6753481	107	0	0
EnterDetectSt_A	6753481	54	0	0
EnterStableSt_A	6753481	48	0	0
PulseIsPulse_A	6753481	48	0	0
StayInStableSt	6753481	202131	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6887	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_sticky_sva.StableStDropOut_A	6753481	428999	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	160	0	0
T21	806	2	0	0
T33	30342	4	0	0
T34	0	2	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	2	0	0
T62	0	4	0	0
T63	0	4	0	0
T64	0	3	0	0
T66	0	2	0	0
T78	0	2	0	0
T79	0	4	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	157827	0	0
T21	806	84	0	0
T33	30342	117	0	0
T34	0	14	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	62	0	0
T62	0	162	0	0
T63	0	164	0	0
T64	0	120	0	0
T66	0	25753	0	0
T78	0	94	0	0
T79	0	56	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069663	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6	0	0
T90	0	1	0	0
T96	1174	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T144	0	1	0	0
T145	496	0	0	0
T146	543	0	0	0
T147	492	0	0	0
T148	5286	0	0	0
T149	11348	0	0	0
T150	562	0	0	0
T151	5070	0	0	0
T152	503	0	0	0
T153	11997	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	202179	0	0
T21	806	234	0	0
T33	30342	79	0	0
T34	0	12	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	411	0	0
T63	0	650	0	0
T66	0	107807	0	0
T78	0	360	0	0
T79	0	247	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	78	0	0
T137	0	100	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T21	806	1	0	0
T33	30342	1	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	1	0	0
T137	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5117958	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5120301	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	107	0	0
T21	806	1	0	0
T33	30342	3	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	3	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	54	0	0
T21	806	1	0	0
T33	30342	1	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	1	0	0
T137	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T21	806	1	0	0
T33	30342	1	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	1	0	0
T137	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T21	806	1	0	0
T33	30342	1	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	1	0	0
T137	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	202131	0	0
T21	806	233	0	0
T33	30342	78	0	0
T34	0	11	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	409	0	0
T63	0	648	0	0
T66	0	107806	0	0
T78	0	359	0	0
T79	0	245	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	77	0	0
T137	0	99	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6887	0	0
T1	0	1	0	0
T4	1362	4	0	0
T5	685	3	0	0
T6	4492	27	0	0
T14	0	8	0	0
T22	703	3	0	0
T23	508	6	0	0
T24	915	0	0	0
T25	4217	23	0	0
T26	426	2	0	0
T27	522	4	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	428999	0	0
T21	806	46	0	0
T33	30342	109	0	0
T34	0	64	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	112	0	0
T63	0	184	0	0
T66	0	77	0	0
T78	0	135	0	0
T79	0	1310	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	78	0	0
T137	0	68	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T23
1	1	Covered	T4,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T21,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T33,T34
1	0	Covered	T4,T6,T23
1	1	Covered	T21,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T33,T62
0	1	Covered	T34,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T33,T62
0	1	Unreachable
1	0	Covered	T21,T33,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T33,T34
DetectSt	168	Covered	T21,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T33,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T33,T34
DebounceSt->IdleSt	163	Covered	T63,T55,T88
DetectSt->IdleSt	186	Covered	T34,T94,T95
DetectSt->StableSt	191	Covered	T21,T33,T62
IdleSt->DebounceSt	148	Covered	T21,T33,T34
StableSt->IdleSt	206	Covered	T21,T33,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T33,T34
0	1	Covered	T21,T33,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T33,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T88,T138
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T34,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T21,T33,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T33,T62
StableSt	-	-	-	-	-	-	0	Covered	T21,T33,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	166	0	0
CntIncr_A	6753481	43047	0	0
CntNoWrap_A	6753481	6069657	0	0
DetectStDropOut_A	6753481	14	0	0
DetectedOut_A	6753481	93525	0	0
DetectedPulseOut_A	6753481	40	0	0
DisabledIdleSt_A	6753481	5117958	0	0
DisabledNoDetection_A	6753481	5120301	0	0
EnterDebounceSt_A	6753481	113	0	0
EnterDetectSt_A	6753481	54	0	0
EnterStableSt_A	6753481	40	0	0
PulseIsPulse_A	6753481	40	0	0
StayInStableSt	6753481	93485	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_sticky_sva.StableStDropOut_A	6753481	562432	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	166	0	0
T21	806	2	0	0
T33	30342	2	0	0
T34	0	2	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	2	0	0
T62	0	4	0	0
T63	0	5	0	0
T64	0	2	0	0
T66	0	2	0	0
T78	0	2	0	0
T79	0	4	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	43047	0	0
T21	806	97	0	0
T33	30342	36	0	0
T34	0	76	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	61	0	0
T62	0	38	0	0
T63	0	175	0	0
T64	0	36185	0	0
T66	0	50	0	0
T78	0	59	0	0
T79	0	164	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069657	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	14	0	0
T34	839	1	0	0
T53	665	0	0	0
T57	28338	0	0	0
T62	1452	0	0	0
T71	492	0	0	0
T94	0	1	0	0
T95	0	4	0	0
T101	2731	0	0	0
T133	5966	0	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	430	0	0	0
T159	1308	0	0	0
T160	94053	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	93525	0	0
T21	806	204	0	0
T33	30342	189	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	93	0	0
T63	0	217	0	0
T64	0	84349	0	0
T66	0	176	0	0
T78	0	207	0	0
T79	0	558	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	423	0	0
T137	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	40	0	0
T21	806	1	0	0
T33	30342	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0
T137	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5117958	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5120301	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	113	0	0
T21	806	1	0	0
T33	30342	1	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	2	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	54	0	0
T21	806	1	0	0
T33	30342	1	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	40	0	0
T21	806	1	0	0
T33	30342	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0
T137	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	40	0	0
T21	806	1	0	0
T33	30342	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0
T137	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	93485	0	0
T21	806	203	0	0
T33	30342	188	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	91	0	0
T63	0	216	0	0
T64	0	84348	0	0
T66	0	175	0	0
T78	0	206	0	0
T79	0	556	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	422	0	0
T137	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	562432	0	0
T21	806	60	0	0
T33	30342	153	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	545	0	0
T63	0	137	0	0
T64	0	70	0	0
T66	0	133394	0	0
T78	0	321	0	0
T79	0	897	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	295	0	0
T137	0	53	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T21,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T62,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T33,T34
1	0	Covered	T4,T6,T23
1	1	Covered	T21,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T62,T63
0	1	Covered	T88,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T62,T63
0	1	Unreachable
1	0	Covered	T21,T62,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T33,T34
DetectSt	168	Covered	T21,T62,T63
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T62,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T62,T63
DebounceSt->IdleSt	163	Covered	T33,T34,T55
DetectSt->IdleSt	186	Covered	T88,T89,T90
DetectSt->StableSt	191	Covered	T21,T62,T63
IdleSt->DebounceSt	148	Covered	T21,T33,T34
StableSt->IdleSt	206	Covered	T21,T62,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T33,T34
0	1	Covered	T21,T33,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T62,T63
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T62,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T34,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T88,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T21,T62,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T62,T63
StableSt	-	-	-	-	-	-	0	Covered	T21,T62,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	170	0	0
CntIncr_A	6753481	76445	0	0
CntNoWrap_A	6753481	6069653	0	0
DetectStDropOut_A	6753481	7	0	0
DetectedOut_A	6753481	396702	0	0
DetectedPulseOut_A	6753481	44	0	0
DisabledIdleSt_A	6753481	5117958	0	0
DisabledNoDetection_A	6753481	5120301	0	0
EnterDebounceSt_A	6753481	120	0	0
EnterDetectSt_A	6753481	51	0	0
EnterStableSt_A	6753481	44	0	0
PulseIsPulse_A	6753481	44	0	0
StayInStableSt	6753481	396658	0	0
gen_high_event_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_sticky_sva.StableStDropOut_A	6753481	472121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	170	0	0
T21	806	2	0	0
T33	30342	5	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	2	0	0
T62	0	4	0	0
T63	0	4	0	0
T64	0	2	0	0
T66	0	2	0	0
T78	0	4	0	0
T79	0	8	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	76445	0	0
T21	806	21	0	0
T33	30342	135	0	0
T34	0	54	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	61	0	0
T62	0	102	0	0
T63	0	136	0	0
T64	0	54	0	0
T66	0	14	0	0
T78	0	308	0	0
T79	0	792	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069653	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	7	0	0
T88	1566	2	0	0
T89	0	2	0	0
T90	0	1	0	0
T111	5168	0	0	0
T137	1185	0	0	0
T138	211453	0	0	0
T161	0	2	0	0
T162	422	0	0	0
T163	2851	0	0	0
T164	2692	0	0	0
T165	665	0	0	0
T166	424	0	0	0
T167	693	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	396702	0	0
T21	806	26	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	193	0	0
T63	0	380	0	0
T64	0	230	0	0
T66	0	88	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	651	0	0
T137	0	101	0	0
T138	0	498	0	0
T139	0	129	0	0
T140	0	703	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T21	806	1	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5117958	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5120301	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	120	0	0
T21	806	1	0	0
T33	30342	5	0	0
T34	0	1	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T55	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	4	0	0
T79	0	8	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	51	0	0
T21	806	1	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T88	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T21	806	1	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T21	806	1	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	396658	0	0
T21	806	25	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	191	0	0
T63	0	378	0	0
T64	0	229	0	0
T66	0	87	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	650	0	0
T137	0	100	0	0
T138	0	497	0	0
T139	0	128	0	0
T140	0	702	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	472121	0	0
T21	806	324	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T52	746	0	0	0
T62	0	403	0	0
T63	0	601	0	0
T64	0	120325	0	0
T66	0	133536	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T136	0	71	0	0
T137	0	96	0	0
T138	0	210453	0	0
T139	0	304	0	0
T140	0	45	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T12,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T12,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T42
0	1	Covered	T168,T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T42
0	1	Covered	T12,T170,T171
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T42
1	-	Covered	T12,T170,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T42
DetectSt	168	Covered	T3,T12,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T42
DebounceSt->IdleSt	163	Covered	T84
DetectSt->IdleSt	186	Covered	T168,T169
DetectSt->StableSt	191	Covered	T3,T12,T42
IdleSt->DebounceSt	148	Covered	T3,T12,T42
StableSt->IdleSt	206	Covered	T12,T55,T172

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T42
0	1	Covered	T3,T12,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T42
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T42
DetectSt	-	-	-	-	1	-	-	Covered	T168,T169
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T55,T170
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	61	0	0
CntIncr_A	6753481	1387	0	0
CntNoWrap_A	6753481	6069762	0	0
DetectStDropOut_A	6753481	2	0	0
DetectedOut_A	6753481	1957	0	0
DetectedPulseOut_A	6753481	28	0	0
DisabledIdleSt_A	6753481	5946873	0	0
DisabledNoDetection_A	6753481	5949166	0	0
EnterDebounceSt_A	6753481	31	0	0
EnterDetectSt_A	6753481	30	0	0
EnterStableSt_A	6753481	28	0	0
PulseIsPulse_A	6753481	28	0	0
StayInStableSt	6753481	1908	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	61	0	0
T3	644	2	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	4	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	2	0	0
T55	0	2	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1387	0	0
T3	644	34	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	68	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	91	0	0
T55	0	22	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	17	0	0
T173	0	12	0	0
T174	0	34	0	0
T175	0	79	0	0
T176	0	48	0	0
T177	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069762	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2	0	0
T168	135827	1	0	0
T169	0	1	0	0
T178	19003	0	0	0
T179	23672	0	0	0
T180	528	0	0	0
T181	421	0	0	0
T182	1501	0	0	0
T183	422	0	0	0
T184	1427	0	0	0
T185	9700	0	0	0
T186	13687	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1957	0	0
T3	644	103	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	210	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	53	0	0
T55	0	23	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	58	0	0
T173	0	61	0	0
T174	0	43	0	0
T175	0	402	0	0
T176	0	46	0	0
T177	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	28	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5946873	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5949166	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	31	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	30	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	28	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	28	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1908	0	0
T3	644	101	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	207	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	51	0	0
T55	0	22	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	56	0	0
T173	0	59	0	0
T174	0	41	0	0
T175	0	400	0	0
T176	0	44	0	0
T177	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6	0	0
T12	788	1	0	0
T13	3779	0	0	0
T21	806	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T48	14380	0	0	0
T52	746	0	0	0
T80	522	0	0	0
T98	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	427	0	0	0
T190	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T6,T23,T26
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T86,T112,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T3,T11,T173
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T11
1	-	Covered	T3,T11,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T1,T99,T170
DetectSt->IdleSt	186	Covered	T86,T112,T98
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T3,T11,T173

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T99,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T86,T112,T98
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T173
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	127	0	0
CntIncr_A	6753481	3417	0	0
CntNoWrap_A	6753481	6069696	0	0
DetectStDropOut_A	6753481	4	0	0
DetectedOut_A	6753481	4503	0	0
DetectedPulseOut_A	6753481	56	0	0
DisabledIdleSt_A	6753481	6001259	0	0
DisabledNoDetection_A	6753481	6003548	0	0
EnterDebounceSt_A	6753481	67	0	0
EnterDetectSt_A	6753481	60	0	0
EnterStableSt_A	6753481	56	0	0
PulseIsPulse_A	6753481	56	0	0
StayInStableSt	6753481	4420	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	2759	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	127	0	0
T1	909	3	0	0
T2	23577	0	0	0
T3	644	2	0	0
T11	0	4	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	2	0	0
T55	0	2	0	0
T63	0	2	0	0
T86	0	2	0	0
T99	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3417	0	0
T1	909	122	0	0
T2	23577	0	0	0
T3	644	34	0	0
T11	0	30	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	94	0	0
T55	0	22	0	0
T63	0	25	0	0
T86	0	62	0	0
T99	0	158	0	0
T173	0	12	0	0
T174	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069696	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4	0	0
T86	576	1	0	0
T98	0	1	0	0
T109	18799	0	0	0
T112	0	1	0	0
T143	642	0	0	0
T191	0	1	0	0
T192	425	0	0	0
T193	527	0	0	0
T194	522	0	0	0
T195	407	0	0	0
T196	727	0	0	0
T197	502	0	0	0
T198	8421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4503	0	0
T1	909	41	0	0
T2	23577	0	0	0
T3	644	40	0	0
T11	0	69	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	44	0	0
T55	0	24	0	0
T63	0	203	0	0
T99	0	41	0	0
T173	0	63	0	0
T174	0	103	0	0
T199	0	297	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	56	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T11	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6001259	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6003548	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	67	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	1	0	0
T11	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T99	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	60	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T11	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T99	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	56	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T11	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	56	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T11	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4420	0	0
T1	909	39	0	0
T2	23577	0	0	0
T3	644	39	0	0
T11	0	67	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	42	0	0
T55	0	23	0	0
T63	0	201	0	0
T99	0	39	0	0
T173	0	62	0	0
T174	0	102	0	0
T199	0	294	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2759	0	0
T1	909	2	0	0
T3	0	1	0	0
T6	4492	22	0	0
T14	496	5	0	0
T15	0	3	0	0
T16	0	3	0	0
T17	0	6	0	0
T22	703	0	0	0
T23	508	5	0	0
T24	915	0	0	0
T25	4217	0	0	0
T26	426	1	0	0
T27	522	5	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	28	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T58	435	0	0	0
T103	422	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	2	0	0