Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T43,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T43,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T43,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T48
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T43,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T43,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T43,T46
0	1	Covered	T43,T63,T99
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T43,T46
1	-	Covered	T43,T63,T99

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T43,T46
DetectSt	168	Covered	T1,T43,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T43,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T43,T46
DebounceSt->IdleSt	163	Covered	T84,T168
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T43,T46
IdleSt->DebounceSt	148	Covered	T1,T43,T46
StableSt->IdleSt	206	Covered	T43,T63,T99

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T43,T46
0	1	Covered	T1,T43,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T43,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T43,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T43,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T168
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T43,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T43,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T63,T99
StableSt	-	-	-	-	-	-	0	Covered	T1,T43,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	98	0	0
CntIncr_A	6753481	45219	0	0
CntNoWrap_A	6753481	6069725	0	0
DetectStDropOut_A	6753481	0	0	0
DetectedOut_A	6753481	8730	0	0
DetectedPulseOut_A	6753481	48	0	0
DisabledIdleSt_A	6753481	5941585	0	0
DisabledNoDetection_A	6753481	5943864	0	0
EnterDebounceSt_A	6753481	50	0	0
EnterDetectSt_A	6753481	48	0	0
EnterStableSt_A	6753481	48	0	0
PulseIsPulse_A	6753481	48	0	0
StayInStableSt	6753481	8654	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	98	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	2	0	0
T55	0	2	0	0
T63	0	2	0	0
T99	0	2	0	0
T160	0	2	0	0
T199	0	6	0	0
T202	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	45219	0	0
T1	909	61	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	81	0	0
T44	0	94	0	0
T46	0	95	0	0
T55	0	22	0	0
T63	0	25	0	0
T99	0	79	0	0
T160	0	34059	0	0
T199	0	111	0	0
T202	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069725	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	8730	0	0
T1	909	42	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	136	0	0
T44	0	139	0	0
T46	0	165	0	0
T55	0	22	0	0
T63	0	22	0	0
T99	0	46	0	0
T160	0	46	0	0
T199	0	226	0	0
T202	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T160	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5941585	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5943864	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	50	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T160	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T160	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T160	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T63	0	1	0	0
T99	0	1	0	0
T160	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	8654	0	0
T1	909	40	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	135	0	0
T44	0	137	0	0
T46	0	163	0	0
T55	0	21	0	0
T63	0	21	0	0
T99	0	45	0	0
T160	0	44	0	0
T199	0	222	0	0
T202	0	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	19	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T41	13260	0	0	0
T43	32209	1	0	0
T63	0	1	0	0
T69	493	0	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T89	0	1	0	0
T99	0	1	0	0
T115	0	1	0	0
T187	0	1	0	0
T199	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	1455	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T6,T23,T24
1	1	Covered	T1,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T12,T203,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T11,T12
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T7
DetectSt	168	Covered	T1,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T7
DebounceSt->IdleSt	163	Covered	T84,T205,T206
DetectSt->IdleSt	186	Covered	T12,T203,T90
DetectSt->StableSt	191	Covered	T1,T3,T7
IdleSt->DebounceSt	148	Covered	T1,T3,T7
StableSt->IdleSt	206	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T205,T206,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T12,T203,T90
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	166	0	0
CntIncr_A	6753481	121566	0	0
CntNoWrap_A	6753481	6069657	0	0
DetectStDropOut_A	6753481	5	0	0
DetectedOut_A	6753481	90798	0	0
DetectedPulseOut_A	6753481	75	0	0
DisabledIdleSt_A	6753481	5770631	0	0
DisabledNoDetection_A	6753481	5772901	0	0
EnterDebounceSt_A	6753481	86	0	0
EnterDetectSt_A	6753481	80	0	0
EnterStableSt_A	6753481	75	0	0
PulseIsPulse_A	6753481	75	0	0
StayInStableSt	6753481	90690	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	3174	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	166	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	2	0	0
T7	0	2	0	0
T11	0	4	0	0
T12	0	6	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	121566	0	0
T1	909	61	0	0
T2	23577	0	0	0
T3	644	34	0	0
T7	0	86	0	0
T11	0	30	0	0
T12	0	102	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	91	0	0
T44	0	94	0	0
T45	0	59	0	0
T48	0	68	0	0
T160	0	34059	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069657	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5	0	0
T12	788	1	0	0
T13	3779	0	0	0
T21	806	0	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T48	14380	0	0	0
T52	746	0	0	0
T80	522	0	0	0
T90	0	1	0	0
T169	0	1	0	0
T189	427	0	0	0
T190	426	0	0	0
T191	0	1	0	0
T203	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	90798	0	0
T1	909	223	0	0
T2	23577	0	0	0
T3	644	43	0	0
T7	0	425	0	0
T11	0	66	0	0
T12	0	72	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	144	0	0
T44	0	40	0	0
T45	0	147	0	0
T48	0	50	0	0
T160	0	22871	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	75	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T7	0	1	0	0
T11	0	2	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5770631	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5772901	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	86	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T7	0	1	0	0
T11	0	2	0	0
T12	0	3	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	80	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T7	0	1	0	0
T11	0	2	0	0
T12	0	3	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	75	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T7	0	1	0	0
T11	0	2	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	75	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	1	0	0
T7	0	1	0	0
T11	0	2	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	90690	0	0
T1	909	222	0	0
T2	23577	0	0	0
T3	644	41	0	0
T7	0	423	0	0
T11	0	64	0	0
T12	0	69	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	142	0	0
T44	0	39	0	0
T45	0	145	0	0
T48	0	48	0	0
T160	0	22870	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3174	0	0
T1	909	1	0	0
T3	0	1	0	0
T6	4492	22	0	0
T14	496	6	0	0
T15	0	4	0	0
T22	703	0	0	0
T23	508	6	0	0
T24	915	4	0	0
T25	4217	0	0	0
T26	426	3	0	0
T27	522	4	0	0
T28	691	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	41	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T105	0	1	0	0
T160	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T23
1	1	Covered	T4,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T4,T6,T23
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T11
1	-	Covered	T1,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T99,T209,T89
DetectSt->IdleSt	186	Covered	T92,T93
DetectSt->StableSt	191	Covered	T1,T7,T11
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T1,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T99,T209,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	137	0	0
CntIncr_A	6753481	3605	0	0
CntNoWrap_A	6753481	6069686	0	0
DetectStDropOut_A	6753481	2	0	0
DetectedOut_A	6753481	4405	0	0
DetectedPulseOut_A	6753481	63	0	0
DisabledIdleSt_A	6753481	5845783	0	0
DisabledNoDetection_A	6753481	5848073	0	0
EnterDebounceSt_A	6753481	72	0	0
EnterDetectSt_A	6753481	65	0	0
EnterStableSt_A	6753481	63	0	0
PulseIsPulse_A	6753481	63	0	0
StayInStableSt	6753481	4314	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	137	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	2	0	0
T11	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	6	0	0
T55	0	2	0	0
T63	0	2	0	0
T86	0	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T174	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3605	0	0
T1	909	61	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	86	0	0
T11	0	15	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	243	0	0
T55	0	22	0	0
T63	0	25	0	0
T86	0	62	0	0
T99	0	158	0	0
T105	0	15	0	0
T174	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069686	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2	0	0
T92	908	1	0	0
T93	0	1	0	0
T140	1288	0	0	0
T210	7720	0	0	0
T211	524	0	0	0
T212	592	0	0	0
T213	12713	0	0	0
T214	522	0	0	0
T215	1454	0	0	0
T216	8582	0	0	0
T217	443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4405	0	0
T1	909	103	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	294	0	0
T11	0	111	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	208	0	0
T55	0	24	0	0
T63	0	43	0	0
T86	0	104	0	0
T105	0	42	0	0
T174	0	73	0	0
T199	0	283	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	63	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	3	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T105	0	1	0	0
T174	0	2	0	0
T199	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5845783	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5848073	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	72	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	3	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T99	0	2	0	0
T105	0	1	0	0
T174	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	65	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	3	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T105	0	1	0	0
T174	0	2	0	0
T199	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	63	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	3	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T105	0	1	0	0
T174	0	2	0	0
T199	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	63	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	3	0	0
T55	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0
T105	0	1	0	0
T174	0	2	0	0
T199	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4314	0	0
T1	909	102	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	293	0	0
T11	0	110	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	204	0	0
T55	0	23	0	0
T63	0	41	0	0
T86	0	102	0	0
T105	0	40	0	0
T174	0	70	0	0
T199	0	280	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	34	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T199	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T12,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T4,T6,T23
1	1	Covered	T3,T12,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T43
0	1	Covered	T12,T43,T99
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T43
1	-	Covered	T12,T43,T99

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T43
DetectSt	168	Covered	T3,T12,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T43
DebounceSt->IdleSt	163	Covered	T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T12,T43
IdleSt->DebounceSt	148	Covered	T3,T12,T43
StableSt->IdleSt	206	Covered	T12,T43,T99

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T43
0	1	Covered	T3,T12,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T43,T99
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	69	0	0
CntIncr_A	6753481	10396	0	0
CntNoWrap_A	6753481	6069754	0	0
DetectStDropOut_A	6753481	0	0	0
DetectedOut_A	6753481	2507	0	0
DetectedPulseOut_A	6753481	34	0	0
DisabledIdleSt_A	6753481	5875945	0	0
DisabledNoDetection_A	6753481	5878238	0	0
EnterDebounceSt_A	6753481	35	0	0
EnterDetectSt_A	6753481	34	0	0
EnterStableSt_A	6753481	34	0	0
PulseIsPulse_A	6753481	34	0	0
StayInStableSt	6753481	2457	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6645	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	69	0	0
T3	644	2	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	4	0	0
T44	0	2	0	0
T55	0	2	0	0
T58	435	0	0	0
T99	0	4	0	0
T103	422	0	0	0
T173	0	2	0	0
T177	0	2	0	0
T199	0	4	0	0
T220	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	10396	0	0
T3	644	34	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	34	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	162	0	0
T44	0	94	0	0
T55	0	22	0	0
T58	435	0	0	0
T99	0	158	0	0
T103	422	0	0	0
T173	0	12	0	0
T177	0	19	0	0
T199	0	84	0	0
T220	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069754	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2507	0	0
T3	644	43	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	40	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	14	0	0
T44	0	44	0	0
T55	0	24	0	0
T58	435	0	0	0
T99	0	288	0	0
T103	422	0	0	0
T173	0	114	0	0
T177	0	40	0	0
T199	0	73	0	0
T220	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	34	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T99	0	2	0	0
T103	422	0	0	0
T173	0	1	0	0
T177	0	1	0	0
T199	0	2	0	0
T220	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5875945	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5878238	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	35	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T99	0	2	0	0
T103	422	0	0	0
T173	0	1	0	0
T177	0	1	0	0
T199	0	2	0	0
T220	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	34	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T99	0	2	0	0
T103	422	0	0	0
T173	0	1	0	0
T177	0	1	0	0
T199	0	2	0	0
T220	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	34	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T99	0	2	0	0
T103	422	0	0	0
T173	0	1	0	0
T177	0	1	0	0
T199	0	2	0	0
T220	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	34	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T99	0	2	0	0
T103	422	0	0	0
T173	0	1	0	0
T177	0	1	0	0
T199	0	2	0	0
T220	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2457	0	0
T3	644	41	0	0
T7	921	0	0	0
T8	111396	0	0	0
T12	0	39	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	12	0	0
T44	0	42	0	0
T55	0	23	0	0
T58	435	0	0	0
T99	0	285	0	0
T103	422	0	0	0
T173	0	112	0	0
T177	0	39	0	0
T199	0	71	0	0
T220	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6645	0	0
T1	0	1	0	0
T2	0	27	0	0
T4	1362	4	0	0
T5	685	0	0	0
T6	4492	19	0	0
T14	0	7	0	0
T15	0	5	0	0
T22	703	0	0	0
T23	508	3	0	0
T24	915	0	0	0
T25	4217	27	0	0
T26	426	4	0	0
T27	522	4	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	17	0	0
T12	788	1	0	0
T13	3779	0	0	0
T21	806	0	0	0
T40	14251	0	0	0
T43	32209	2	0	0
T48	14380	0	0	0
T52	746	0	0	0
T80	522	0	0	0
T93	0	1	0	0
T99	0	1	0	0
T177	0	1	0	0
T189	427	0	0	0
T190	426	0	0	0
T199	0	2	0	0
T200	0	2	0	0
T209	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T23,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T23,T25
1	1	Covered	T6,T23,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Covered	T6,T23,T25
1	1	Covered	T7,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T91,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T7,T11,T222
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T11
1	-	Covered	T7,T11,T222

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T11
DetectSt	168	Covered	T7,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T11
DebounceSt->IdleSt	163	Covered	T86,T84,T205
DetectSt->IdleSt	186	Covered	T91,T191
DetectSt->StableSt	191	Covered	T7,T8,T11
IdleSt->DebounceSt	148	Covered	T7,T8,T11
StableSt->IdleSt	206	Covered	T7,T11,T222

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T11
0	1	Covered	T7,T8,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T23,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T86,T205,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T91,T191
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T222
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	124	0	0
CntIncr_A	6753481	102395	0	0
CntNoWrap_A	6753481	6069699	0	0
DetectStDropOut_A	6753481	2	0	0
DetectedOut_A	6753481	66769	0	0
DetectedPulseOut_A	6753481	58	0	0
DisabledIdleSt_A	6753481	5827062	0	0
DisabledNoDetection_A	6753481	5829348	0	0
EnterDebounceSt_A	6753481	64	0	0
EnterDetectSt_A	6753481	60	0	0
EnterStableSt_A	6753481	58	0	0
PulseIsPulse_A	6753481	58	0	0
StayInStableSt	6753481	66681	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	124	0	0
T7	921	4	0	0
T8	111396	2	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	4	0	0
T42	0	2	0	0
T55	0	2	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T91	0	2	0	0
T103	422	0	0	0
T105	0	2	0	0
T174	0	2	0	0
T202	0	2	0	0
T222	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	102395	0	0
T7	921	172	0	0
T8	111396	46396	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	30	0	0
T42	0	91	0	0
T55	0	22	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T91	0	79	0	0
T103	422	0	0	0
T105	0	15	0	0
T174	0	34	0	0
T202	0	38	0	0
T222	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069699	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2	0	0
T86	576	0	0	0
T91	611	1	0	0
T108	5566	0	0	0
T136	2282	0	0	0
T191	0	1	0	0
T192	425	0	0	0
T193	527	0	0	0
T194	522	0	0	0
T224	524	0	0	0
T225	406	0	0	0
T226	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	66769	0	0
T7	921	113	0	0
T8	111396	46	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	155	0	0
T42	0	145	0	0
T55	0	23	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T103	422	0	0	0
T105	0	6	0	0
T174	0	247	0	0
T199	0	144	0	0
T202	0	136	0	0
T222	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	58	0	0
T7	921	2	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T103	422	0	0	0
T105	0	1	0	0
T174	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T222	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5827062	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5829348	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	64	0	0
T7	921	2	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T91	0	1	0	0
T103	422	0	0	0
T105	0	1	0	0
T174	0	1	0	0
T202	0	1	0	0
T222	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	60	0	0
T7	921	2	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T91	0	1	0	0
T103	422	0	0	0
T105	0	1	0	0
T174	0	1	0	0
T202	0	1	0	0
T222	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	58	0	0
T7	921	2	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T103	422	0	0	0
T105	0	1	0	0
T174	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T222	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	58	0	0
T7	921	2	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T103	422	0	0	0
T105	0	1	0	0
T174	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T222	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	66681	0	0
T7	921	110	0	0
T8	111396	44	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	152	0	0
T42	0	143	0	0
T55	0	22	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T103	422	0	0	0
T105	0	5	0	0
T174	0	245	0	0
T199	0	143	0	0
T202	0	135	0	0
T222	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	27	0	0
T7	921	1	0	0
T8	111396	0	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T11	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T103	422	0	0	0
T105	0	1	0	0
T170	0	1	0	0
T177	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T220	0	1	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T23,T25
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T6,T23,T25
1	1	Covered	T1,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T43
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T1,T11,T43
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T12
1	-	Covered	T1,T11,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T12
DetectSt	168	Covered	T1,T11,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T12
DebounceSt->IdleSt	163	Covered	T84,T168
DetectSt->IdleSt	186	Covered	T43
DetectSt->StableSt	191	Covered	T1,T11,T12
IdleSt->DebounceSt	148	Covered	T1,T11,T12
StableSt->IdleSt	206	Covered	T1,T11,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T12
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T43
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	75	0	0
CntIncr_A	6753481	17871	0	0
CntNoWrap_A	6753481	6069748	0	0
DetectStDropOut_A	6753481	1	0	0
DetectedOut_A	6753481	2776	0	0
DetectedPulseOut_A	6753481	36	0	0
DisabledIdleSt_A	6753481	5809663	0	0
DisabledNoDetection_A	6753481	5811954	0	0
EnterDebounceSt_A	6753481	39	0	0
EnterDetectSt_A	6753481	37	0	0
EnterStableSt_A	6753481	36	0	0
PulseIsPulse_A	6753481	36	0	0
StayInStableSt	6753481	2720	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6224	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	75	0	0
T1	909	4	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	4	0	0
T46	0	2	0	0
T55	0	2	0	0
T91	0	2	0	0
T105	0	2	0	0
T199	0	2	0	0
T222	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	17871	0	0
T1	909	122	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	15	0	0
T12	0	34	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	162	0	0
T46	0	95	0	0
T55	0	22	0	0
T91	0	79	0	0
T105	0	15	0	0
T199	0	57	0	0
T222	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069748	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T41	13260	0	0	0
T43	32209	1	0	0
T69	493	0	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T204	1455	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2776	0	0
T1	909	265	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	40	0	0
T12	0	93	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	133	0	0
T46	0	40	0	0
T55	0	22	0	0
T91	0	42	0	0
T105	0	113	0	0
T199	0	198	0	0
T222	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	36	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T91	0	1	0	0
T105	0	1	0	0
T199	0	1	0	0
T222	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5809663	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5811954	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	39	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T55	0	1	0	0
T91	0	1	0	0
T105	0	1	0	0
T199	0	1	0	0
T222	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	37	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T55	0	1	0	0
T91	0	1	0	0
T105	0	1	0	0
T199	0	1	0	0
T222	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	36	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T91	0	1	0	0
T105	0	1	0	0
T199	0	1	0	0
T222	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	36	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T91	0	1	0	0
T105	0	1	0	0
T199	0	1	0	0
T222	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2720	0	0
T1	909	262	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	39	0	0
T12	0	91	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	132	0	0
T46	0	39	0	0
T55	0	21	0	0
T91	0	40	0	0
T105	0	111	0	0
T199	0	196	0	0
T222	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6224	0	0
T1	909	2	0	0
T2	0	30	0	0
T3	0	1	0	0
T6	4492	22	0	0
T14	496	6	0	0
T15	0	6	0	0
T22	703	0	0	0
T23	508	5	0	0
T24	915	0	0	0
T25	4217	22	0	0
T26	426	4	0	0
T27	522	5	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	15	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T11	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T89	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T207	0	2	0	0
T220	0	1	0	0
T221	0	1	0	0