Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T23,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T23,T25
1	1	Covered	T6,T23,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T12
1	0	Covered	T6,T23,T25
1	1	Covered	T3,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T12
0	1	Covered	T227
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T12
0	1	Covered	T3,T7,T43
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T12
1	-	Covered	T3,T7,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T12
DetectSt	168	Covered	T3,T7,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T12
DebounceSt->IdleSt	163	Covered	T3,T99,T86
DetectSt->IdleSt	186	Covered	T227
DetectSt->StableSt	191	Covered	T3,T7,T12
IdleSt->DebounceSt	148	Covered	T3,T7,T12
StableSt->IdleSt	206	Covered	T3,T7,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T12
0	1	Covered	T3,T7,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T23,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T99,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T227
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T43
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	140	0	0
CntIncr_A	6753481	42031	0	0
CntNoWrap_A	6753481	6069683	0	0
DetectStDropOut_A	6753481	1	0	0
DetectedOut_A	6753481	11492	0	0
DetectedPulseOut_A	6753481	66	0	0
DisabledIdleSt_A	6753481	5942156	0	0
DisabledNoDetection_A	6753481	5944438	0	0
EnterDebounceSt_A	6753481	73	0	0
EnterDetectSt_A	6753481	67	0	0
EnterStableSt_A	6753481	66	0	0
PulseIsPulse_A	6753481	66	0	0
StayInStableSt	6753481	11396	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	140	0	0
T3	644	3	0	0
T7	921	2	0	0
T8	111396	0	0	0
T12	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	0	2	0	0
T58	435	0	0	0
T99	0	3	0	0
T103	422	0	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	42031	0	0
T3	644	68	0	0
T7	921	86	0	0
T8	111396	0	0	0
T12	0	34	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	91	0	0
T43	0	81	0	0
T44	0	94	0	0
T45	0	59	0	0
T48	0	68	0	0
T58	435	0	0	0
T99	0	158	0	0
T103	422	0	0	0
T160	0	34059	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069683	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1	0	0
T161	2219	0	0	0
T188	900	0	0	0
T227	15216	1	0	0
T228	445	0	0	0
T229	17542	0	0	0
T230	5129	0	0	0
T231	968	0	0	0
T232	25163	0	0	0
T233	404	0	0	0
T234	551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	11492	0	0
T3	644	25	0	0
T7	921	137	0	0
T8	111396	0	0	0
T12	0	345	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	145	0	0
T43	0	127	0	0
T44	0	5	0	0
T45	0	14	0	0
T48	0	108	0	0
T58	435	0	0	0
T99	0	47	0	0
T103	422	0	0	0
T160	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	66	0	0
T3	644	1	0	0
T7	921	1	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T58	435	0	0	0
T99	0	1	0	0
T103	422	0	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5942156	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5944438	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	73	0	0
T3	644	2	0	0
T7	921	1	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T58	435	0	0	0
T99	0	2	0	0
T103	422	0	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	67	0	0
T3	644	1	0	0
T7	921	1	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T58	435	0	0	0
T99	0	1	0	0
T103	422	0	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	66	0	0
T3	644	1	0	0
T7	921	1	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T58	435	0	0	0
T99	0	1	0	0
T103	422	0	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	66	0	0
T3	644	1	0	0
T7	921	1	0	0
T8	111396	0	0	0
T12	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T58	435	0	0	0
T99	0	1	0	0
T103	422	0	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	11396	0	0
T3	644	24	0	0
T7	921	136	0	0
T8	111396	0	0	0
T12	0	343	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	143	0	0
T43	0	126	0	0
T44	0	4	0	0
T45	0	13	0	0
T48	0	106	0	0
T58	435	0	0	0
T99	0	46	0	0
T103	422	0	0	0
T160	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	35	0	0
T3	644	1	0	0
T7	921	1	0	0
T8	111396	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T58	435	0	0	0
T99	0	1	0	0
T103	422	0	0	0
T105	0	1	0	0
T175	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T23,T25
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T6,T23,T25
1	1	Covered	T11,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T43,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T43,T44
0	1	Covered	T199,T92,T209
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T43,T44
1	-	Covered	T199,T92,T209

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T43,T44
DetectSt	168	Covered	T11,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T43,T44
DebounceSt->IdleSt	163	Covered	T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T43,T44
IdleSt->DebounceSt	148	Covered	T11,T43,T44
StableSt->IdleSt	206	Covered	T43,T55,T199

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T43,T44
0	1	Covered	T11,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T43,T44
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T43,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T55,T199,T92
StableSt	-	-	-	-	-	-	0	Covered	T11,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	59	0	0
CntIncr_A	6753481	1663	0	0
CntNoWrap_A	6753481	6069764	0	0
DetectStDropOut_A	6753481	0	0	0
DetectedOut_A	6753481	2486	0	0
DetectedPulseOut_A	6753481	29	0	0
DisabledIdleSt_A	6753481	5736826	0	0
DisabledNoDetection_A	6753481	5739119	0	0
EnterDebounceSt_A	6753481	30	0	0
EnterDetectSt_A	6753481	29	0	0
EnterStableSt_A	6753481	29	0	0
PulseIsPulse_A	6753481	29	0	0
StayInStableSt	6753481	2439	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6275	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	59	0	0
T11	651	2	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	2	0	0
T92	0	2	0	0
T135	408	0	0	0
T175	0	2	0	0
T189	427	0	0	0
T199	0	4	0	0
T209	0	2	0	0
T220	0	2	0	0
T235	0	2	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1663	0	0
T11	651	15	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	81	0	0
T44	0	94	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	22	0	0
T92	0	81	0	0
T135	408	0	0	0
T175	0	79	0	0
T189	427	0	0	0
T199	0	84	0	0
T209	0	94	0	0
T220	0	20	0	0
T235	0	16	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069764	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2486	0	0
T11	651	70	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	342	0	0
T44	0	274	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	23	0	0
T92	0	1	0	0
T135	408	0	0	0
T175	0	42	0	0
T189	427	0	0	0
T199	0	281	0	0
T209	0	138	0	0
T220	0	65	0	0
T235	0	42	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	29	0	0
T11	651	1	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T135	408	0	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	2	0	0
T209	0	1	0	0
T220	0	1	0	0
T235	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5736826	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5739119	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	30	0	0
T11	651	1	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T135	408	0	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	2	0	0
T209	0	1	0	0
T220	0	1	0	0
T235	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	29	0	0
T11	651	1	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T135	408	0	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	2	0	0
T209	0	1	0	0
T220	0	1	0	0
T235	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	29	0	0
T11	651	1	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T135	408	0	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	2	0	0
T209	0	1	0	0
T220	0	1	0	0
T235	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	29	0	0
T11	651	1	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T135	408	0	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	2	0	0
T209	0	1	0	0
T220	0	1	0	0
T235	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2439	0	0
T11	651	68	0	0
T12	788	0	0	0
T13	3779	0	0	0
T43	0	340	0	0
T44	0	272	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	22	0	0
T135	408	0	0	0
T175	0	40	0	0
T189	427	0	0	0
T199	0	279	0	0
T203	0	101	0	0
T209	0	137	0	0
T220	0	63	0	0
T235	0	40	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6275	0	0
T1	909	0	0	0
T2	0	22	0	0
T3	0	2	0	0
T6	4492	21	0	0
T14	496	9	0	0
T15	0	3	0	0
T16	0	5	0	0
T22	703	0	0	0
T23	508	4	0	0
T24	915	0	0	0
T25	4217	28	0	0
T26	426	3	0	0
T27	522	6	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	10	0	0
T88	1566	0	0	0
T92	0	1	0	0
T111	5168	0	0	0
T137	1185	0	0	0
T148	0	1	0	0
T162	422	0	0	0
T163	2851	0	0	0
T164	2692	0	0	0
T165	665	0	0	0
T166	424	0	0	0
T168	0	1	0	0
T199	52937	2	0	0
T203	0	1	0	0
T209	0	1	0	0
T239	0	2	0	0
T240	0	1	0	0
T241	723	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T23,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T23,T25
1	1	Covered	T6,T23,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T6,T23,T25
1	1	Covered	T1,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T1,T12,T43
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T12
1	-	Covered	T1,T12,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T12
DetectSt	168	Covered	T1,T7,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T12
DebounceSt->IdleSt	163	Covered	T84,T242,T169
DetectSt->IdleSt	186	Covered	T90
DetectSt->StableSt	191	Covered	T1,T7,T12
IdleSt->DebounceSt	148	Covered	T1,T7,T12
StableSt->IdleSt	206	Covered	T1,T12,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T23,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T242,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T90
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	135	0	0
CntIncr_A	6753481	65273	0	0
CntNoWrap_A	6753481	6069688	0	0
DetectStDropOut_A	6753481	1	0	0
DetectedOut_A	6753481	11951	0	0
DetectedPulseOut_A	6753481	65	0	0
DisabledIdleSt_A	6753481	5915975	0	0
DisabledNoDetection_A	6753481	5918260	0	0
EnterDebounceSt_A	6753481	70	0	0
EnterDetectSt_A	6753481	66	0	0
EnterStableSt_A	6753481	65	0	0
PulseIsPulse_A	6753481	65	0	0
StayInStableSt	6753481	11862	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	135	0	0
T1	909	4	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	2	0	0
T12	0	4	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T63	0	2	0	0
T99	0	6	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	65273	0	0
T1	909	122	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	86	0	0
T12	0	68	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	81	0	0
T45	0	59	0	0
T46	0	95	0	0
T48	0	68	0	0
T63	0	25	0	0
T99	0	237	0	0
T173	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069688	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1	0	0
T90	14094	1	0	0
T207	18484	0	0	0
T243	402	0	0	0
T244	505	0	0	0
T245	493	0	0	0
T246	423	0	0	0
T247	13650	0	0	0
T248	15387	0	0	0
T249	848	0	0	0
T250	983	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	11951	0	0
T1	909	253	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	140	0	0
T12	0	235	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	125	0	0
T45	0	73	0	0
T46	0	166	0	0
T48	0	108	0	0
T63	0	202	0	0
T99	0	153	0	0
T173	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	65	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T63	0	1	0	0
T99	0	3	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5915975	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5918260	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	70	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T63	0	1	0	0
T99	0	3	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	66	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T63	0	1	0	0
T99	0	3	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	65	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T63	0	1	0	0
T99	0	3	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	65	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T63	0	1	0	0
T99	0	3	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	11862	0	0
T1	909	250	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	138	0	0
T12	0	232	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	124	0	0
T45	0	71	0	0
T46	0	164	0	0
T48	0	106	0	0
T63	0	200	0	0
T99	0	149	0	0
T173	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	40	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T12	0	1	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T43	0	1	0	0
T99	0	2	0	0
T105	0	1	0	0
T164	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	3	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T23,T25
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T6,T23,T25
1	1	Covered	T3,T11,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T42
0	1	Covered	T3,T11,T174
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T42
1	-	Covered	T3,T11,T174

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T42
DetectSt	168	Covered	T3,T11,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T42
DebounceSt->IdleSt	163	Covered	T84,T148,T115
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T11,T42
IdleSt->DebounceSt	148	Covered	T3,T11,T42
StableSt->IdleSt	206	Covered	T3,T11,T174

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T42
0	1	Covered	T3,T11,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T174
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	91	0	0
CntIncr_A	6753481	6766	0	0
CntNoWrap_A	6753481	6069732	0	0
DetectStDropOut_A	6753481	0	0	0
DetectedOut_A	6753481	4300	0	0
DetectedPulseOut_A	6753481	44	0	0
DisabledIdleSt_A	6753481	5866539	0	0
DisabledNoDetection_A	6753481	5868827	0	0
EnterDebounceSt_A	6753481	47	0	0
EnterDetectSt_A	6753481	44	0	0
EnterStableSt_A	6753481	44	0	0
PulseIsPulse_A	6753481	44	0	0
StayInStableSt	6753481	4230	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6263	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	91	0	0
T3	644	2	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	4	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	2	0	0
T44	0	2	0	0
T55	0	2	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0
T199	0	4	0	0
T202	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6766	0	0
T3	644	34	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	30	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	91	0	0
T44	0	94	0	0
T55	0	22	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	77	0	0
T173	0	12	0	0
T174	0	34	0	0
T199	0	114	0	0
T202	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069732	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4300	0	0
T3	644	27	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	98	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	52	0	0
T44	0	139	0	0
T55	0	23	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	55	0	0
T173	0	115	0	0
T174	0	39	0	0
T199	0	86	0	0
T202	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0
T202	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5866539	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5868827	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	47	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0
T202	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0
T202	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0
T202	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T199	0	2	0	0
T202	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4230	0	0
T3	644	26	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	95	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T42	0	50	0	0
T44	0	137	0	0
T55	0	22	0	0
T58	435	0	0	0
T103	422	0	0	0
T164	0	53	0	0
T173	0	113	0	0
T174	0	38	0	0
T199	0	83	0	0
T202	0	74	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6263	0	0
T1	909	1	0	0
T2	0	30	0	0
T3	0	1	0	0
T6	4492	17	0	0
T14	496	6	0	0
T15	0	5	0	0
T22	703	0	0	0
T23	508	4	0	0
T24	915	0	0	0
T25	4217	23	0	0
T26	426	3	0	0
T27	522	5	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	17	0	0
T3	644	1	0	0
T7	921	0	0	0
T8	111396	0	0	0
T11	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T58	435	0	0	0
T93	0	1	0	0
T103	422	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0
T199	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T12,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T12,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T12,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T12,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T45
0	1	Covered	T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T45
0	1	Covered	T11,T12,T45
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T45
1	-	Covered	T11,T12,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T45
DetectSt	168	Covered	T11,T12,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T12,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T45
DebounceSt->IdleSt	163	Covered	T199,T170,T84
DetectSt->IdleSt	186	Covered	T90
DetectSt->StableSt	191	Covered	T11,T12,T45
IdleSt->DebounceSt	148	Covered	T11,T12,T45
StableSt->IdleSt	206	Covered	T11,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T45
0	1	Covered	T11,T12,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T199,T170,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T45
DetectSt	-	-	-	-	1	-	-	Covered	T90
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	105	0	0
CntIncr_A	6753481	2890	0	0
CntNoWrap_A	6753481	6069718	0	0
DetectStDropOut_A	6753481	1	0	0
DetectedOut_A	6753481	4312	0	0
DetectedPulseOut_A	6753481	48	0	0
DisabledIdleSt_A	6753481	5894900	0	0
DisabledNoDetection_A	6753481	5897200	0	0
EnterDebounceSt_A	6753481	56	0	0
EnterDetectSt_A	6753481	49	0	0
EnterStableSt_A	6753481	48	0	0
PulseIsPulse_A	6753481	48	0	0
StayInStableSt	6753481	4243	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	105	0	0
T11	651	2	0	0
T12	788	4	0	0
T13	3779	0	0	0
T45	0	2	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	2	0	0
T86	0	2	0	0
T135	408	0	0	0
T164	0	2	0	0
T173	0	4	0	0
T175	0	2	0	0
T189	427	0	0	0
T199	0	3	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2890	0	0
T11	651	15	0	0
T12	788	68	0	0
T13	3779	0	0	0
T45	0	59	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	22	0	0
T86	0	62	0	0
T135	408	0	0	0
T164	0	77	0	0
T173	0	24	0	0
T175	0	79	0	0
T189	427	0	0	0
T199	0	54	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069718	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1	0	0
T90	14094	1	0	0
T207	18484	0	0	0
T243	402	0	0	0
T244	505	0	0	0
T245	493	0	0	0
T246	423	0	0	0
T247	13650	0	0	0
T248	15387	0	0	0
T249	848	0	0	0
T250	983	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4312	0	0
T11	651	85	0	0
T12	788	154	0	0
T13	3779	0	0	0
T45	0	14	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	23	0	0
T86	0	42	0	0
T135	408	0	0	0
T164	0	207	0	0
T173	0	80	0	0
T175	0	5	0	0
T189	427	0	0	0
T199	0	39	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	186	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T11	651	1	0	0
T12	788	2	0	0
T13	3779	0	0	0
T45	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T86	0	1	0	0
T135	408	0	0	0
T164	0	1	0	0
T173	0	2	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5894900	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5897200	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	56	0	0
T11	651	1	0	0
T12	788	2	0	0
T13	3779	0	0	0
T45	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T86	0	1	0	0
T135	408	0	0	0
T164	0	1	0	0
T173	0	2	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	2	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	49	0	0
T11	651	1	0	0
T12	788	2	0	0
T13	3779	0	0	0
T45	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T86	0	1	0	0
T135	408	0	0	0
T164	0	1	0	0
T173	0	2	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T11	651	1	0	0
T12	788	2	0	0
T13	3779	0	0	0
T45	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T86	0	1	0	0
T135	408	0	0	0
T164	0	1	0	0
T173	0	2	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	48	0	0
T11	651	1	0	0
T12	788	2	0	0
T13	3779	0	0	0
T45	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	1	0	0
T86	0	1	0	0
T135	408	0	0	0
T164	0	1	0	0
T173	0	2	0	0
T175	0	1	0	0
T189	427	0	0	0
T199	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	4243	0	0
T11	651	84	0	0
T12	788	152	0	0
T13	3779	0	0	0
T45	0	13	0	0
T48	14380	0	0	0
T51	434	0	0	0
T55	0	22	0	0
T86	0	40	0	0
T135	408	0	0	0
T164	0	205	0	0
T173	0	77	0	0
T175	0	4	0	0
T189	427	0	0	0
T199	0	37	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0
T251	0	184	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	26	0	0
T11	651	1	0	0
T12	788	2	0	0
T13	3779	0	0	0
T45	0	1	0	0
T48	14380	0	0	0
T51	434	0	0	0
T89	0	2	0	0
T92	0	1	0	0
T135	408	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T189	427	0	0	0
T209	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T236	422	0	0	0
T237	413	0	0	0
T238	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T7,T12,T173
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T12
1	-	Covered	T7,T12,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T12
DetectSt	168	Covered	T1,T7,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T12
DebounceSt->IdleSt	163	Covered	T84,T131,T148
DetectSt->IdleSt	186	Covered	T169
DetectSt->StableSt	191	Covered	T1,T7,T12
IdleSt->DebounceSt	148	Covered	T1,T7,T12
StableSt->IdleSt	206	Covered	T7,T12,T173

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T131,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T169
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T173
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	75	0	0
CntIncr_A	6753481	1866	0	0
CntNoWrap_A	6753481	6069748	0	0
DetectStDropOut_A	6753481	1	0	0
DetectedOut_A	6753481	3127	0	0
DetectedPulseOut_A	6753481	35	0	0
DisabledIdleSt_A	6753481	5824018	0	0
DisabledNoDetection_A	6753481	5826302	0	0
EnterDebounceSt_A	6753481	39	0	0
EnterDetectSt_A	6753481	36	0	0
EnterStableSt_A	6753481	35	0	0
PulseIsPulse_A	6753481	35	0	0
StayInStableSt	6753481	3074	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6753481	6887	0	0
gen_low_level_sva.LowLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	75	0	0
T1	909	2	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	2	0	0
T12	0	4	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	2	0	0
T92	0	2	0	0
T173	0	2	0	0
T175	0	2	0	0
T199	0	2	0	0
T200	0	4	0	0
T220	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1866	0	0
T1	909	61	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	86	0	0
T12	0	68	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	22	0	0
T92	0	81	0	0
T173	0	12	0	0
T175	0	79	0	0
T199	0	57	0	0
T200	0	96	0	0
T220	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069748	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1	0	0
T157	746	0	0	0
T169	27088	1	0	0
T252	2873	0	0	0
T253	402	0	0	0
T254	15897	0	0	0
T255	1245	0	0	0
T256	402	0	0	0
T257	19611	0	0	0
T258	493	0	0	0
T259	11200	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3127	0	0
T1	909	265	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	10	0	0
T12	0	85	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	22	0	0
T92	0	125	0	0
T173	0	9	0	0
T175	0	317	0	0
T199	0	246	0	0
T200	0	81	0	0
T220	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	35	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T199	0	1	0	0
T200	0	2	0	0
T220	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5824018	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5826302	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	39	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T199	0	1	0	0
T200	0	2	0	0
T220	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	36	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T199	0	1	0	0
T200	0	2	0	0
T220	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	35	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T199	0	1	0	0
T200	0	2	0	0
T220	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	35	0	0
T1	909	1	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	1	0	0
T12	0	2	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	1	0	0
T92	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T199	0	1	0	0
T200	0	2	0	0
T220	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3074	0	0
T1	909	263	0	0
T2	23577	0	0	0
T3	644	0	0	0
T7	0	9	0	0
T12	0	82	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T55	0	21	0	0
T89	0	200	0	0
T92	0	124	0	0
T173	0	8	0	0
T175	0	315	0	0
T199	0	245	0	0
T200	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6887	0	0
T1	0	1	0	0
T4	1362	4	0	0
T5	685	3	0	0
T6	4492	27	0	0
T14	0	8	0	0
T22	703	3	0	0
T23	508	6	0	0
T24	915	0	0	0
T25	4217	23	0	0
T26	426	2	0	0
T27	522	4	0	0
T28	691	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	16	0	0
T7	921	1	0	0
T8	111396	0	0	0
T9	36087	0	0	0
T10	21382	0	0	0
T12	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T89	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T103	422	0	0	0
T170	0	1	0	0
T173	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T220	0	1	0	0