Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T2,T9,T41
1	1	Covered	T25,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T2,T9
0	1	Covered	T25,T50,T47
1	0	Covered	T47,T55,T107

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T41
0	1	Covered	T2,T9,T41
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T41
1	-	Covered	T2,T9,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T2,T9
DetectSt	168	Covered	T25,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T2,T9
DebounceSt->IdleSt	163	Covered	T55,T84,T260
DetectSt->IdleSt	186	Covered	T25,T50,T47
DetectSt->StableSt	191	Covered	T2,T9,T41
IdleSt->DebounceSt	148	Covered	T25,T2,T9
StableSt->IdleSt	206	Covered	T2,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T2,T9
0	1	Covered	T25,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T25,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T84,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T25,T50,T47
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T41
DetectSt	-	-	-	-	0	0	-	Covered	T25,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T41
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	2649	0	0
CntIncr_A	6753481	87618	0	0
CntNoWrap_A	6753481	6067174	0	0
DetectStDropOut_A	6753481	465	0	0
DetectedOut_A	6753481	55945	0	0
DetectedPulseOut_A	6753481	631	0	0
DisabledIdleSt_A	6753481	5658777	0	0
DisabledNoDetection_A	6753481	5660953	0	0
EnterDebounceSt_A	6753481	1331	0	0
EnterDetectSt_A	6753481	1318	0	0
EnterStableSt_A	6753481	631	0	0
PulseIsPulse_A	6753481	631	0	0
StayInStableSt	6753481	55237	0	0
gen_high_event_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	553	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2649	0	0
T1	909	0	0	0
T2	23577	4	0	0
T3	644	0	0	0
T9	0	18	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	14	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	24	0	0
T47	0	56	0	0
T49	0	6	0	0
T50	0	18	0	0
T75	0	16	0	0
T76	0	20	0	0
T77	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	87618	0	0
T1	909	0	0	0
T2	23577	156	0	0
T3	644	0	0	0
T9	0	1575	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	218	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	876	0	0
T47	0	1548	0	0
T49	0	282	0	0
T50	0	500	0	0
T75	0	600	0	0
T76	0	480	0	0
T77	0	644	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6067174	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3802	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	465	0	0
T1	909	0	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	7	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T47	0	19	0	0
T50	0	9	0	0
T55	0	1	0	0
T106	0	25	0	0
T107	0	10	0	0
T108	0	30	0	0
T109	0	9	0	0
T111	0	22	0	0
T261	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	55945	0	0
T2	23577	15	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	1040	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	1142	0	0
T49	0	73	0	0
T55	0	432	0	0
T58	435	0	0	0
T75	0	357	0	0
T76	0	1746	0	0
T77	0	424	0	0
T262	0	756	0	0
T263	0	4724	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	631	0	0
T2	23577	2	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	12	0	0
T49	0	3	0	0
T55	0	5	0	0
T58	435	0	0	0
T75	0	8	0	0
T76	0	10	0	0
T77	0	14	0	0
T262	0	14	0	0
T263	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5658777	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	2014	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5660953	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	2014	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1331	0	0
T1	909	0	0	0
T2	23577	2	0	0
T3	644	0	0	0
T9	0	9	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	7	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	12	0	0
T47	0	28	0	0
T49	0	3	0	0
T50	0	9	0	0
T75	0	8	0	0
T76	0	10	0	0
T77	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1318	0	0
T1	909	0	0	0
T2	23577	2	0	0
T3	644	0	0	0
T9	0	9	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	7	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	12	0	0
T47	0	28	0	0
T49	0	3	0	0
T50	0	9	0	0
T75	0	8	0	0
T76	0	10	0	0
T77	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	631	0	0
T2	23577	2	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	12	0	0
T49	0	3	0	0
T55	0	5	0	0
T58	435	0	0	0
T75	0	8	0	0
T76	0	10	0	0
T77	0	14	0	0
T262	0	14	0	0
T263	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	631	0	0
T2	23577	2	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	12	0	0
T49	0	3	0	0
T55	0	5	0	0
T58	435	0	0	0
T75	0	8	0	0
T76	0	10	0	0
T77	0	14	0	0
T262	0	14	0	0
T263	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	55237	0	0
T2	23577	13	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	1030	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	1130	0	0
T49	0	70	0	0
T55	0	427	0	0
T58	435	0	0	0
T75	0	349	0	0
T76	0	1736	0	0
T77	0	410	0	0
T262	0	739	0	0
T263	0	4700	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	553	0	0
T2	23577	2	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	8	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	12	0	0
T49	0	3	0	0
T55	0	4	0	0
T58	435	0	0	0
T75	0	8	0	0
T76	0	10	0	0
T77	0	14	0	0
T262	0	11	0	0
T263	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T10,T51

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T13,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T6,T25,T2
1	1	Covered	T8,T10,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T48
0	1	Covered	T104,T105,T55
1	0	Covered	T55,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T48
0	1	Covered	T10,T13,T48
1	0	Covered	T76,T55,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T13,T48
1	-	Covered	T10,T13,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T51
DetectSt	168	Covered	T10,T13,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T13,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T13,T48
DebounceSt->IdleSt	163	Covered	T8,T10,T51
DetectSt->IdleSt	186	Covered	T104,T105,T55
DetectSt->StableSt	191	Covered	T10,T13,T48
IdleSt->DebounceSt	148	Covered	T8,T10,T51
StableSt->IdleSt	206	Covered	T10,T13,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T51
0	1	Covered	T8,T10,T51
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T51
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T13,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T51
DetectSt	-	-	-	-	1	-	-	Covered	T104,T105,T55
DetectSt	-	-	-	-	0	1	-	Covered	T10,T13,T48
DetectSt	-	-	-	-	0	0	-	Covered	T10,T13,T48
StableSt	-	-	-	-	-	-	1	Covered	T10,T13,T48
StableSt	-	-	-	-	-	-	0	Covered	T10,T13,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	780	0	0
CntIncr_A	6753481	34594	0	0
CntNoWrap_A	6753481	6069043	0	0
DetectStDropOut_A	6753481	38	0	0
DetectedOut_A	6753481	13403	0	0
DetectedPulseOut_A	6753481	312	0	0
DisabledIdleSt_A	6753481	5729190	0	0
DisabledNoDetection_A	6753481	5730863	0	0
EnterDebounceSt_A	6753481	429	0	0
EnterDetectSt_A	6753481	353	0	0
EnterStableSt_A	6753481	312	0	0
PulseIsPulse_A	6753481	312	0	0
StayInStableSt	6753481	13076	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	290	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	780	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	3	0	0
T13	0	2	0	0
T33	0	2	0	0
T38	0	16	0	0
T40	0	5	0	0
T43	0	23	0	0
T48	0	4	0	0
T51	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T101	0	1	0	0
T103	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	34594	0	0
T8	111396	20	0	0
T9	36087	0	0	0
T10	21382	228	0	0
T13	0	25	0	0
T33	0	49	0	0
T38	0	776	0	0
T40	0	216	0	0
T43	0	1490	0	0
T48	0	144	0	0
T51	0	20	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T101	0	20	0	0
T103	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069043	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	38	0	0
T39	39070	0	0	0
T44	877	0	0	0
T54	755	0	0	0
T55	0	1	0	0
T104	27089	3	0	0
T105	0	4	0	0
T110	0	3	0	0
T113	0	5	0	0
T114	0	6	0	0
T115	0	7	0	0
T116	0	3	0	0
T118	0	2	0	0
T119	0	2	0	0
T120	502	0	0	0
T121	441	0	0	0
T122	422	0	0	0
T123	404	0	0	0
T124	422	0	0	0
T125	494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	13403	0	0
T10	21382	39	0	0
T11	651	0	0	0
T13	0	3	0	0
T33	0	35	0	0
T38	0	168	0	0
T39	0	208	0	0
T40	0	75	0	0
T43	0	761	0	0
T48	0	19	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	150	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T133	0	20	0	0
T134	425	0	0	0
T135	408	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	312	0	0
T10	21382	1	0	0
T11	651	0	0	0
T13	0	1	0	0
T33	0	1	0	0
T38	0	8	0	0
T39	0	3	0	0
T40	0	2	0	0
T43	0	11	0	0
T48	0	2	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	4	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T133	0	2	0	0
T134	425	0	0	0
T135	408	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5729190	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5730863	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	429	0	0
T8	111396	1	0	0
T9	36087	0	0	0
T10	21382	2	0	0
T13	0	1	0	0
T33	0	1	0	0
T38	0	8	0	0
T40	0	3	0	0
T43	0	12	0	0
T48	0	2	0	0
T51	0	1	0	0
T58	435	0	0	0
T59	536	0	0	0
T67	492	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T101	0	1	0	0
T103	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	353	0	0
T10	21382	1	0	0
T11	651	0	0	0
T13	0	1	0	0
T33	0	1	0	0
T38	0	8	0	0
T40	0	2	0	0
T43	0	11	0	0
T48	0	2	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	4	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	3	0	0
T133	0	2	0	0
T134	425	0	0	0
T135	408	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	312	0	0
T10	21382	1	0	0
T11	651	0	0	0
T13	0	1	0	0
T33	0	1	0	0
T38	0	8	0	0
T39	0	3	0	0
T40	0	2	0	0
T43	0	11	0	0
T48	0	2	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	4	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T133	0	2	0	0
T134	425	0	0	0
T135	408	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	312	0	0
T10	21382	1	0	0
T11	651	0	0	0
T13	0	1	0	0
T33	0	1	0	0
T38	0	8	0	0
T39	0	3	0	0
T40	0	2	0	0
T43	0	11	0	0
T48	0	2	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	4	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T133	0	2	0	0
T134	425	0	0	0
T135	408	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	13076	0	0
T10	21382	38	0	0
T11	651	0	0	0
T13	0	2	0	0
T33	0	34	0	0
T38	0	160	0	0
T39	0	205	0	0
T40	0	73	0	0
T43	0	750	0	0
T48	0	17	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	146	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T133	0	18	0	0
T134	425	0	0	0
T135	408	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	290	0	0
T10	21382	1	0	0
T11	651	0	0	0
T13	0	1	0	0
T33	0	1	0	0
T38	0	8	0	0
T39	0	3	0	0
T40	0	2	0	0
T43	0	11	0	0
T48	0	2	0	0
T50	5416	0	0	0
T51	434	0	0	0
T57	0	4	0	0
T59	536	0	0	0
T60	1008	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T133	0	2	0	0
T134	425	0	0	0
T135	408	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T2,T9,T41
1	1	Covered	T25,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T2,T9
0	1	Covered	T25,T50,T55
1	0	Covered	T41,T55,T107

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T47
0	1	Covered	T2,T9,T47
1	0	Covered	T55,T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T47
1	-	Covered	T2,T9,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T2,T9
DetectSt	168	Covered	T25,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T2,T9
DebounceSt->IdleSt	163	Covered	T55,T84,T260
DetectSt->IdleSt	186	Covered	T25,T50,T41
DetectSt->StableSt	191	Covered	T2,T9,T47
IdleSt->DebounceSt	148	Covered	T25,T2,T9
StableSt->IdleSt	206	Covered	T2,T9,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T2,T9
0	1	Covered	T25,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T25,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T84,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T25,T50,T41
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T47
DetectSt	-	-	-	-	0	0	-	Covered	T25,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T47
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	2673	0	0
CntIncr_A	6753481	81902	0	0
CntNoWrap_A	6753481	6067150	0	0
DetectStDropOut_A	6753481	411	0	0
DetectedOut_A	6753481	60442	0	0
DetectedPulseOut_A	6753481	715	0	0
DisabledIdleSt_A	6753481	5652644	0	0
DisabledNoDetection_A	6753481	5654826	0	0
EnterDebounceSt_A	6753481	1343	0	0
EnterDetectSt_A	6753481	1330	0	0
EnterStableSt_A	6753481	715	0	0
PulseIsPulse_A	6753481	715	0	0
StayInStableSt	6753481	59656	0	0
gen_high_event_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	642	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	2673	0	0
T1	909	0	0	0
T2	23577	18	0	0
T3	644	0	0	0
T9	0	18	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	12	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	2	0	0
T47	0	22	0	0
T49	0	54	0	0
T50	0	8	0	0
T75	0	52	0	0
T76	0	2	0	0
T77	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	81902	0	0
T1	909	0	0	0
T2	23577	729	0	0
T3	644	0	0	0
T9	0	1350	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	186	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	104	0	0
T47	0	473	0	0
T49	0	1701	0	0
T50	0	220	0	0
T75	0	1430	0	0
T76	0	54	0	0
T77	0	552	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6067150	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3804	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	411	0	0
T1	909	0	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	6	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T50	0	4	0	0
T55	0	1	0	0
T84	0	1	0	0
T85	0	5	0	0
T106	0	8	0	0
T108	0	18	0	0
T111	0	22	0	0
T264	0	21	0	0
T265	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	60442	0	0
T2	23577	1567	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	1265	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T47	0	785	0	0
T49	0	2505	0	0
T55	0	497	0	0
T58	435	0	0	0
T75	0	2035	0	0
T76	0	27	0	0
T77	0	365	0	0
T262	0	1212	0	0
T263	0	2179	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	715	0	0
T2	23577	9	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T47	0	11	0	0
T49	0	27	0	0
T55	0	5	0	0
T58	435	0	0	0
T75	0	26	0	0
T76	0	1	0	0
T77	0	12	0	0
T262	0	20	0	0
T263	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5652644	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	2014	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5654826	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	2014	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1343	0	0
T1	909	0	0	0
T2	23577	9	0	0
T3	644	0	0	0
T9	0	9	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	6	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	1	0	0
T47	0	11	0	0
T49	0	27	0	0
T50	0	4	0	0
T75	0	26	0	0
T76	0	1	0	0
T77	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1330	0	0
T1	909	0	0	0
T2	23577	9	0	0
T3	644	0	0	0
T9	0	9	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	6	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	1	0	0
T47	0	11	0	0
T49	0	27	0	0
T50	0	4	0	0
T75	0	26	0	0
T76	0	1	0	0
T77	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	715	0	0
T2	23577	9	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T47	0	11	0	0
T49	0	27	0	0
T55	0	5	0	0
T58	435	0	0	0
T75	0	26	0	0
T76	0	1	0	0
T77	0	12	0	0
T262	0	20	0	0
T263	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	715	0	0
T2	23577	9	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T47	0	11	0	0
T49	0	27	0	0
T55	0	5	0	0
T58	435	0	0	0
T75	0	26	0	0
T76	0	1	0	0
T77	0	12	0	0
T262	0	20	0	0
T263	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	59656	0	0
T2	23577	1553	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	1255	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T47	0	772	0	0
T49	0	2478	0	0
T55	0	492	0	0
T58	435	0	0	0
T75	0	2009	0	0
T76	0	26	0	0
T77	0	353	0	0
T262	0	1189	0	0
T263	0	2167	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	642	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	8	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T47	0	9	0	0
T49	0	27	0	0
T55	0	4	0	0
T58	435	0	0	0
T75	0	26	0	0
T76	0	1	0	0
T77	0	12	0	0
T262	0	17	0	0
T263	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T10,T48

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T6,T25,T2
1	1	Covered	T2,T10,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T48
0	1	Covered	T40,T133,T266
1	0	Covered	T55,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T48
0	1	Covered	T2,T10,T48
1	0	Covered	T55,T261,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T48
1	-	Covered	T2,T10,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T48
DetectSt	168	Covered	T2,T10,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T10,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T48
DebounceSt->IdleSt	163	Covered	T10,T43,T33
DetectSt->IdleSt	186	Covered	T40,T133,T55
DetectSt->StableSt	191	Covered	T2,T10,T48
IdleSt->DebounceSt	148	Covered	T2,T10,T48
StableSt->IdleSt	206	Covered	T2,T10,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T48
0	1	Covered	T2,T10,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T43,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T48
DetectSt	-	-	-	-	1	-	-	Covered	T40,T133,T55
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T48
DetectSt	-	-	-	-	0	0	-	Covered	T2,T10,T48
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	780	0	0
CntIncr_A	6753481	43872	0	0
CntNoWrap_A	6753481	6069043	0	0
DetectStDropOut_A	6753481	78	0	0
DetectedOut_A	6753481	12958	0	0
DetectedPulseOut_A	6753481	285	0	0
DisabledIdleSt_A	6753481	5717342	0	0
DisabledNoDetection_A	6753481	5719084	0	0
EnterDebounceSt_A	6753481	413	0	0
EnterDetectSt_A	6753481	368	0	0
EnterStableSt_A	6753481	285	0	0
PulseIsPulse_A	6753481	285	0	0
StayInStableSt	6753481	12659	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	264	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	780	0	0
T2	23577	10	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	16	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	7	0	0
T38	0	2	0	0
T40	0	12	0	0
T43	0	5	0	0
T47	0	4	0	0
T48	0	6	0	0
T58	435	0	0	0
T104	0	11	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	43872	0	0
T2	23577	330	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	1368	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	343	0	0
T38	0	104	0	0
T40	0	747	0	0
T43	0	280	0	0
T47	0	78	0	0
T48	0	213	0	0
T58	435	0	0	0
T104	0	828	0	0
T133	0	141	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069043	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	78	0	0
T33	30342	0	0	0
T38	22180	0	0	0
T40	14251	6	0	0
T41	13260	0	0	0
T43	32209	0	0	0
T69	493	0	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T83	402	0	0	0
T114	0	11	0	0
T133	0	1	0	0
T153	0	10	0	0
T266	0	3	0	0
T267	0	4	0	0
T268	0	8	0	0
T269	0	4	0	0
T270	0	6	0	0
T271	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	12958	0	0
T2	23577	411	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	58	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	26	0	0
T38	0	13	0	0
T39	0	204	0	0
T43	0	194	0	0
T47	0	164	0	0
T48	0	26	0	0
T58	435	0	0	0
T75	0	96	0	0
T104	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	285	0	0
T2	23577	5	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	7	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	12	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	3	0	0
T58	435	0	0	0
T75	0	1	0	0
T104	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5717342	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5719084	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	413	0	0
T2	23577	5	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	9	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	4	0	0
T38	0	1	0	0
T40	0	6	0	0
T43	0	3	0	0
T47	0	2	0	0
T48	0	3	0	0
T58	435	0	0	0
T104	0	7	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	368	0	0
T2	23577	5	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	7	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T40	0	6	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	3	0	0
T58	435	0	0	0
T104	0	4	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	285	0	0
T2	23577	5	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	7	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	12	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	3	0	0
T58	435	0	0	0
T75	0	1	0	0
T104	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	285	0	0
T2	23577	5	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	7	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	12	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	3	0	0
T58	435	0	0	0
T75	0	1	0	0
T104	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	12659	0	0
T2	23577	403	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	51	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	23	0	0
T38	0	12	0	0
T39	0	192	0	0
T43	0	192	0	0
T47	0	160	0	0
T48	0	22	0	0
T58	435	0	0	0
T75	0	95	0	0
T104	0	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	264	0	0
T2	23577	2	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	7	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	12	0	0
T43	0	2	0	0
T48	0	2	0	0
T58	435	0	0	0
T63	0	2	0	0
T75	0	1	0	0
T104	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T2,T9,T41
1	1	Covered	T25,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T2,T9
0	1	Covered	T25,T50,T75
1	0	Covered	T75,T55,T272

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T41
0	1	Covered	T2,T9,T41
1	0	Covered	T55,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T41
1	-	Covered	T2,T9,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T2,T9
DetectSt	168	Covered	T25,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T2,T9
DebounceSt->IdleSt	163	Covered	T55,T84,T260
DetectSt->IdleSt	186	Covered	T25,T50,T75
DetectSt->StableSt	191	Covered	T2,T9,T41
IdleSt->DebounceSt	148	Covered	T25,T2,T9
StableSt->IdleSt	206	Covered	T2,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T2,T9
0	1	Covered	T25,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T25,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T84,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T25,T50,T75
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T41
DetectSt	-	-	-	-	0	0	-	Covered	T25,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T41
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	3375	0	0
CntIncr_A	6753481	107546	0	0
CntNoWrap_A	6753481	6066448	0	0
DetectStDropOut_A	6753481	566	0	0
DetectedOut_A	6753481	81419	0	0
DetectedPulseOut_A	6753481	940	0	0
DisabledIdleSt_A	6753481	5635983	0	0
DisabledNoDetection_A	6753481	5638121	0	0
EnterDebounceSt_A	6753481	1697	0	0
EnterDetectSt_A	6753481	1678	0	0
EnterStableSt_A	6753481	940	0	0
PulseIsPulse_A	6753481	940	0	0
StayInStableSt	6753481	80364	0	0
gen_high_event_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	823	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3375	0	0
T1	909	0	0	0
T2	23577	18	0	0
T3	644	0	0	0
T9	0	56	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	54	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	14	0	0
T47	0	18	0	0
T49	0	14	0	0
T50	0	42	0	0
T75	0	52	0	0
T76	0	62	0	0
T77	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	107546	0	0
T1	909	0	0	0
T2	23577	513	0	0
T3	644	0	0	0
T9	0	5012	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	865	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	448	0	0
T47	0	450	0	0
T49	0	588	0	0
T50	0	1166	0	0
T75	0	2073	0	0
T76	0	1984	0	0
T77	0	682	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6066448	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3762	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	566	0	0
T1	909	0	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	27	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T50	0	21	0	0
T55	0	1	0	0
T75	0	8	0	0
T106	0	22	0	0
T108	0	26	0	0
T111	0	8	0	0
T264	0	14	0	0
T265	0	22	0	0
T272	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	81419	0	0
T2	23577	1953	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	6472	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	415	0	0
T47	0	1193	0	0
T49	0	343	0	0
T55	0	424	0	0
T58	435	0	0	0
T76	0	1964	0	0
T77	0	160	0	0
T262	0	1032	0	0
T263	0	3089	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	940	0	0
T2	23577	9	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	28	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	7	0	0
T47	0	9	0	0
T49	0	7	0	0
T55	0	5	0	0
T58	435	0	0	0
T76	0	31	0	0
T77	0	11	0	0
T262	0	20	0	0
T263	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5635983	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	2014	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5638121	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	2014	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1697	0	0
T1	909	0	0	0
T2	23577	9	0	0
T3	644	0	0	0
T9	0	28	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	27	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	7	0	0
T47	0	9	0	0
T49	0	7	0	0
T50	0	21	0	0
T75	0	26	0	0
T76	0	31	0	0
T77	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1678	0	0
T1	909	0	0	0
T2	23577	9	0	0
T3	644	0	0	0
T9	0	28	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	27	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	7	0	0
T47	0	9	0	0
T49	0	7	0	0
T50	0	21	0	0
T75	0	26	0	0
T76	0	31	0	0
T77	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	940	0	0
T2	23577	9	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	28	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	7	0	0
T47	0	9	0	0
T49	0	7	0	0
T55	0	5	0	0
T58	435	0	0	0
T76	0	31	0	0
T77	0	11	0	0
T262	0	20	0	0
T263	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	940	0	0
T2	23577	9	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	28	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	7	0	0
T47	0	9	0	0
T49	0	7	0	0
T55	0	5	0	0
T58	435	0	0	0
T76	0	31	0	0
T77	0	11	0	0
T262	0	20	0	0
T263	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	80364	0	0
T2	23577	1940	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	6436	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	407	0	0
T47	0	1183	0	0
T49	0	336	0	0
T55	0	419	0	0
T58	435	0	0	0
T76	0	1933	0	0
T77	0	149	0	0
T262	0	1009	0	0
T263	0	3080	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	823	0	0
T2	23577	5	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	20	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T41	0	6	0	0
T47	0	8	0	0
T49	0	7	0	0
T55	0	4	0	0
T58	435	0	0	0
T76	0	31	0	0
T77	0	11	0	0
T262	0	17	0	0
T263	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T6,T25,T2
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T48,T33,T38
1	0	Covered	T55,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T2,T10,T40
1	0	Covered	T55,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T2,T10,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T48,T40,T33
DetectSt->IdleSt	186	Covered	T48,T33,T38
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T40,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T48,T33,T38
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	894	0	0
CntIncr_A	6753481	47373	0	0
CntNoWrap_A	6753481	6068929	0	0
DetectStDropOut_A	6753481	68	0	0
DetectedOut_A	6753481	16476	0	0
DetectedPulseOut_A	6753481	355	0	0
DisabledIdleSt_A	6753481	5693733	0	0
DisabledNoDetection_A	6753481	5695414	0	0
EnterDebounceSt_A	6753481	468	0	0
EnterDetectSt_A	6753481	428	0	0
EnterStableSt_A	6753481	355	0	0
PulseIsPulse_A	6753481	355	0	0
StayInStableSt	6753481	16076	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	307	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	894	0	0
T2	23577	8	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	14	0	0
T10	0	2	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	21	0	0
T38	0	6	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	22	0	0
T58	435	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	47373	0	0
T2	23577	372	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	1211	0	0
T10	0	161	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	953	0	0
T38	0	352	0	0
T40	0	270	0	0
T41	0	78	0	0
T43	0	172	0	0
T47	0	49	0	0
T48	0	914	0	0
T58	435	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6068929	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	68	0	0
T21	806	0	0	0
T33	30342	10	0	0
T38	0	3	0	0
T40	14251	0	0	0
T43	32209	0	0	0
T48	14380	10	0	0
T52	746	0	0	0
T63	0	2	0	0
T80	522	0	0	0
T81	445	0	0	0
T82	532	0	0	0
T84	0	1	0	0
T105	0	1	0	0
T133	0	1	0	0
T190	426	0	0	0
T273	0	2	0	0
T274	0	6	0	0
T275	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	16476	0	0
T2	23577	222	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	348	0	0
T10	0	17	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T39	0	76	0	0
T40	0	20	0	0
T41	0	25	0	0
T43	0	24	0	0
T47	0	71	0	0
T57	0	156	0	0
T58	435	0	0	0
T104	0	515	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	355	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T39	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T57	0	3	0	0
T58	435	0	0	0
T104	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5693733	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5695414	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	468	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	11	0	0
T38	0	3	0	0
T40	0	3	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	12	0	0
T58	435	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	428	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T33	0	10	0	0
T38	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	11	0	0
T58	435	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	355	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T39	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T57	0	3	0	0
T58	435	0	0	0
T104	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	355	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T39	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T57	0	3	0	0
T58	435	0	0	0
T104	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	16076	0	0
T2	23577	218	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T9	0	334	0	0
T10	0	16	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T39	0	73	0	0
T40	0	18	0	0
T41	0	24	0	0
T43	0	23	0	0
T47	0	69	0	0
T57	0	153	0	0
T58	435	0	0	0
T104	0	505	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	307	0	0
T2	23577	4	0	0
T3	644	0	0	0
T7	921	0	0	0
T8	111396	0	0	0
T10	0	1	0	0
T16	507	0	0	0
T17	507	0	0	0
T18	505	0	0	0
T19	493	0	0	0
T20	39361	0	0	0
T39	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T57	0	3	0	0
T58	435	0	0	0
T76	0	4	0	0
T104	0	10	0	0
T276	0	4	0	0