Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T2,T9,T41
1	1	Covered	T25,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T2,T9
0	1	Covered	T25,T50,T47
1	0	Covered	T2,T47,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T41,T49
0	1	Covered	T9,T41,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T41,T49
1	-	Covered	T9,T41,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T2,T9
DetectSt	168	Covered	T25,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T41,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T2,T9
DebounceSt->IdleSt	163	Covered	T55,T84,T260
DetectSt->IdleSt	186	Covered	T25,T2,T50
DetectSt->StableSt	191	Covered	T9,T41,T49
IdleSt->DebounceSt	148	Covered	T25,T2,T9
StableSt->IdleSt	206	Covered	T9,T41,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T2,T9
0	1	Covered	T25,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T25,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T84,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T25,T2,T50
DetectSt	-	-	-	-	0	1	-	Covered	T9,T41,T49
DetectSt	-	-	-	-	0	0	-	Covered	T25,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T9,T41,T49
StableSt	-	-	-	-	-	-	0	Covered	T9,T41,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	3076	0	0
CntIncr_A	6753481	99892	0	0
CntNoWrap_A	6753481	6066747	0	0
DetectStDropOut_A	6753481	513	0	0
DetectedOut_A	6753481	78251	0	0
DetectedPulseOut_A	6753481	844	0	0
DisabledIdleSt_A	6753481	5641875	0	0
DisabledNoDetection_A	6753481	5644025	0	0
EnterDebounceSt_A	6753481	1547	0	0
EnterDetectSt_A	6753481	1529	0	0
EnterStableSt_A	6753481	844	0	0
PulseIsPulse_A	6753481	844	0	0
StayInStableSt	6753481	77304	0	0
gen_high_event_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	741	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	3076	0	0
T1	909	0	0	0
T2	23577	10	0	0
T3	644	0	0	0
T9	0	46	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	16	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	46	0	0
T47	0	34	0	0
T49	0	28	0	0
T50	0	46	0	0
T75	0	24	0	0
T76	0	30	0	0
T77	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	99892	0	0
T1	909	0	0	0
T2	23577	418	0	0
T3	644	0	0	0
T9	0	4094	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	250	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	1288	0	0
T47	0	936	0	0
T49	0	1190	0	0
T50	0	1287	0	0
T75	0	961	0	0
T76	0	1193	0	0
T77	0	1736	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6066747	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3800	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	513	0	0
T1	909	0	0	0
T2	23577	0	0	0
T3	644	0	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	8	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T47	0	10	0	0
T50	0	23	0	0
T55	0	1	0	0
T76	0	6	0	0
T85	0	18	0	0
T106	0	22	0	0
T108	0	26	0	0
T109	0	5	0	0
T111	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	78251	0	0
T9	36087	3132	0	0
T10	21382	0	0	0
T41	0	1714	0	0
T49	0	1458	0	0
T50	5416	0	0	0
T55	0	429	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T77	0	1720	0	0
T107	0	642	0	0
T134	425	0	0	0
T262	0	2326	0	0
T263	0	6749	0	0
T277	0	882	0	0
T278	0	1343	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	844	0	0
T9	36087	23	0	0
T10	21382	0	0	0
T41	0	23	0	0
T49	0	14	0	0
T50	5416	0	0	0
T55	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T77	0	28	0	0
T107	0	8	0	0
T134	425	0	0	0
T262	0	20	0	0
T263	0	25	0	0
T277	0	14	0	0
T278	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5641875	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	2014	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5644025	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	2014	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1547	0	0
T1	909	0	0	0
T2	23577	5	0	0
T3	644	0	0	0
T9	0	23	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	8	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	23	0	0
T47	0	17	0	0
T49	0	14	0	0
T50	0	23	0	0
T75	0	12	0	0
T76	0	15	0	0
T77	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	1529	0	0
T1	909	0	0	0
T2	23577	5	0	0
T3	644	0	0	0
T9	0	23	0	0
T14	496	0	0	0
T15	523	0	0	0
T16	507	0	0	0
T25	4217	8	0	0
T26	426	0	0	0
T27	522	0	0	0
T28	691	0	0	0
T41	0	23	0	0
T47	0	17	0	0
T49	0	14	0	0
T50	0	23	0	0
T75	0	12	0	0
T76	0	15	0	0
T77	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	844	0	0
T9	36087	23	0	0
T10	21382	0	0	0
T41	0	23	0	0
T49	0	14	0	0
T50	5416	0	0	0
T55	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T77	0	28	0	0
T107	0	8	0	0
T134	425	0	0	0
T262	0	20	0	0
T263	0	25	0	0
T277	0	14	0	0
T278	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	844	0	0
T9	36087	23	0	0
T10	21382	0	0	0
T41	0	23	0	0
T49	0	14	0	0
T50	5416	0	0	0
T55	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T77	0	28	0	0
T107	0	8	0	0
T134	425	0	0	0
T262	0	20	0	0
T263	0	25	0	0
T277	0	14	0	0
T278	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	77304	0	0
T9	36087	3106	0	0
T10	21382	0	0	0
T41	0	1689	0	0
T49	0	1444	0	0
T50	5416	0	0	0
T55	0	424	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T77	0	1692	0	0
T107	0	633	0	0
T134	425	0	0	0
T262	0	2302	0	0
T263	0	6723	0	0
T277	0	868	0	0
T278	0	1325	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	741	0	0
T9	36087	20	0	0
T10	21382	0	0	0
T41	0	21	0	0
T49	0	14	0	0
T50	5416	0	0	0
T55	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T77	0	28	0	0
T107	0	7	0	0
T134	425	0	0	0
T262	0	16	0	0
T263	0	24	0	0
T277	0	14	0	0
T278	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T2,T9
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T2,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T10,T48

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T48
1	0	Covered	T6,T25,T2
1	1	Covered	T9,T10,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T48
0	1	Covered	T133,T63,T199
1	0	Covered	T55,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T48
0	1	Covered	T9,T10,T48
1	0	Covered	T55,T84,T279

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T48
1	-	Covered	T9,T10,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T48
DetectSt	168	Covered	T9,T10,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T10,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T48
DebounceSt->IdleSt	163	Covered	T57,T104,T39
DetectSt->IdleSt	186	Covered	T133,T63,T55
DetectSt->StableSt	191	Covered	T9,T10,T48
IdleSt->DebounceSt	148	Covered	T9,T10,T48
StableSt->IdleSt	206	Covered	T9,T10,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T10,T48
0	1	Covered	T9,T10,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T84
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T104,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T48
DetectSt	-	-	-	-	1	-	-	Covered	T133,T63,T55
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T48
DetectSt	-	-	-	-	0	0	-	Covered	T9,T10,T48
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T48
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6753481	787	0	0
CntIncr_A	6753481	44540	0	0
CntNoWrap_A	6753481	6069036	0	0
DetectStDropOut_A	6753481	64	0	0
DetectedOut_A	6753481	13175	0	0
DetectedPulseOut_A	6753481	306	0	0
DisabledIdleSt_A	6753481	5711324	0	0
DisabledNoDetection_A	6753481	5713045	0	0
EnterDebounceSt_A	6753481	413	0	0
EnterDetectSt_A	6753481	375	0	0
EnterStableSt_A	6753481	306	0	0
PulseIsPulse_A	6753481	306	0	0
StayInStableSt	6753481	12833	0	0
gen_high_level_sva.HighLevelEvent_A	6753481	6072167	0	0
gen_not_sticky_sva.StableStDropOut_A	6753481	266	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	787	0	0
T9	36087	2	0	0
T10	21382	2	0	0
T33	0	6	0	0
T38	0	2	0	0
T39	0	25	0	0
T41	0	4	0	0
T48	0	6	0	0
T50	5416	0	0	0
T57	0	11	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	3	0	0
T133	0	2	0	0
T134	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	44540	0	0
T9	36087	146	0	0
T10	21382	146	0	0
T33	0	327	0	0
T38	0	66	0	0
T39	0	1795	0	0
T41	0	156	0	0
T48	0	210	0	0
T50	5416	0	0	0
T57	0	625	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	150	0	0
T133	0	141	0	0
T134	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6069036	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	64	0	0
T44	877	0	0	0
T54	755	0	0	0
T63	0	8	0	0
T71	492	0	0	0
T97	0	4	0	0
T104	27089	0	0	0
T116	0	2	0	0
T120	502	0	0	0
T121	441	0	0	0
T122	422	0	0	0
T123	404	0	0	0
T124	422	0	0	0
T133	5966	1	0	0
T199	0	3	0	0
T269	0	9	0	0
T280	0	7	0	0
T281	0	1	0	0
T282	0	5	0	0
T283	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	13175	0	0
T9	36087	79	0	0
T10	21382	32	0	0
T33	0	17	0	0
T38	0	51	0	0
T39	0	268	0	0
T41	0	50	0	0
T48	0	30	0	0
T50	5416	0	0	0
T57	0	68	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	79	0	0
T134	425	0	0	0
T276	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	306	0	0
T9	36087	1	0	0
T10	21382	1	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	11	0	0
T41	0	2	0	0
T48	0	3	0	0
T50	5416	0	0	0
T57	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	1	0	0
T134	425	0	0	0
T276	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5711324	0	0
T4	1362	961	0	0
T5	685	284	0	0
T6	4492	628	0	0
T22	703	302	0	0
T23	508	107	0	0
T24	915	514	0	0
T25	4217	3816	0	0
T26	426	25	0	0
T27	522	121	0	0
T28	691	290	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	5713045	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	413	0	0
T9	36087	1	0	0
T10	21382	1	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	14	0	0
T41	0	2	0	0
T48	0	3	0	0
T50	5416	0	0	0
T57	0	6	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	2	0	0
T133	0	1	0	0
T134	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	375	0	0
T9	36087	1	0	0
T10	21382	1	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	11	0	0
T41	0	2	0	0
T48	0	3	0	0
T50	5416	0	0	0
T57	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	1	0	0
T133	0	1	0	0
T134	425	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	306	0	0
T9	36087	1	0	0
T10	21382	1	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	11	0	0
T41	0	2	0	0
T48	0	3	0	0
T50	5416	0	0	0
T57	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	1	0	0
T134	425	0	0	0
T276	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	306	0	0
T9	36087	1	0	0
T10	21382	1	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	11	0	0
T41	0	2	0	0
T48	0	3	0	0
T50	5416	0	0	0
T57	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	1	0	0
T134	425	0	0	0
T276	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	12833	0	0
T9	36087	78	0	0
T10	21382	31	0	0
T33	0	14	0	0
T38	0	50	0	0
T39	0	257	0	0
T41	0	48	0	0
T48	0	26	0	0
T50	5416	0	0	0
T57	0	63	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	78	0	0
T134	425	0	0	0
T276	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	6072167	0	0
T4	1362	962	0	0
T5	685	285	0	0
T6	4492	638	0	0
T22	703	303	0	0
T23	508	108	0	0
T24	915	515	0	0
T25	4217	3817	0	0
T26	426	26	0	0
T27	522	122	0	0
T28	691	291	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6753481	266	0	0
T9	36087	1	0	0
T10	21382	1	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	11	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	5416	0	0	0
T57	0	5	0	0
T59	536	0	0	0
T60	1008	0	0	0
T68	5828	0	0	0
T72	514	0	0	0
T73	545	0	0	0
T74	502	0	0	0
T104	0	1	0	0
T134	425	0	0	0
T276	0	2	0	0