Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1336325426	9587	0	0
auto_block_debounce_ctl_rd_A	1336325426	1440	0	0
auto_block_out_ctl_rd_A	1336325426	1591	0	0
com_det_ctl_0_rd_A	1336325426	3350	0	0
com_det_ctl_1_rd_A	1336325426	3550	0	0
com_det_ctl_2_rd_A	1336325426	3639	0	0
com_det_ctl_3_rd_A	1336325426	3484	0	0
com_out_ctl_0_rd_A	1336325426	3551	0	0
com_out_ctl_1_rd_A	1336325426	3596	0	0
com_out_ctl_2_rd_A	1336325426	3815	0	0
com_out_ctl_3_rd_A	1336325426	3594	0	0
com_pre_det_ctl_0_rd_A	1336325426	969	0	0
com_pre_det_ctl_1_rd_A	1336325426	1038	0	0
com_pre_det_ctl_2_rd_A	1336325426	1063	0	0
com_pre_det_ctl_3_rd_A	1336325426	1092	0	0
com_pre_sel_ctl_0_rd_A	1336325426	3736	0	0
com_pre_sel_ctl_1_rd_A	1336325426	3657	0	0
com_pre_sel_ctl_2_rd_A	1336325426	3698	0	0
com_pre_sel_ctl_3_rd_A	1336325426	3668	0	0
com_sel_ctl_0_rd_A	1336325426	3868	0	0
com_sel_ctl_1_rd_A	1336325426	3760	0	0
com_sel_ctl_2_rd_A	1336325426	3716	0	0
com_sel_ctl_3_rd_A	1336325426	3757	0	0
ec_rst_ctl_rd_A	1336325426	2155	0	0
intr_enable_rd_A	1336325426	1517	0	0
key_intr_ctl_rd_A	1336325426	1848	0	0
key_intr_debounce_ctl_rd_A	1336325426	1182	0	0
key_invert_ctl_rd_A	1336325426	3907	0	0
pin_allowed_ctl_rd_A	1336325426	4194	0	0
pin_out_ctl_rd_A	1336325426	3652	0	0
pin_out_value_rd_A	1336325426	3881	0	0
regwen_rd_A	1336325426	1109	0	0
ulp_ac_debounce_ctl_rd_A	1336325426	1209	0	0
ulp_ctl_rd_A	1336325426	1222	0	0
ulp_lid_debounce_ctl_rd_A	1336325426	1106	0	0
ulp_pwrb_debounce_ctl_rd_A	1336325426	1168	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	9587	0	0
T1	343194	0	0	0
T6	217892	1	0	0
T13	0	9	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T33	0	3	0	0
T63	0	9	0	0
T68	0	6	0	0
T100	0	9	0	0
T105	0	10	0	0
T141	0	2	0	0
T199	0	9	0	0
T218	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1440	0	0
T1	343194	0	0	0
T6	217892	5	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T45	0	7	0	0
T68	0	18	0	0
T78	0	12	0	0
T141	0	36	0	0
T142	0	15	0	0
T143	0	8	0	0
T199	0	32	0	0
T310	0	15	0	0
T311	0	6	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1591	0	0
T1	343194	0	0	0
T6	217892	3	0	0
T14	59595	0	0	0
T22	351637	7	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T45	0	14	0	0
T68	0	23	0	0
T78	0	12	0	0
T141	0	16	0	0
T142	0	6	0	0
T143	0	10	0	0
T310	0	15	0	0
T311	0	13	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3350	0	0
T1	343194	0	0	0
T6	217892	4	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	61	0	0
T41	0	28	0	0
T47	0	35	0	0
T68	0	20	0	0
T133	0	68	0	0
T141	0	17	0	0
T276	0	56	0	0
T312	0	58	0	0
T313	0	49	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3550	0	0
T1	343194	0	0	0
T6	217892	11	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	63	0	0
T41	0	20	0	0
T47	0	36	0	0
T68	0	23	0	0
T133	0	61	0	0
T141	0	18	0	0
T276	0	65	0	0
T312	0	69	0	0
T313	0	84	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3639	0	0
T1	343194	0	0	0
T6	217892	8	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	56	0	0
T41	0	31	0	0
T47	0	46	0	0
T68	0	13	0	0
T133	0	82	0	0
T141	0	13	0	0
T276	0	87	0	0
T312	0	48	0	0
T313	0	83	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3484	0	0
T10	267287	0	0	0
T11	295865	0	0	0
T40	0	59	0	0
T41	0	33	0	0
T47	0	51	0	0
T50	270810	0	0	0
T59	64380	0	0	0
T60	247112	0	0	0
T68	282678	16	0	0
T73	16380	0	0	0
T74	243481	0	0	0
T133	0	71	0	0
T134	42508	0	0	0
T135	48905	0	0	0
T141	0	28	0	0
T199	0	67	0	0
T276	0	77	0	0
T312	0	52	0	0
T313	0	86	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3551	0	0
T1	343194	0	0	0
T6	217892	3	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	74	0	0
T41	0	39	0	0
T47	0	17	0	0
T68	0	9	0	0
T133	0	61	0	0
T141	0	12	0	0
T276	0	75	0	0
T312	0	70	0	0
T313	0	62	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3596	0	0
T1	343194	0	0	0
T6	217892	7	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	73	0	0
T41	0	40	0	0
T47	0	61	0	0
T68	0	18	0	0
T133	0	81	0	0
T141	0	14	0	0
T276	0	60	0	0
T312	0	87	0	0
T313	0	43	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3815	0	0
T10	267287	0	0	0
T11	295865	0	0	0
T40	0	85	0	0
T41	0	24	0	0
T47	0	39	0	0
T50	270810	0	0	0
T59	64380	0	0	0
T60	247112	0	0	0
T68	282678	8	0	0
T73	16380	0	0	0
T74	243481	0	0	0
T133	0	60	0	0
T134	42508	0	0	0
T135	48905	0	0	0
T141	0	9	0	0
T199	0	78	0	0
T276	0	86	0	0
T312	0	67	0	0
T313	0	64	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3594	0	0
T1	343194	0	0	0
T6	217892	11	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	48	0	0
T41	0	19	0	0
T47	0	39	0	0
T68	0	17	0	0
T133	0	56	0	0
T141	0	6	0	0
T276	0	73	0	0
T312	0	84	0	0
T313	0	79	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	969	0	0
T1	343194	0	0	0
T6	217892	14	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	25	0	0
T89	0	23	0	0
T141	0	22	0	0
T170	0	15	0	0
T172	0	30	0	0
T187	0	12	0	0
T199	0	13	0	0
T314	0	29	0	0
T315	0	16	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1038	0	0
T1	343194	0	0	0
T6	217892	14	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	9	0	0
T89	0	34	0	0
T141	0	8	0	0
T170	0	7	0	0
T172	0	40	0	0
T187	0	6	0	0
T199	0	21	0	0
T314	0	31	0	0
T315	0	28	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1063	0	0
T1	343194	0	0	0
T6	217892	4	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	11	0	0
T89	0	21	0	0
T141	0	29	0	0
T170	0	13	0	0
T172	0	28	0	0
T187	0	13	0	0
T199	0	24	0	0
T314	0	36	0	0
T315	0	23	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1092	0	0
T1	343194	0	0	0
T6	217892	1	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	23	0	0
T89	0	22	0	0
T141	0	28	0	0
T170	0	12	0	0
T172	0	34	0	0
T187	0	7	0	0
T199	0	36	0	0
T314	0	31	0	0
T315	0	11	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3736	0	0
T1	343194	0	0	0
T6	217892	8	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	77	0	0
T41	0	46	0	0
T47	0	37	0	0
T68	0	15	0	0
T133	0	84	0	0
T141	0	16	0	0
T276	0	58	0	0
T312	0	76	0	0
T313	0	67	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3657	0	0
T1	343194	0	0	0
T6	217892	11	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	77	0	0
T41	0	18	0	0
T47	0	22	0	0
T68	0	19	0	0
T133	0	89	0	0
T141	0	19	0	0
T276	0	66	0	0
T312	0	60	0	0
T313	0	70	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3698	0	0
T1	343194	0	0	0
T6	217892	5	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	69	0	0
T41	0	42	0	0
T47	0	35	0	0
T68	0	18	0	0
T133	0	86	0	0
T141	0	10	0	0
T276	0	80	0	0
T312	0	82	0	0
T313	0	54	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3668	0	0
T1	343194	0	0	0
T6	217892	4	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	69	0	0
T41	0	35	0	0
T47	0	36	0	0
T68	0	18	0	0
T133	0	63	0	0
T141	0	11	0	0
T276	0	57	0	0
T312	0	64	0	0
T313	0	73	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3868	0	0
T10	267287	0	0	0
T11	295865	0	0	0
T40	0	68	0	0
T41	0	20	0	0
T47	0	22	0	0
T50	270810	0	0	0
T59	64380	0	0	0
T60	247112	0	0	0
T68	282678	18	0	0
T73	16380	0	0	0
T74	243481	0	0	0
T133	0	77	0	0
T134	42508	0	0	0
T135	48905	0	0	0
T141	0	15	0	0
T199	0	60	0	0
T276	0	88	0	0
T312	0	78	0	0
T313	0	56	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3760	0	0
T10	267287	0	0	0
T11	295865	0	0	0
T40	0	86	0	0
T41	0	30	0	0
T47	0	14	0	0
T50	270810	0	0	0
T59	64380	0	0	0
T60	247112	0	0	0
T68	282678	30	0	0
T73	16380	0	0	0
T74	243481	0	0	0
T133	0	76	0	0
T134	42508	0	0	0
T135	48905	0	0	0
T141	0	9	0	0
T199	0	71	0	0
T276	0	63	0	0
T312	0	77	0	0
T313	0	68	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3716	0	0
T1	343194	0	0	0
T6	217892	2	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	94	0	0
T41	0	27	0	0
T47	0	38	0	0
T68	0	8	0	0
T133	0	70	0	0
T141	0	16	0	0
T276	0	69	0	0
T312	0	65	0	0
T313	0	51	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3757	0	0
T1	343194	0	0	0
T6	217892	3	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	44	0	0
T41	0	27	0	0
T47	0	36	0	0
T68	0	26	0	0
T133	0	65	0	0
T141	0	15	0	0
T276	0	58	0	0
T312	0	69	0	0
T313	0	51	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	2155	0	0
T1	343194	0	0	0
T6	217892	11	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T40	0	15	0	0
T41	0	12	0	0
T68	0	24	0	0
T133	0	8	0	0
T141	0	9	0	0
T276	0	11	0	0
T312	0	25	0	0
T313	0	37	0	0
T316	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1517	0	0
T1	343194	0	0	0
T6	217892	11	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T45	0	7	0	0
T68	0	29	0	0
T89	0	39	0	0
T141	0	14	0	0
T170	0	39	0	0
T172	0	42	0	0
T187	0	27	0	0
T199	0	32	0	0
T314	0	94	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1848	0	0
T1	343194	0	0	0
T6	217892	13	0	0
T7	0	1	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T44	0	4	0	0
T45	0	2	0	0
T68	0	16	0	0
T86	0	4	0	0
T91	0	4	0	0
T141	0	16	0	0
T199	0	37	0	0
T208	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1182	0	0
T1	343194	0	0	0
T6	217892	8	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	16	0	0
T89	0	27	0	0
T141	0	7	0	0
T170	0	15	0	0
T172	0	26	0	0
T187	0	8	0	0
T199	0	20	0	0
T314	0	22	0	0
T315	0	21	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3907	0	0
T1	343194	0	0	0
T6	217892	45	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	91	0	0
T71	0	77	0	0
T78	0	61	0	0
T141	0	72	0	0
T172	0	24	0	0
T197	0	54	0	0
T199	0	151	0	0
T226	0	80	0	0
T317	0	60	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	4194	0	0
T1	343194	0	0	0
T6	217892	34	0	0
T14	59595	0	0	0
T18	0	60	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T61	0	130	0	0
T68	0	77	0	0
T74	0	43	0	0
T141	0	79	0	0
T199	0	37	0	0
T318	0	50	0	0
T319	0	72	0	0
T320	0	57	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3652	0	0
T1	343194	0	0	0
T6	217892	63	0	0
T14	59595	0	0	0
T18	0	63	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T61	0	125	0	0
T68	0	85	0	0
T74	0	37	0	0
T141	0	76	0	0
T199	0	23	0	0
T318	0	47	0	0
T319	0	63	0	0
T320	0	51	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	3881	0	0
T1	343194	0	0	0
T6	217892	57	0	0
T14	59595	0	0	0
T18	0	75	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T61	0	156	0	0
T68	0	91	0	0
T74	0	75	0	0
T141	0	78	0	0
T199	0	15	0	0
T318	0	67	0	0
T319	0	78	0	0
T320	0	60	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1109	0	0
T1	343194	0	0	0
T6	217892	3	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	6	0	0
T89	0	10	0	0
T141	0	13	0	0
T170	0	12	0	0
T172	0	18	0	0
T187	0	7	0	0
T199	0	29	0	0
T314	0	26	0	0
T315	0	24	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1209	0	0
T1	343194	0	0	0
T6	217892	5	0	0
T14	59595	0	0	0
T21	0	3	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T61	0	5	0	0
T68	0	9	0	0
T78	0	5	0	0
T137	0	8	0	0
T139	0	17	0	0
T141	0	11	0	0
T172	0	19	0	0
T199	0	31	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1222	0	0
T1	343194	0	0	0
T6	217892	10	0	0
T14	59595	0	0	0
T21	0	4	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T61	0	7	0	0
T68	0	17	0	0
T78	0	1	0	0
T137	0	9	0	0
T139	0	17	0	0
T141	0	18	0	0
T172	0	31	0	0
T199	0	44	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1106	0	0
T1	343194	0	0	0
T6	217892	11	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T68	0	13	0	0
T78	0	4	0	0
T137	0	9	0	0
T139	0	8	0	0
T141	0	22	0	0
T172	0	28	0	0
T199	0	25	0	0
T321	0	4	0	0
T322	0	10	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1336325426	1168	0	0
T1	343194	0	0	0
T6	217892	18	0	0
T14	59595	0	0	0
T22	351637	0	0	0
T23	50896	0	0	0
T24	109810	0	0	0
T25	991106	0	0	0
T26	204426	0	0	0
T27	237540	0	0	0
T28	48464	0	0	0
T61	0	1	0	0
T68	0	3	0	0
T78	0	2	0	0
T137	0	9	0	0
T139	0	6	0	0
T141	0	16	0	0
T172	0	18	0	0
T199	0	30	0	0
T321	0	6	0	0