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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.33 96.81 100.00 97.44 98.74 99.61 93.69


Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T177 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3445556561 Apr 23 02:24:21 PM PDT 24 Apr 23 02:24:30 PM PDT 24 2841663894 ps
T92 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.111983167 Apr 23 02:24:14 PM PDT 24 Apr 23 02:24:16 PM PDT 24 4545833678 ps
T210 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2497857446 Apr 23 02:23:46 PM PDT 24 Apr 23 02:24:21 PM PDT 24 38603526603 ps
T211 /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.714840831 Apr 23 02:22:41 PM PDT 24 Apr 23 02:22:43 PM PDT 24 2623030327 ps
T212 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1419986694 Apr 23 02:23:39 PM PDT 24 Apr 23 02:23:49 PM PDT 24 2961070273 ps
T213 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2248117238 Apr 23 02:24:55 PM PDT 24 Apr 23 02:25:40 PM PDT 24 63568880603 ps
T214 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1691565472 Apr 23 02:24:16 PM PDT 24 Apr 23 02:24:25 PM PDT 24 2609196859 ps
T215 /workspace/coverage/default/13.sysrst_ctrl_stress_all.2631957246 Apr 23 02:23:02 PM PDT 24 Apr 23 02:23:08 PM PDT 24 7274801013 ps
T140 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2468758939 Apr 23 02:23:17 PM PDT 24 Apr 23 02:23:22 PM PDT 24 6440458912 ps
T216 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1969440339 Apr 23 02:23:52 PM PDT 24 Apr 23 02:24:08 PM PDT 24 42915310263 ps
T217 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3180414889 Apr 23 02:22:41 PM PDT 24 Apr 23 02:22:48 PM PDT 24 2215573077 ps
T321 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2326643485 Apr 23 02:23:02 PM PDT 24 Apr 23 02:23:08 PM PDT 24 3748325197 ps
T470 /workspace/coverage/default/16.sysrst_ctrl_alert_test.757240355 Apr 23 02:23:00 PM PDT 24 Apr 23 02:23:03 PM PDT 24 2030001425 ps
T471 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3335525883 Apr 23 02:22:20 PM PDT 24 Apr 23 02:22:27 PM PDT 24 2227424573 ps
T472 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3963355463 Apr 23 02:22:57 PM PDT 24 Apr 23 02:23:02 PM PDT 24 2467550278 ps
T473 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.155853712 Apr 23 02:23:04 PM PDT 24 Apr 23 02:23:07 PM PDT 24 2524042376 ps
T474 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.949168061 Apr 23 02:23:17 PM PDT 24 Apr 23 02:27:43 PM PDT 24 253980999310 ps
T475 /workspace/coverage/default/19.sysrst_ctrl_alert_test.3299640650 Apr 23 02:23:20 PM PDT 24 Apr 23 02:23:26 PM PDT 24 2012905028 ps
T476 /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1668630166 Apr 23 02:22:38 PM PDT 24 Apr 23 02:22:40 PM PDT 24 2464531764 ps
T264 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.107811275 Apr 23 02:22:41 PM PDT 24 Apr 23 02:22:53 PM PDT 24 25580467936 ps
T220 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3247606120 Apr 23 02:23:57 PM PDT 24 Apr 23 02:24:00 PM PDT 24 2962489279 ps
T477 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3141565391 Apr 23 02:24:17 PM PDT 24 Apr 23 02:24:24 PM PDT 24 3298141773 ps
T478 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4199645369 Apr 23 02:24:10 PM PDT 24 Apr 23 02:24:19 PM PDT 24 3194338741 ps
T479 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.640121007 Apr 23 02:23:49 PM PDT 24 Apr 23 02:23:51 PM PDT 24 2937084466 ps
T480 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2651556071 Apr 23 02:24:19 PM PDT 24 Apr 23 02:24:27 PM PDT 24 2611352581 ps
T322 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3184878055 Apr 23 02:23:21 PM PDT 24 Apr 23 02:23:24 PM PDT 24 9616013640 ps
T481 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3331049835 Apr 23 02:22:44 PM PDT 24 Apr 23 02:22:50 PM PDT 24 2473812961 ps
T482 /workspace/coverage/default/9.sysrst_ctrl_smoke.2279508496 Apr 23 02:22:30 PM PDT 24 Apr 23 02:22:37 PM PDT 24 2114139901 ps
T209 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3576909570 Apr 23 02:23:33 PM PDT 24 Apr 23 02:23:36 PM PDT 24 5701146100 ps
T200 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2972090557 Apr 23 02:23:50 PM PDT 24 Apr 23 02:23:55 PM PDT 24 4267130672 ps
T483 /workspace/coverage/default/0.sysrst_ctrl_alert_test.816515383 Apr 23 02:22:29 PM PDT 24 Apr 23 02:22:35 PM PDT 24 2014659405 ps
T484 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3178644087 Apr 23 02:22:28 PM PDT 24 Apr 23 02:22:30 PM PDT 24 2530816138 ps
T393 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3410526903 Apr 23 02:25:26 PM PDT 24 Apr 23 02:27:50 PM PDT 24 59631751289 ps
T485 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3985709505 Apr 23 02:22:29 PM PDT 24 Apr 23 02:22:34 PM PDT 24 2034998288 ps
T378 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.383606042 Apr 23 02:24:19 PM PDT 24 Apr 23 02:26:01 PM PDT 24 99766848947 ps
T201 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.605148945 Apr 23 02:23:37 PM PDT 24 Apr 23 02:24:38 PM PDT 24 24008205105 ps
T486 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.160144560 Apr 23 02:23:17 PM PDT 24 Apr 23 02:23:20 PM PDT 24 2118391200 ps
T273 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1705951186 Apr 23 02:23:04 PM PDT 24 Apr 23 02:23:33 PM PDT 24 45842571898 ps
T89 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3125945903 Apr 23 02:23:25 PM PDT 24 Apr 23 02:24:21 PM PDT 24 89142797360 ps
T265 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.142605311 Apr 23 02:24:26 PM PDT 24 Apr 23 02:25:31 PM PDT 24 26833233642 ps
T487 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.858657720 Apr 23 02:24:05 PM PDT 24 Apr 23 02:24:16 PM PDT 24 3943015709 ps
T488 /workspace/coverage/default/37.sysrst_ctrl_stress_all.2024714543 Apr 23 02:23:50 PM PDT 24 Apr 23 02:23:57 PM PDT 24 6574912663 ps
T489 /workspace/coverage/default/39.sysrst_ctrl_smoke.331145759 Apr 23 02:23:52 PM PDT 24 Apr 23 02:23:54 PM PDT 24 2132113512 ps
T490 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2300443494 Apr 23 02:22:45 PM PDT 24 Apr 23 02:23:28 PM PDT 24 261302506219 ps
T314 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3605929170 Apr 23 02:23:58 PM PDT 24 Apr 23 02:25:53 PM PDT 24 46133986472 ps
T491 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1454965473 Apr 23 02:23:10 PM PDT 24 Apr 23 02:23:19 PM PDT 24 3070759698 ps
T366 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2379106538 Apr 23 02:24:25 PM PDT 24 Apr 23 02:30:25 PM PDT 24 137399897091 ps
T492 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.935564523 Apr 23 02:22:51 PM PDT 24 Apr 23 02:22:54 PM PDT 24 2495726252 ps
T272 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1044022450 Apr 23 02:23:14 PM PDT 24 Apr 23 02:24:15 PM PDT 24 47219095619 ps
T493 /workspace/coverage/default/15.sysrst_ctrl_alert_test.849027327 Apr 23 02:23:04 PM PDT 24 Apr 23 02:23:07 PM PDT 24 2025063430 ps
T494 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2334740475 Apr 23 02:24:05 PM PDT 24 Apr 23 02:24:10 PM PDT 24 2617406236 ps
T495 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2300697968 Apr 23 02:22:25 PM PDT 24 Apr 23 02:22:27 PM PDT 24 2160714817 ps
T170 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2638094500 Apr 23 02:22:53 PM PDT 24 Apr 23 02:24:06 PM PDT 24 100517153236 ps
T496 /workspace/coverage/default/14.sysrst_ctrl_smoke.3634299477 Apr 23 02:23:00 PM PDT 24 Apr 23 02:23:03 PM PDT 24 2136585679 ps
T292 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.266926903 Apr 23 02:23:24 PM PDT 24 Apr 23 02:24:04 PM PDT 24 15030292970 ps
T497 /workspace/coverage/default/11.sysrst_ctrl_alert_test.3464596824 Apr 23 02:22:40 PM PDT 24 Apr 23 02:22:45 PM PDT 24 2034930048 ps
T498 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.102503324 Apr 23 02:23:41 PM PDT 24 Apr 23 02:25:48 PM PDT 24 50506984079 ps
T499 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2423975038 Apr 23 02:22:42 PM PDT 24 Apr 23 02:22:45 PM PDT 24 2737758133 ps
T500 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.436206029 Apr 23 02:23:12 PM PDT 24 Apr 23 02:23:16 PM PDT 24 2475386743 ps
T501 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3831665984 Apr 23 02:22:55 PM PDT 24 Apr 23 02:28:57 PM PDT 24 272732827035 ps
T502 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3250904003 Apr 23 02:23:58 PM PDT 24 Apr 23 02:24:05 PM PDT 24 2479836591 ps
T371 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.810365329 Apr 23 02:24:32 PM PDT 24 Apr 23 02:26:16 PM PDT 24 73756304029 ps
T390 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2159668941 Apr 23 02:24:03 PM PDT 24 Apr 23 02:24:33 PM PDT 24 39620976031 ps
T503 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1550867369 Apr 23 02:22:30 PM PDT 24 Apr 23 02:22:33 PM PDT 24 2499761273 ps
T504 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2440719854 Apr 23 02:23:51 PM PDT 24 Apr 23 02:23:53 PM PDT 24 2645656965 ps
T203 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.377310403 Apr 23 02:22:53 PM PDT 24 Apr 23 02:22:58 PM PDT 24 3674680224 ps
T505 /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.979372641 Apr 23 02:22:38 PM PDT 24 Apr 23 02:22:42 PM PDT 24 3413132839 ps
T506 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.871290677 Apr 23 02:23:23 PM PDT 24 Apr 23 02:23:30 PM PDT 24 2202384646 ps
T507 /workspace/coverage/default/10.sysrst_ctrl_alert_test.1114870899 Apr 23 02:22:31 PM PDT 24 Apr 23 02:22:34 PM PDT 24 2046855001 ps
T508 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3145555385 Apr 23 02:22:46 PM PDT 24 Apr 23 02:24:19 PM PDT 24 136179786307 ps
T274 /workspace/coverage/default/7.sysrst_ctrl_stress_all.3517738680 Apr 23 02:22:41 PM PDT 24 Apr 23 02:25:22 PM PDT 24 56496489342 ps
T112 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.605963547 Apr 23 02:24:06 PM PDT 24 Apr 23 02:26:35 PM PDT 24 2177154678160 ps
T126 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2782058722 Apr 23 02:24:02 PM PDT 24 Apr 23 02:24:04 PM PDT 24 2218817420 ps
T84 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1238543420 Apr 23 02:22:19 PM PDT 24 Apr 23 02:23:18 PM PDT 24 38334369908 ps
T127 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.402985592 Apr 23 02:24:24 PM PDT 24 Apr 23 02:24:41 PM PDT 24 30740448553 ps
T128 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.924579118 Apr 23 02:24:04 PM PDT 24 Apr 23 02:24:07 PM PDT 24 2523906144 ps
T95 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.905347804 Apr 23 02:22:39 PM PDT 24 Apr 23 02:22:48 PM PDT 24 7601437045 ps
T129 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1795472152 Apr 23 02:24:01 PM PDT 24 Apr 23 02:24:07 PM PDT 24 2099105490 ps
T130 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4201569473 Apr 23 02:22:31 PM PDT 24 Apr 23 02:22:35 PM PDT 24 2458794280 ps
T131 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.668797497 Apr 23 02:24:02 PM PDT 24 Apr 23 02:24:05 PM PDT 24 4204067049 ps
T132 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2690727665 Apr 23 02:22:28 PM PDT 24 Apr 23 02:22:37 PM PDT 24 2530765859 ps
T509 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1963721423 Apr 23 02:22:32 PM PDT 24 Apr 23 02:22:36 PM PDT 24 3718666509 ps
T362 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1151842466 Apr 23 02:24:27 PM PDT 24 Apr 23 02:25:37 PM PDT 24 104156880123 ps
T510 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3159311836 Apr 23 02:22:40 PM PDT 24 Apr 23 02:22:43 PM PDT 24 4349575437 ps
T511 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.27359993 Apr 23 02:23:44 PM PDT 24 Apr 23 02:23:48 PM PDT 24 2476384241 ps
T512 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2794861160 Apr 23 02:23:33 PM PDT 24 Apr 23 02:23:36 PM PDT 24 2533161713 ps
T513 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3807123750 Apr 23 02:22:32 PM PDT 24 Apr 23 02:22:44 PM PDT 24 3893692444 ps
T360 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3917551603 Apr 23 02:24:27 PM PDT 24 Apr 23 02:26:01 PM PDT 24 35555717643 ps
T514 /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.366899086 Apr 23 02:22:30 PM PDT 24 Apr 23 02:23:06 PM PDT 24 114069315344 ps
T515 /workspace/coverage/default/22.sysrst_ctrl_alert_test.2391949946 Apr 23 02:23:10 PM PDT 24 Apr 23 02:23:12 PM PDT 24 2116062312 ps
T516 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1482112765 Apr 23 02:23:30 PM PDT 24 Apr 23 02:26:00 PM PDT 24 234220135549 ps
T517 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2098192117 Apr 23 02:24:04 PM PDT 24 Apr 23 02:24:11 PM PDT 24 2475684957 ps
T518 /workspace/coverage/default/2.sysrst_ctrl_smoke.479115857 Apr 23 02:22:28 PM PDT 24 Apr 23 02:22:34 PM PDT 24 2108579342 ps
T519 /workspace/coverage/default/24.sysrst_ctrl_alert_test.3236021768 Apr 23 02:23:17 PM PDT 24 Apr 23 02:23:24 PM PDT 24 2009667781 ps
T520 /workspace/coverage/default/7.sysrst_ctrl_smoke.2968880355 Apr 23 02:22:42 PM PDT 24 Apr 23 02:22:48 PM PDT 24 2112625574 ps
T521 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.942027042 Apr 23 02:23:53 PM PDT 24 Apr 23 02:24:00 PM PDT 24 4122219575 ps
T522 /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.4071410156 Apr 23 02:22:47 PM PDT 24 Apr 23 02:22:52 PM PDT 24 2619559305 ps
T523 /workspace/coverage/default/44.sysrst_ctrl_alert_test.3026713538 Apr 23 02:24:08 PM PDT 24 Apr 23 02:24:11 PM PDT 24 2035003300 ps
T524 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.217367530 Apr 23 02:23:39 PM PDT 24 Apr 23 02:23:44 PM PDT 24 2427355884 ps
T525 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2134791296 Apr 23 02:22:31 PM PDT 24 Apr 23 02:22:39 PM PDT 24 2511010715 ps
T526 /workspace/coverage/default/38.sysrst_ctrl_alert_test.711747050 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:34 PM PDT 24 2012106374 ps
T527 /workspace/coverage/default/30.sysrst_ctrl_alert_test.1503673219 Apr 23 02:23:37 PM PDT 24 Apr 23 02:23:40 PM PDT 24 2043836131 ps
T368 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2950441430 Apr 23 02:22:56 PM PDT 24 Apr 23 02:23:23 PM PDT 24 46054309811 ps
T528 /workspace/coverage/default/2.sysrst_ctrl_alert_test.2025946545 Apr 23 02:22:29 PM PDT 24 Apr 23 02:22:36 PM PDT 24 2011935260 ps
T529 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.339736064 Apr 23 02:22:43 PM PDT 24 Apr 23 02:22:50 PM PDT 24 2170630608 ps
T379 /workspace/coverage/default/39.sysrst_ctrl_stress_all.1183342095 Apr 23 02:23:53 PM PDT 24 Apr 23 02:24:51 PM PDT 24 100757032271 ps
T530 /workspace/coverage/default/28.sysrst_ctrl_alert_test.3882770680 Apr 23 02:23:39 PM PDT 24 Apr 23 02:23:45 PM PDT 24 2013485610 ps
T531 /workspace/coverage/default/39.sysrst_ctrl_alert_test.366115412 Apr 23 02:23:56 PM PDT 24 Apr 23 02:23:58 PM PDT 24 2050026607 ps
T113 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.245058382 Apr 23 02:23:35 PM PDT 24 Apr 23 02:29:08 PM PDT 24 137199017863 ps
T532 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4052226354 Apr 23 02:22:24 PM PDT 24 Apr 23 02:22:29 PM PDT 24 6305044762 ps
T533 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.355473958 Apr 23 02:23:20 PM PDT 24 Apr 23 02:23:30 PM PDT 24 10757700681 ps
T93 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1804127717 Apr 23 02:23:22 PM PDT 24 Apr 23 02:23:25 PM PDT 24 3213663774 ps
T534 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3013174952 Apr 23 02:23:14 PM PDT 24 Apr 23 02:23:16 PM PDT 24 2592252324 ps
T535 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3779090332 Apr 23 02:23:51 PM PDT 24 Apr 23 02:23:56 PM PDT 24 7466525902 ps
T536 /workspace/coverage/default/20.sysrst_ctrl_alert_test.2569872227 Apr 23 02:23:06 PM PDT 24 Apr 23 02:23:10 PM PDT 24 2027327491 ps
T268 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1100476760 Apr 23 02:24:19 PM PDT 24 Apr 23 02:25:37 PM PDT 24 117376315978 ps
T537 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3036209403 Apr 23 02:22:17 PM PDT 24 Apr 23 02:22:20 PM PDT 24 2495206088 ps
T538 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3150883175 Apr 23 02:24:33 PM PDT 24 Apr 23 02:25:33 PM PDT 24 25833712652 ps
T539 /workspace/coverage/default/17.sysrst_ctrl_smoke.1844484311 Apr 23 02:22:56 PM PDT 24 Apr 23 02:23:01 PM PDT 24 2112661732 ps
T540 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1332650593 Apr 23 02:23:11 PM PDT 24 Apr 23 02:23:15 PM PDT 24 2027322111 ps
T541 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.129855884 Apr 23 02:24:24 PM PDT 24 Apr 23 02:25:24 PM PDT 24 24080791201 ps
T542 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.154461095 Apr 23 02:23:53 PM PDT 24 Apr 23 02:23:55 PM PDT 24 2133508976 ps
T269 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.364301100 Apr 23 02:23:58 PM PDT 24 Apr 23 02:24:36 PM PDT 24 51464860934 ps
T543 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.316782958 Apr 23 02:25:32 PM PDT 24 Apr 23 02:25:36 PM PDT 24 3195580869 ps
T544 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.990883962 Apr 23 02:22:55 PM PDT 24 Apr 23 02:24:25 PM PDT 24 35476232633 ps
T545 /workspace/coverage/default/46.sysrst_ctrl_alert_test.2145407573 Apr 23 02:24:17 PM PDT 24 Apr 23 02:24:20 PM PDT 24 2065151791 ps
T275 /workspace/coverage/default/32.sysrst_ctrl_stress_all.771702917 Apr 23 02:23:39 PM PDT 24 Apr 23 02:24:46 PM PDT 24 104595256669 ps
T546 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3023283572 Apr 23 02:23:38 PM PDT 24 Apr 23 02:23:47 PM PDT 24 3160556463 ps
T547 /workspace/coverage/default/49.sysrst_ctrl_alert_test.829720982 Apr 23 02:24:22 PM PDT 24 Apr 23 02:24:24 PM PDT 24 2038626851 ps
T548 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.302031504 Apr 23 02:23:09 PM PDT 24 Apr 23 02:23:12 PM PDT 24 2634482022 ps
T363 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.88757901 Apr 23 02:24:29 PM PDT 24 Apr 23 02:26:00 PM PDT 24 70064417397 ps
T549 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2718012083 Apr 23 02:23:05 PM PDT 24 Apr 23 02:25:29 PM PDT 24 112530286030 ps
T550 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3442858491 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:35 PM PDT 24 2222927635 ps
T551 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3678973020 Apr 23 02:22:28 PM PDT 24 Apr 23 02:22:32 PM PDT 24 2538114873 ps
T552 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3369262413 Apr 23 02:24:01 PM PDT 24 Apr 23 02:24:04 PM PDT 24 2509093284 ps
T171 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2389030471 Apr 23 02:22:53 PM PDT 24 Apr 23 02:22:55 PM PDT 24 3852564394 ps
T553 /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1233089918 Apr 23 02:22:31 PM PDT 24 Apr 23 02:22:36 PM PDT 24 2149202195 ps
T554 /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2848950079 Apr 23 02:23:41 PM PDT 24 Apr 23 02:23:48 PM PDT 24 2467496475 ps
T154 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2258206876 Apr 23 02:22:43 PM PDT 24 Apr 23 02:22:52 PM PDT 24 5046687692 ps
T356 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3388890756 Apr 23 02:22:59 PM PDT 24 Apr 23 02:29:00 PM PDT 24 146841436064 ps
T187 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3978546114 Apr 23 02:22:29 PM PDT 24 Apr 23 02:22:48 PM PDT 24 29476488674 ps
T205 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2903426389 Apr 23 02:23:47 PM PDT 24 Apr 23 02:23:50 PM PDT 24 2871865618 ps
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T581 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2233350523 Apr 23 02:22:59 PM PDT 24 Apr 23 02:23:02 PM PDT 24 2528649950 ps
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T582 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1120226034 Apr 23 02:22:18 PM PDT 24 Apr 23 02:22:23 PM PDT 24 2543414758 ps
T583 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2333825840 Apr 23 02:22:43 PM PDT 24 Apr 23 02:22:49 PM PDT 24 2618454802 ps
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T592 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3100814596 Apr 23 02:23:56 PM PDT 24 Apr 23 02:24:02 PM PDT 24 3667866455 ps
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T602 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3436433213 Apr 23 02:22:43 PM PDT 24 Apr 23 02:22:52 PM PDT 24 2613830188 ps
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T604 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.677767791 Apr 23 02:22:41 PM PDT 24 Apr 23 02:22:44 PM PDT 24 3386417487 ps
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T315 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2671390862 Apr 23 02:22:19 PM PDT 24 Apr 23 02:23:29 PM PDT 24 28074164996 ps
T369 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.4237874919 Apr 23 02:22:30 PM PDT 24 Apr 23 02:23:21 PM PDT 24 75111957318 ps
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T98 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2462955354 Apr 23 02:23:37 PM PDT 24 Apr 23 02:24:46 PM PDT 24 98496222042 ps
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T239 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3524838656 Apr 23 02:22:54 PM PDT 24 Apr 23 02:23:48 PM PDT 24 109364291877 ps
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T615 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2367408443 Apr 23 02:22:47 PM PDT 24 Apr 23 02:22:50 PM PDT 24 2542245612 ps
T240 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2067933753 Apr 23 02:23:25 PM PDT 24 Apr 23 02:23:33 PM PDT 24 3356825448 ps
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T618 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3887726626 Apr 23 02:24:01 PM PDT 24 Apr 23 02:24:11 PM PDT 24 3578000507 ps
T619 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1216314582 Apr 23 02:23:50 PM PDT 24 Apr 23 02:23:54 PM PDT 24 3491004369 ps
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T260 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1206350490 Apr 23 02:22:44 PM PDT 24 Apr 23 02:23:47 PM PDT 24 21828501369 ps
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T620 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.1883003897 Apr 23 02:23:21 PM PDT 24 Apr 23 02:23:25 PM PDT 24 3949744663 ps
T621 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1819560657 Apr 23 02:24:04 PM PDT 24 Apr 23 02:24:06 PM PDT 24 2524014549 ps
T622 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.950062977 Apr 23 02:25:26 PM PDT 24 Apr 23 02:26:37 PM PDT 24 27329327938 ps
T623 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3631840700 Apr 23 02:24:29 PM PDT 24 Apr 23 02:24:48 PM PDT 24 25352165605 ps
T624 /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2374652786 Apr 23 02:23:01 PM PDT 24 Apr 23 02:23:08 PM PDT 24 2202790805 ps
T155 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3168747594 Apr 23 02:22:45 PM PDT 24 Apr 23 02:22:52 PM PDT 24 3632723958 ps
T90 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3791607873 Apr 23 02:22:31 PM PDT 24 Apr 23 02:23:55 PM PDT 24 70474062233 ps
T243 /workspace/coverage/default/40.sysrst_ctrl_alert_test.1048537475 Apr 23 02:23:57 PM PDT 24 Apr 23 02:24:04 PM PDT 24 2009046724 ps
T244 /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2897031010 Apr 23 02:22:42 PM PDT 24 Apr 23 02:22:45 PM PDT 24 2528758444 ps
T245 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.958774511 Apr 23 02:22:47 PM PDT 24 Apr 23 02:22:52 PM PDT 24 2465746329 ps
T207 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2092590640 Apr 23 02:22:43 PM PDT 24 Apr 23 02:22:52 PM PDT 24 92423084651 ps
T246 /workspace/coverage/default/40.sysrst_ctrl_smoke.2777595107 Apr 23 02:23:58 PM PDT 24 Apr 23 02:24:01 PM PDT 24 2118275887 ps
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