Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1933

1

T1

1

T3

9

T5

17

auto[1]

690

1

T1

12

T3

6

T5

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2015

1

T1

9

T3

13

T5

8

auto[1]

608

1

T1

4

T3

2

T5

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2014

1

T1

8

T3

5

T5

9

auto[1]

609

1

T1

5

T3

10

T5

12

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1936

1

T1

13

T3

14

T5

21

auto[1]

687

1

T3

1

T27

4

T6

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2422

1

T1

13

T3

15

T5

21

auto[1]

201

1

T27

1

T28

14

T34

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2379

1

T1

13

T3

15

T5

21

auto[1]

244

1

T27

5

T28

2

T45

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2297

1

T1

13

T3

15

T5

21

auto[1]

326

1

T28

2

T45

13

T34

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2475

1

T1

13

T3

15

T5

21

auto[1]

148

1

T45

10

T81

6

T264

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2442

1

T1

13

T3

15

T5

21

auto[1]

181

1

T27

5

T28

2

T46

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2033

1

T1

12

T3

9

T5

13

auto[1]

590

1

T1

1

T3

6

T5

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	978	1			T1	12		T3	15		T5	21
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	66	1			T28	12		T34	1		T46	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	53	1			T81	2		T262	4		T313	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	32	1			T46	5		T320	3		T132	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	42	1			T45	7		T81	3		T364	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	10	1			T351	7		T113	2		T370	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	10	1			T371	3		T372	1		T373	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	114	1			T45	6		T47	4		T127	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	37	1			T34	2		T356	8		T374	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T46	3		T132	4		T361	9
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	21	1			T81	3		T264	2		T273	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T375	4		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T376	2		T354	6		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	77	1			T262	2		T263	16		T153	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	10	1			T125	1		T264	6		T376	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	17	1			T27	1		T113	1		T377	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T27	1		T113	1		T373	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	8	1			T351	7		T378	1		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T376	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T379	1		T354	6		T380	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	52	1			T45	3		T47	4		T263	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T350	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T381	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T28	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	8	1			T382	8		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T266	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

132

1

T1

8

T35

12

T131

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

118

1

T45

3

T81

3

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

71

1

T3

3

T192

3

T383

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

154

1

T28

14

T32

6

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

53

1

T262

2

T111

5

T314

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T6

3

T126

2

T264

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T49

2

T135

4

T371

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

125

1

T1

1

T3

9

T27

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T10

4

T23

1

T135

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

69

1

T5

8

T32

1

T45

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T49

2

T111

3

T201

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

93

1

T27

1

T135

7

T268

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T274

4

T319

3

T384

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T123

1

T62

1

T202

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T3

1

T123

1

T126

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

139

1

T5

9

T45

6

T192

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

79

1

T46

3

T268

3

T262

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T34

1

T118

1

T351

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T3

2

T35

6

T81

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T320

3

T361

9

T181

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

42

1

T6

3

T23

1

T62

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T137

1

T144

2

T156

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T137

1

T126

3

T270

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T46

5

T126

3

T202

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

41

1

T1

3

T5

4

T10

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T34

1

T137

1

T385

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T49

2

T35

3

T181

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T46

6

T62

1

T144

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T274

3

T275

2

T386

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T348

1

T319

2

T118

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T269

1

T296

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded