Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114923

1

T4

53

T1

391

T2

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137119	1			T4	37		T1	586		T2	6
values[0x0]	64199	1			T4	43		T1	117		T2	2
values[0x1]	65405	1			T4	53		T1	117		T2	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144184

1

T4

67

T1

456

T2

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	817	1			T27	1		T74	1		T49	5
valid_sources[0x01]	966	1			T27	5		T55	3		T74	1
valid_sources[0x02]	933	1			T15	1		T27	4		T28	3
valid_sources[0x03]	1040	1			T13	3		T27	2		T55	1
valid_sources[0x04]	954	1			T15	2		T27	2		T74	2
valid_sources[0x05]	861	1			T4	3		T15	2		T27	5
valid_sources[0x06]	1839	1			T15	3		T27	2		T56	2
valid_sources[0x07]	1322	1			T13	1		T15	1		T27	3
valid_sources[0x08]	817	1			T15	1		T27	5		T6	1
valid_sources[0x09]	973	1			T13	2		T15	1		T27	3
valid_sources[0x0a]	1164	1			T13	1		T15	5		T27	5
valid_sources[0x0b]	2055	1			T15	1		T27	6		T6	39
valid_sources[0x0c]	704	1			T15	2		T27	3		T28	5
valid_sources[0x0d]	1168	1			T27	1		T74	1		T49	3
valid_sources[0x0e]	841	1			T1	20		T15	1		T27	2
valid_sources[0x0f]	1158	1			T15	1		T27	6		T49	2
valid_sources[0x10]	779	1			T27	4		T74	1		T28	2
valid_sources[0x11]	777	1			T4	2		T27	5		T28	2
valid_sources[0x12]	955	1			T15	3		T27	3		T28	4
valid_sources[0x13]	922	1			T14	6		T15	2		T27	3
valid_sources[0x14]	904	1			T4	2		T15	2		T27	7
valid_sources[0x15]	909	1			T13	2		T15	1		T27	4
valid_sources[0x16]	960	1			T15	1		T27	3		T6	51
valid_sources[0x17]	1871	1			T15	3		T27	2		T55	2
valid_sources[0x18]	850	1			T13	1		T27	2		T55	2
valid_sources[0x19]	751	1			T14	3		T27	3		T56	1
valid_sources[0x1a]	957	1			T1	20		T15	4		T27	4
valid_sources[0x1b]	1047	1			T15	1		T27	2		T6	16
valid_sources[0x1c]	795	1			T4	6		T15	2		T27	4
valid_sources[0x1d]	942	1			T14	1		T15	1		T27	3
valid_sources[0x1e]	791	1			T13	3		T15	1		T27	1
valid_sources[0x1f]	894	1			T14	1		T27	5		T74	1
valid_sources[0x20]	1751	1			T2	1		T27	2		T6	19
valid_sources[0x21]	1717	1			T15	1		T17	1		T27	10
valid_sources[0x22]	952	1			T13	4		T14	4		T27	3
valid_sources[0x23]	907	1			T15	1		T28	6		T32	3
valid_sources[0x24]	821	1			T12	4		T13	3		T15	1
valid_sources[0x25]	945	1			T1	6		T15	3		T27	5
valid_sources[0x26]	847	1			T27	3		T49	4		T28	5
valid_sources[0x27]	1714	1			T15	2		T27	5		T49	3
valid_sources[0x28]	1188	1			T15	1		T27	2		T55	1
valid_sources[0x29]	856	1			T13	3		T15	2		T27	2
valid_sources[0x2a]	973	1			T15	5		T27	5		T49	1
valid_sources[0x2b]	963	1			T27	8		T28	2		T32	2
valid_sources[0x2c]	1353	1			T4	5		T13	1		T6	8
valid_sources[0x2d]	1136	1			T13	1		T17	1		T49	2
valid_sources[0x2e]	926	1			T15	3		T55	1		T74	1
valid_sources[0x2f]	1520	1			T15	2		T27	4		T26	5
valid_sources[0x30]	897	1			T15	1		T27	5		T56	1
valid_sources[0x31]	1047	1			T13	4		T15	1		T27	2
valid_sources[0x32]	842	1			T15	5		T27	5		T49	1
valid_sources[0x33]	1021	1			T15	1		T28	5		T32	2
valid_sources[0x34]	873	1			T15	3		T27	3		T28	6
valid_sources[0x35]	1629	1			T15	1		T27	5		T56	1
valid_sources[0x36]	922	1			T4	2		T14	2		T15	1
valid_sources[0x37]	907	1			T15	2		T27	7		T6	5
valid_sources[0x38]	798	1			T15	3		T27	5		T49	4
valid_sources[0x39]	1084	1			T27	7		T28	1		T32	3
valid_sources[0x3a]	1043	1			T27	4		T6	6		T74	1
valid_sources[0x3b]	877	1			T27	6		T103	1		T49	3
valid_sources[0x3c]	776	1			T2	1		T15	6		T27	1
valid_sources[0x3d]	866	1			T15	1		T27	2		T6	35
valid_sources[0x3e]	1478	1			T4	4		T15	1		T27	4
valid_sources[0x3f]	1276	1			T27	1		T74	1		T28	5
valid_sources[0x40]	676	1			T27	3		T74	4		T28	4
valid_sources[0x41]	769	1			T13	2		T15	2		T74	1
valid_sources[0x42]	940	1			T15	1		T17	1		T27	3
valid_sources[0x43]	1413	1			T15	2		T27	1		T26	10
valid_sources[0x44]	2845	1			T27	2		T28	10		T32	1
valid_sources[0x45]	856	1			T2	1		T15	2		T16	1
valid_sources[0x46]	810	1			T15	1		T27	3		T103	1
valid_sources[0x47]	936	1			T15	1		T27	2		T74	1
valid_sources[0x48]	821	1			T15	1		T27	3		T28	1
valid_sources[0x49]	1751	1			T13	2		T15	3		T27	5
valid_sources[0x4a]	945	1			T15	1		T27	12		T55	2
valid_sources[0x4b]	964	1			T13	2		T15	1		T27	1
valid_sources[0x4c]	1119	1			T13	1		T15	2		T27	5
valid_sources[0x4d]	904	1			T15	2		T27	6		T74	2
valid_sources[0x4e]	693	1			T13	1		T15	1		T27	2
valid_sources[0x4f]	825	1			T13	3		T27	1		T49	5
valid_sources[0x50]	914	1			T13	2		T15	2		T27	1
valid_sources[0x51]	907	1			T17	1		T27	4		T26	1
valid_sources[0x52]	962	1			T4	5		T15	2		T26	2
valid_sources[0x53]	858	1			T15	4		T27	3		T49	4
valid_sources[0x54]	984	1			T15	3		T27	8		T28	4
valid_sources[0x55]	984	1			T15	2		T27	3		T26	4
valid_sources[0x56]	916	1			T1	20		T15	2		T27	3
valid_sources[0x57]	884	1			T15	2		T27	7		T56	1
valid_sources[0x58]	961	1			T13	4		T14	2		T15	1
valid_sources[0x59]	1115	1			T15	1		T27	2		T49	1
valid_sources[0x5a]	781	1			T15	4		T27	2		T49	10
valid_sources[0x5b]	1050	1			T13	1		T27	3		T74	1
valid_sources[0x5c]	859	1			T15	4		T27	3		T6	24
valid_sources[0x5d]	874	1			T15	4		T27	5		T28	6
valid_sources[0x5e]	1978	1			T4	5		T13	3		T15	1
valid_sources[0x5f]	829	1			T27	3		T49	2		T28	5
valid_sources[0x60]	744	1			T15	3		T27	2		T74	1
valid_sources[0x61]	836	1			T27	4		T74	1		T49	1
valid_sources[0x62]	918	1			T15	3		T27	2		T6	6
valid_sources[0x63]	1057	1			T15	2		T27	6		T7	3
valid_sources[0x64]	726	1			T4	3		T55	1		T74	1
valid_sources[0x65]	1870	1			T15	1		T27	1		T6	1
valid_sources[0x66]	937	1			T12	2		T15	3		T27	8
valid_sources[0x67]	886	1			T13	5		T15	7		T27	9
valid_sources[0x68]	949	1			T15	1		T27	4		T55	1
valid_sources[0x69]	763	1			T28	6		T32	8		T45	3
valid_sources[0x6a]	885	1			T4	4		T13	1		T15	5
valid_sources[0x6b]	1450	1			T1	20		T15	1		T27	3
valid_sources[0x6c]	956	1			T15	1		T27	3		T74	1
valid_sources[0x6d]	855	1			T15	2		T27	1		T26	16
valid_sources[0x6e]	801	1			T13	4		T15	1		T27	2
valid_sources[0x6f]	869	1			T15	2		T27	4		T49	5
valid_sources[0x70]	1043	1			T4	7		T15	1		T27	3
valid_sources[0x71]	883	1			T15	1		T27	4		T74	1
valid_sources[0x72]	830	1			T15	1		T27	5		T49	3
valid_sources[0x73]	804	1			T15	2		T27	5		T6	14
valid_sources[0x74]	1002	1			T13	1		T15	3		T27	3
valid_sources[0x75]	895	1			T13	4		T27	3		T74	2
valid_sources[0x76]	993	1			T27	7		T103	1		T49	1
valid_sources[0x77]	1019	1			T74	2		T49	7		T28	10
valid_sources[0x78]	828	1			T15	1		T27	4		T49	6
valid_sources[0x79]	1037	1			T15	2		T27	4		T55	1
valid_sources[0x7a]	725	1			T13	1		T15	2		T27	3
valid_sources[0x7b]	920	1			T27	5		T26	5		T28	6
valid_sources[0x7c]	1093	1			T4	1		T13	1		T15	1
valid_sources[0x7d]	1398	1			T14	4		T15	1		T49	3
valid_sources[0x7e]	899	1			T15	3		T27	7		T49	1
valid_sources[0x7f]	750	1			T15	6		T27	2		T55	1
valid_sources[0x80]	828	1			T15	1		T27	2		T49	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60851

1

T4

18

T1

281

T2

3

values[0x0]

all_enables

biggest_size

31584

1

T4

24

T1

66

T12

2

values[0x1]

all_enables

biggest_size

22488

1

T4

11

T1

44

T12

1