Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T1,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T12
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T48
0	1	Covered	T4
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T48
0	1	Covered	T1,T12,T48
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T48
1	-	Covered	T1,T12,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T1,T12
DetectSt	168	Covered	T4,T1,T12
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T12,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T1,T12
DebounceSt->IdleSt	163	Covered	T4,T12,T25
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T1,T12,T48
IdleSt->DebounceSt	148	Covered	T4,T1,T12
StableSt->IdleSt	206	Covered	T1,T12,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T1,T12
0	1	Covered	T4,T1,T12
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T12
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T1,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T1,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T12,T23
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T1,T12
DetectSt	-	-	-	-	1	-	-	Covered	T4
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T48
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	336	0	0
CntIncr_A	7986755	283959	0	0
CntNoWrap_A	7986755	7325578	0	0
DetectStDropOut_A	7986755	1	0	0
DetectedOut_A	7986755	1040	0	0
DetectedPulseOut_A	7986755	155	0	0
DisabledIdleSt_A	7986755	7033894	0	0
DisabledNoDetection_A	7986755	7036214	0	0
EnterDebounceSt_A	7986755	184	0	0
EnterDetectSt_A	7986755	156	0	0
EnterStableSt_A	7986755	155	0	0
PulseIsPulse_A	7986755	155	0	0
StayInStableSt	7986755	885	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6931	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	154	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	336	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T4	2408	3	0	0
T12	62930	5	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	11	0	0
T48	0	4	0	0
T51	0	6	0	0
T53	0	2	0	0
T54	0	4	0	0
T121	0	3	0	0
T122	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	283959	0	0
T1	28580	80	0	0
T2	606	0	0	0
T3	29349	0	0	0
T4	2408	29	0	0
T12	62930	62415	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	312	0	0
T25	0	452	0	0
T48	0	40	0	0
T51	0	103	0	0
T53	0	74	0	0
T54	0	114	0	0
T121	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325578	0	0
T1	28580	24460	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	401	0	0
T12	62930	62524	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1	0	0
T1	28580	0	0	0
T2	606	0	0	0
T3	29349	0	0	0
T4	2408	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1040	0	0
T1	28580	9	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	11	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	36	0	0
T48	0	15	0	0
T51	0	10	0	0
T53	0	3	0	0
T54	0	12	0	0
T121	0	11	0	0
T122	0	7	0	0
T136	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	155	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	2	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	5	0	0
T48	0	2	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7033894	0	0
T1	28580	24328	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	310	0	0
T12	62930	3	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7036214	0	0
T1	28580	24350	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	313	0	0
T12	62930	3	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	184	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T4	2408	2	0	0
T12	62930	3	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	6	0	0
T25	0	1	0	0
T48	0	2	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T121	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	156	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T4	2408	1	0	0
T12	62930	2	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	5	0	0
T48	0	2	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	155	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	2	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	5	0	0
T48	0	2	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	155	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	2	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	5	0	0
T48	0	2	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	885	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	9	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	31	0	0
T48	0	13	0	0
T51	0	7	0	0
T53	0	2	0	0
T54	0	10	0	0
T121	0	10	0	0
T122	0	5	0	0
T136	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6931	0	0
T1	28580	33	0	0
T2	606	0	0	0
T3	29349	14	0	0
T4	2408	15	0	0
T5	0	9	0	0
T12	62930	3	0	0
T13	506	5	0	0
T14	524	6	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	4	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	154	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	2	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	5	0	0
T48	0	2	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0
T136	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T22,T23,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T12
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T62
0	1	Covered	T118,T119,T120
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T62
0	1	Unreachable
1	0	Covered	T22,T23,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T23,T62
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T22,T23,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T62
DebounceSt->IdleSt	163	Covered	T24,T40,T83
DetectSt->IdleSt	186	Covered	T118,T119,T120
DetectSt->StableSt	191	Covered	T22,T23,T62
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T22,T23,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T62
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T83,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T118,T119,T120
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T62
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	161	0	0
CntIncr_A	7986755	4587	0	0
CntNoWrap_A	7986755	7325753	0	0
DetectStDropOut_A	7986755	13	0	0
DetectedOut_A	7986755	9460	0	0
DetectedPulseOut_A	7986755	51	0	0
DisabledIdleSt_A	7986755	5833248	0	0
DisabledNoDetection_A	7986755	5835632	0	0
EnterDebounceSt_A	7986755	98	0	0
EnterDetectSt_A	7986755	64	0	0
EnterStableSt_A	7986755	51	0	0
PulseIsPulse_A	7986755	51	0	0
StayInStableSt	7986755	9409	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6931	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_sticky_sva.StableStDropOut_A	7986755	1243064	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	161	0	0
T22	583	2	0	0
T23	40884	2	0	0
T24	0	2	0	0
T35	10526	0	0	0
T40	0	2	0	0
T54	696	0	0	0
T62	0	2	0	0
T63	0	4	0	0
T69	491	0	0	0
T82	0	2	0	0
T83	0	3	0	0
T84	0	4	0	0
T85	0	4	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	4587	0	0
T22	583	75	0	0
T23	40884	92	0	0
T24	0	174	0	0
T35	10526	0	0	0
T40	0	54	0	0
T54	696	0	0	0
T62	0	33	0	0
T63	0	148	0	0
T69	491	0	0	0
T82	0	38	0	0
T83	0	146	0	0
T84	0	38	0	0
T85	0	58	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325753	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	13	0	0
T114	0	4	0	0
T118	15102	1	0	0
T119	0	1	0	0
T120	0	5	0	0
T131	30248	0	0	0
T148	0	2	0	0
T149	432	0	0	0
T150	492	0	0	0
T151	528	0	0	0
T152	4616	0	0	0
T153	14852	0	0	0
T154	422	0	0	0
T155	704	0	0	0
T156	29378	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	9460	0	0
T22	583	1	0	0
T23	40884	420	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	164	0	0
T63	0	795	0	0
T69	491	0	0	0
T82	0	187	0	0
T83	0	75	0	0
T84	0	91	0	0
T85	0	506	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T138	0	342	0	0
T140	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	51	0	0
T22	583	1	0	0
T23	40884	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T138	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5833248	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5835632	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	98	0	0
T22	583	1	0	0
T23	40884	1	0	0
T24	0	2	0	0
T35	10526	0	0	0
T40	0	2	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	64	0	0
T22	583	1	0	0
T23	40884	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	51	0	0
T22	583	1	0	0
T23	40884	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T138	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	51	0	0
T22	583	1	0	0
T23	40884	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T138	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	9409	0	0
T23	40884	419	0	0
T24	810	0	0	0
T36	276096	0	0	0
T44	3836	0	0	0
T62	0	163	0	0
T63	0	793	0	0
T70	498	0	0	0
T77	684	0	0	0
T79	467	0	0	0
T82	0	186	0	0
T83	0	74	0	0
T84	0	89	0	0
T85	0	504	0	0
T138	0	341	0	0
T140	0	36	0	0
T143	0	206	0	0
T157	424	0	0	0
T158	728	0	0	0
T159	526	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6931	0	0
T1	28580	33	0	0
T2	606	0	0	0
T3	29349	14	0	0
T4	2408	15	0	0
T5	0	9	0	0
T12	62930	3	0	0
T13	506	5	0	0
T14	524	6	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	4	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1243064	0	0
T22	583	57	0	0
T23	40884	128	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	341	0	0
T63	0	197	0	0
T69	491	0	0	0
T82	0	204	0	0
T83	0	21592	0	0
T84	0	330	0	0
T85	0	480617	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T138	0	141	0	0
T140	0	151	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T22,T24,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T2
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T63,T82,T84
0	1	Covered	T22,T24,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T63,T82,T84
0	1	Unreachable
1	0	Covered	T63,T82,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T24,T63
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T63,T82,T84

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T24,T63
DebounceSt->IdleSt	163	Covered	T23,T62,T40
DetectSt->IdleSt	186	Covered	T22,T24,T117
DetectSt->StableSt	191	Covered	T63,T82,T84
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T63,T82,T84

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T24,T63
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T24,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T62,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T22,T24,T117
DetectSt	-	-	-	-	0	1	-	Covered	T63,T82,T84
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T63,T82,T84
StableSt	-	-	-	-	-	-	0	Covered	T63,T82,T84
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	189	0	0
CntIncr_A	7986755	154544	0	0
CntNoWrap_A	7986755	7325725	0	0
DetectStDropOut_A	7986755	16	0	0
DetectedOut_A	7986755	404573	0	0
DetectedPulseOut_A	7986755	40	0	0
DisabledIdleSt_A	7986755	5833248	0	0
DisabledNoDetection_A	7986755	5835632	0	0
EnterDebounceSt_A	7986755	134	0	0
EnterDetectSt_A	7986755	56	0	0
EnterStableSt_A	7986755	40	0	0
PulseIsPulse_A	7986755	40	0	0
StayInStableSt	7986755	404533	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_sticky_sva.StableStDropOut_A	7986755	431246	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	189	0	0
T22	583	2	0	0
T23	40884	4	0	0
T24	0	4	0	0
T35	10526	0	0	0
T40	0	2	0	0
T54	696	0	0	0
T62	0	4	0	0
T63	0	4	0	0
T69	491	0	0	0
T82	0	2	0	0
T83	0	3	0	0
T84	0	4	0	0
T85	0	10	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	154544	0	0
T22	583	78	0	0
T23	40884	76	0	0
T24	0	136	0	0
T35	10526	0	0	0
T40	0	53	0	0
T54	696	0	0	0
T62	0	324	0	0
T63	0	68	0	0
T69	491	0	0	0
T82	0	82	0	0
T83	0	32535	0	0
T84	0	144	0	0
T85	0	420	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325725	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	16	0	0
T22	583	1	0	0
T23	40884	0	0	0
T24	0	2	0	0
T35	10526	0	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T117	0	1	0	0
T160	0	4	0	0
T161	0	5	0	0
T162	0	1	0	0
T163	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	404573	0	0
T63	1867	506	0	0
T64	883	0	0	0
T80	5566	0	0	0
T82	0	251	0	0
T84	0	227	0	0
T119	0	157	0	0
T121	697	0	0	0
T122	637	0	0	0
T136	646	0	0	0
T138	0	46	0	0
T139	0	3	0	0
T140	0	68	0	0
T141	0	30	0	0
T142	0	41	0	0
T143	0	356	0	0
T144	18214	0	0	0
T145	426	0	0	0
T146	522	0	0	0
T147	646	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T63	1867	2	0	0
T64	883	0	0	0
T80	5566	0	0	0
T82	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0
T121	697	0	0	0
T122	637	0	0	0
T136	646	0	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	18214	0	0	0
T145	426	0	0	0
T146	522	0	0	0
T147	646	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5833248	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5835632	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	134	0	0
T22	583	1	0	0
T23	40884	4	0	0
T24	0	2	0	0
T35	10526	0	0	0
T40	0	2	0	0
T54	696	0	0	0
T62	0	4	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	10	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	56	0	0
T22	583	1	0	0
T23	40884	0	0	0
T24	0	2	0	0
T35	10526	0	0	0
T54	696	0	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	1	0	0
T84	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T117	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T63	1867	2	0	0
T64	883	0	0	0
T80	5566	0	0	0
T82	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0
T121	697	0	0	0
T122	637	0	0	0
T136	646	0	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	18214	0	0	0
T145	426	0	0	0
T146	522	0	0	0
T147	646	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T63	1867	2	0	0
T64	883	0	0	0
T80	5566	0	0	0
T82	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0
T121	697	0	0	0
T122	637	0	0	0
T136	646	0	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	18214	0	0	0
T145	426	0	0	0
T146	522	0	0	0
T147	646	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	404533	0	0
T63	1867	504	0	0
T64	883	0	0	0
T80	5566	0	0	0
T82	0	250	0	0
T84	0	225	0	0
T119	0	156	0	0
T121	697	0	0	0
T122	637	0	0	0
T136	646	0	0	0
T138	0	45	0	0
T139	0	2	0	0
T140	0	67	0	0
T141	0	29	0	0
T142	0	40	0	0
T143	0	355	0	0
T144	18214	0	0	0
T145	426	0	0	0
T146	522	0	0	0
T147	646	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	431246	0	0
T63	1867	577	0	0
T64	883	0	0	0
T80	5566	0	0	0
T82	0	103	0	0
T84	0	87	0	0
T119	0	55	0	0
T121	697	0	0	0
T122	637	0	0	0
T136	646	0	0	0
T138	0	526	0	0
T139	0	87	0	0
T140	0	114	0	0
T141	0	23179	0	0
T142	0	26	0	0
T143	0	100	0	0
T144	18214	0	0	0
T145	426	0	0	0
T146	522	0	0	0
T147	646	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T22,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T2
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T84,T114,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Unreachable
1	0	Covered	T22,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T23,T24
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T22,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T24
DebounceSt->IdleSt	163	Covered	T82,T40,T84
DetectSt->IdleSt	186	Covered	T84,T114,T115
DetectSt->StableSt	191	Covered	T22,T23,T24
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T84,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T84,T114,T115
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	157	0	0
CntIncr_A	7986755	173899	0	0
CntNoWrap_A	7986755	7325757	0	0
DetectStDropOut_A	7986755	6	0	0
DetectedOut_A	7986755	762067	0	0
DetectedPulseOut_A	7986755	44	0	0
DisabledIdleSt_A	7986755	5833248	0	0
DisabledNoDetection_A	7986755	5835632	0	0
EnterDebounceSt_A	7986755	108	0	0
EnterDetectSt_A	7986755	50	0	0
EnterStableSt_A	7986755	44	0	0
PulseIsPulse_A	7986755	44	0	0
StayInStableSt	7986755	762023	0	0
gen_high_event_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_sticky_sva.StableStDropOut_A	7986755	460989	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	157	0	0
T22	583	2	0	0
T23	40884	2	0	0
T24	0	2	0	0
T35	10526	0	0	0
T40	0	2	0	0
T54	696	0	0	0
T62	0	2	0	0
T63	0	4	0	0
T69	491	0	0	0
T82	0	4	0	0
T83	0	2	0	0
T84	0	7	0	0
T85	0	4	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	173899	0	0
T22	583	64	0	0
T23	40884	55	0	0
T24	0	71	0	0
T35	10526	0	0	0
T40	0	53	0	0
T54	696	0	0	0
T62	0	89	0	0
T63	0	54	0	0
T69	491	0	0	0
T82	0	388	0	0
T83	0	70	0	0
T84	0	192	0	0
T85	0	53578	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325757	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6	0	0
T84	939	2	0	0
T85	529788	0	0	0
T114	0	3	0	0
T115	0	1	0	0
T128	5065	0	0	0
T164	424	0	0	0
T165	799	0	0	0
T166	502	0	0	0
T167	410	0	0	0
T168	402	0	0	0
T169	33896	0	0	0
T170	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	762067	0	0
T22	583	47	0	0
T23	40884	335	0	0
T24	0	203	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	362	0	0
T63	0	204	0	0
T69	491	0	0	0
T83	0	270	0	0
T84	0	1	0	0
T85	0	427476	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	38	0	0
T138	0	454	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	44	0	0
T22	583	1	0	0
T23	40884	1	0	0
T24	0	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5833248	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5835632	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	108	0	0
T22	583	1	0	0
T23	40884	1	0	0
T24	0	1	0	0
T35	10526	0	0	0
T40	0	2	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T82	0	4	0	0
T83	0	1	0	0
T84	0	4	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	50	0	0
T22	583	1	0	0
T23	40884	1	0	0
T24	0	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T83	0	1	0	0
T84	0	3	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	44	0	0
T22	583	1	0	0
T23	40884	1	0	0
T24	0	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	44	0	0
T22	583	1	0	0
T23	40884	1	0	0
T24	0	1	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T69	491	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	762023	0	0
T22	583	46	0	0
T23	40884	334	0	0
T24	0	202	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	361	0	0
T63	0	202	0	0
T69	491	0	0	0
T83	0	269	0	0
T85	0	427474	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	37	0	0
T138	0	453	0	0
T140	0	131	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	460989	0	0
T22	583	31	0	0
T23	40884	265	0	0
T24	0	99	0	0
T35	10526	0	0	0
T54	696	0	0	0
T62	0	89	0	0
T63	0	904	0	0
T69	491	0	0	0
T83	0	32271	0	0
T84	0	84	0	0
T85	0	140	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T89	981	0	0	0
T90	422	0	0	0
T118	0	38	0	0
T138	0	53	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T11,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T11,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T11,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T11,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T37
0	1	Covered	T116,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T37
0	1	Covered	T1,T11,T37
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T37
1	-	Covered	T1,T11,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T37
DetectSt	168	Covered	T1,T11,T37
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T11,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T37
DebounceSt->IdleSt	163	Covered	T172,T60,T173
DetectSt->IdleSt	186	Covered	T116,T171
DetectSt->StableSt	191	Covered	T1,T11,T37
IdleSt->DebounceSt	148	Covered	T1,T11,T37
StableSt->IdleSt	206	Covered	T1,T11,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T37
0	1	Covered	T1,T11,T37
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T37
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T172
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T37
DetectSt	-	-	-	-	1	-	-	Covered	T116,T171
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T37
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	74	0	0
CntIncr_A	7986755	61153	0	0
CntNoWrap_A	7986755	7325840	0	0
DetectStDropOut_A	7986755	2	0	0
DetectedOut_A	7986755	5052	0	0
DetectedPulseOut_A	7986755	34	0	0
DisabledIdleSt_A	7986755	6869593	0	0
DisabledNoDetection_A	7986755	6871920	0	0
EnterDebounceSt_A	7986755	39	0	0
EnterDetectSt_A	7986755	36	0	0
EnterStableSt_A	7986755	34	0	0
PulseIsPulse_A	7986755	34	0	0
StayInStableSt	7986755	5001	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	74	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	2	0	0
T40	0	2	0	0
T111	0	4	0	0
T116	0	2	0	0
T172	0	3	0	0
T174	0	4	0	0
T175	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61153	0	0
T1	28580	176	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	170	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	2530	0	0
T40	0	23	0	0
T111	0	68	0	0
T116	0	74	0	0
T172	0	72	0	0
T174	0	133	0	0
T175	0	43	0	0
T176	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325840	0	0
T1	28580	24458	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2	0	0
T116	804	1	0	0
T171	0	1	0	0
T177	422	0	0	0
T178	500	0	0	0
T179	409	0	0	0
T180	849	0	0	0
T181	10099	0	0	0
T182	490	0	0	0
T183	535	0	0	0
T184	828	0	0	0
T185	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5052	0	0
T1	28580	67	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	86	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	2963	0	0
T40	0	23	0	0
T111	0	138	0	0
T172	0	84	0	0
T174	0	151	0	0
T175	0	28	0	0
T176	0	47	0	0
T186	0	139	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T111	0	2	0	0
T172	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6869593	0	0
T1	28580	23701	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6871920	0	0
T1	28580	23722	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	39	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T111	0	2	0	0
T116	0	1	0	0
T172	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	36	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T111	0	2	0	0
T116	0	1	0	0
T172	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T111	0	2	0	0
T172	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T111	0	2	0	0
T172	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5001	0	0
T1	28580	64	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	83	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	2962	0	0
T40	0	22	0	0
T111	0	136	0	0
T172	0	83	0	0
T174	0	147	0	0
T175	0	27	0	0
T176	0	45	0	0
T186	0	137	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	16	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T37	0	1	0	0
T111	0	2	0	0
T172	0	1	0	0
T175	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T1,T13
1	1	Covered	T1,T2,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T36
0	1	Covered	T11,T111,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T36
0	1	Covered	T1,T39,T43
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T36
1	-	Covered	T1,T39,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T11
DetectSt	168	Covered	T1,T2,T11
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T2,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T11
DebounceSt->IdleSt	163	Covered	T36,T62,T39
DetectSt->IdleSt	186	Covered	T11,T111,T186
DetectSt->StableSt	191	Covered	T1,T2,T36
IdleSt->DebounceSt	148	Covered	T1,T2,T11
StableSt->IdleSt	206	Covered	T1,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T11
0	1	Covered	T1,T2,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T62,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T111,T186
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	144	0	0
CntIncr_A	7986755	141184	0	0
CntNoWrap_A	7986755	7325770	0	0
DetectStDropOut_A	7986755	4	0	0
DetectedOut_A	7986755	61818	0	0
DetectedPulseOut_A	7986755	65	0	0
DisabledIdleSt_A	7986755	6817237	0	0
DisabledNoDetection_A	7986755	6819567	0	0
EnterDebounceSt_A	7986755	75	0	0
EnterDetectSt_A	7986755	69	0	0
EnterStableSt_A	7986755	65	0	0
PulseIsPulse_A	7986755	65	0	0
StayInStableSt	7986755	61721	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	2647	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	144	0	0
T1	28580	4	0	0
T2	606	2	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	3	0	0
T38	0	2	0	0
T39	0	3	0	0
T40	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	141184	0	0
T1	28580	176	0	0
T2	606	76	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	170	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	86976	0	0
T38	0	86	0	0
T39	0	110	0	0
T40	0	23	0	0
T43	0	136	0	0
T62	0	65	0	0
T78	0	49976	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325770	0	0
T1	28580	24458	0	0
T2	606	203	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	4	0	0
T11	839	2	0	0
T25	4430	0	0	0
T33	1602	0	0	0
T34	8787	0	0	0
T53	771	0	0	0
T68	402	0	0	0
T75	521	0	0	0
T76	527	0	0	0
T111	0	1	0	0
T186	0	1	0	0
T191	504	0	0	0
T192	27259	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61818	0	0
T1	28580	245	0	0
T2	606	120	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	42	0	0
T38	0	45	0	0
T39	0	47	0	0
T40	0	23	0	0
T43	0	107	0	0
T78	0	55963	0	0
T193	0	93	0	0
T194	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	65	0	0
T1	28580	2	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T78	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6817237	0	0
T1	28580	23701	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6819567	0	0
T1	28580	23722	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	75	0	0
T1	28580	2	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T62	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	69	0	0
T1	28580	2	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T78	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	65	0	0
T1	28580	2	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T78	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	65	0	0
T1	28580	2	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T78	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61721	0	0
T1	28580	243	0	0
T2	606	118	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	40	0	0
T38	0	43	0	0
T39	0	46	0	0
T40	0	22	0	0
T43	0	104	0	0
T78	0	55961	0	0
T193	0	92	0	0
T194	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2647	0	0
T1	28580	17	0	0
T2	606	1	0	0
T3	29349	0	0	0
T4	2408	10	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	62930	0	0	0
T13	506	5	0	0
T14	524	6	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	7	0	0
T55	0	6	0	0
T74	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	32	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T111	0	1	0	0
T118	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0