Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T36
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T7,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T36
0	1	Covered	T111,T187
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T36
0	1	Covered	T7,T36,T111
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T36
1	-	Covered	T7,T36,T111

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T36
DetectSt	168	Covered	T2,T7,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T36
DebounceSt->IdleSt	163	Covered	T195,T196
DetectSt->IdleSt	186	Covered	T111,T60,T187
DetectSt->StableSt	191	Covered	T2,T7,T36
IdleSt->DebounceSt	148	Covered	T2,T7,T36
StableSt->IdleSt	206	Covered	T7,T36,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T36
0	1	Covered	T2,T7,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T196
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T36
DetectSt	-	-	-	-	1	-	-	Covered	T111,T60,T187
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T36,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	103	0	0
CntIncr_A	7986755	89788	0	0
CntNoWrap_A	7986755	7325811	0	0
DetectStDropOut_A	7986755	2	0	0
DetectedOut_A	7986755	90147	0	0
DetectedPulseOut_A	7986755	48	0	0
DisabledIdleSt_A	7986755	6717111	0	0
DisabledNoDetection_A	7986755	6719429	0	0
EnterDebounceSt_A	7986755	53	0	0
EnterDetectSt_A	7986755	51	0	0
EnterStableSt_A	7986755	48	0	0
PulseIsPulse_A	7986755	48	0	0
StayInStableSt	7986755	90071	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	103	0	0
T2	606	2	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	4	0	0
T40	0	2	0	0
T42	0	2	0	0
T77	0	2	0	0
T111	0	4	0	0
T193	0	2	0	0
T197	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	89788	0	0
T2	606	76	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	13	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	86976	0	0
T40	0	23	0	0
T42	0	11	0	0
T77	0	87	0	0
T193	0	35	0	0
T195	0	10	0	0
T197	0	74	0	0
T198	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325811	0	0
T1	28580	24462	0	0
T2	606	203	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2	0	0
T41	788	0	0	0
T111	30144	1	0	0
T187	0	1	0	0
T199	3073	0	0	0
T200	2737	0	0	0
T201	16502	0	0	0
T202	19773	0	0	0
T203	5640	0	0	0
T204	511	0	0	0
T205	496	0	0	0
T206	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	90147	0	0
T2	606	43	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	40	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	87103	0	0
T40	0	24	0	0
T42	0	42	0	0
T77	0	38	0	0
T111	0	21	0	0
T193	0	89	0	0
T197	0	44	0	0
T198	0	277	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	48	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T77	0	1	0	0
T111	0	1	0	0
T193	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6717111	0	0
T1	28580	24462	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6719429	0	0
T1	28580	24484	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	53	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T77	0	1	0	0
T193	0	1	0	0
T195	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	51	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T77	0	1	0	0
T111	0	2	0	0
T193	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	48	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T77	0	1	0	0
T111	0	1	0	0
T193	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	48	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T77	0	1	0	0
T111	0	1	0	0
T193	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	90071	0	0
T2	606	41	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	39	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	87100	0	0
T40	0	23	0	0
T42	0	40	0	0
T77	0	36	0	0
T111	0	20	0	0
T193	0	87	0	0
T197	0	42	0	0
T198	0	275	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	19	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	0	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	1	0	0
T143	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T143,T210
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T2,T7,T42
1	0	Covered	T40,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T9
1	-	Covered	T2,T7,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T8
DetectSt	168	Covered	T2,T7,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T8
DebounceSt->IdleSt	163	Covered	T101,T197,T176
DetectSt->IdleSt	186	Covered	T143,T210
DetectSt->StableSt	191	Covered	T2,T7,T8
IdleSt->DebounceSt	148	Covered	T2,T7,T8
StableSt->IdleSt	206	Covered	T2,T7,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T197,T176,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T143,T210
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	137	0	0
CntIncr_A	7986755	180608	0	0
CntNoWrap_A	7986755	7325777	0	0
DetectStDropOut_A	7986755	3	0	0
DetectedOut_A	7986755	70676	0	0
DetectedPulseOut_A	7986755	62	0	0
DisabledIdleSt_A	7986755	6423635	0	0
DisabledNoDetection_A	7986755	6425960	0	0
EnterDebounceSt_A	7986755	73	0	0
EnterDetectSt_A	7986755	65	0	0
EnterStableSt_A	7986755	62	0	0
PulseIsPulse_A	7986755	62	0	0
StayInStableSt	7986755	70581	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	2981	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	137	0	0
T2	606	2	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T197	0	1	0	0
T211	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	180608	0	0
T2	606	76	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	26	0	0
T8	0	43	0	0
T9	0	46	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	23	0	0
T42	0	11	0	0
T43	0	136	0	0
T44	0	87	0	0
T101	0	501	0	0
T211	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325777	0	0
T1	28580	24462	0	0
T2	606	203	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	3	0	0
T120	1690	0	0	0
T143	16386	2	0	0
T210	0	1	0	0
T212	441	0	0	0
T213	15430	0	0	0
T214	494	0	0	0
T215	36340	0	0	0
T216	3718	0	0	0
T217	443	0	0	0
T218	616	0	0	0
T219	9744	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	70676	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	77	0	0
T8	0	46	0	0
T9	0	218	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	23	0	0
T42	0	148	0	0
T43	0	84	0	0
T44	0	313	0	0
T83	0	116	0	0
T211	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T83	0	3	0	0
T211	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6423635	0	0
T1	28580	24462	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6425960	0	0
T1	28580	24484	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	73	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T101	0	1	0	0
T211	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	65	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T83	0	3	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T83	0	3	0	0
T211	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T83	0	3	0	0
T211	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	70581	0	0
T7	568	74	0	0
T8	543	44	0	0
T9	765	216	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T40	0	22	0	0
T42	0	147	0	0
T43	0	81	0	0
T44	0	311	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T83	0	112	0	0
T126	0	39	0	0
T211	0	68	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2981	0	0
T1	28580	19	0	0
T2	606	1	0	0
T3	29349	0	0	0
T4	2408	10	0	0
T6	0	2	0	0
T7	0	2	0	0
T12	62930	0	0	0
T13	506	4	0	0
T14	524	6	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	4	0	0
T55	0	7	0	0
T74	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	27	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T7	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T83	0	2	0	0
T111	0	2	0	0
T172	0	2	0	0
T193	0	1	0	0
T195	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T8,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T8,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T8,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T44
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T8,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T44
0	1	Covered	T180,T186
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T44
0	1	Covered	T36,T39,T43
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T44
1	-	Covered	T36,T39,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T44
DetectSt	168	Covered	T2,T8,T44
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T8,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T44
DebounceSt->IdleSt	163	Covered	T39,T101,T190
DetectSt->IdleSt	186	Covered	T180,T186,T60
DetectSt->StableSt	191	Covered	T2,T8,T44
IdleSt->DebounceSt	148	Covered	T2,T8,T44
StableSt->IdleSt	206	Covered	T44,T36,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T44
0	1	Covered	T2,T8,T44
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T44
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T190,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T44
DetectSt	-	-	-	-	1	-	-	Covered	T180,T186,T60
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	133	0	0
CntIncr_A	7986755	190745	0	0
CntNoWrap_A	7986755	7325781	0	0
DetectStDropOut_A	7986755	2	0	0
DetectedOut_A	7986755	142557	0	0
DetectedPulseOut_A	7986755	61	0	0
DisabledIdleSt_A	7986755	6638265	0	0
DisabledNoDetection_A	7986755	6640594	0	0
EnterDebounceSt_A	7986755	70	0	0
EnterDetectSt_A	7986755	64	0	0
EnterStableSt_A	7986755	61	0	0
PulseIsPulse_A	7986755	61	0	0
StayInStableSt	7986755	142470	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	133	0	0
T2	606	2	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	4	0	0
T39	0	3	0	0
T40	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T211	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	190745	0	0
T2	606	76	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	43	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	86976	0	0
T39	0	110	0	0
T40	0	23	0	0
T43	0	136	0	0
T44	0	87	0	0
T77	0	87	0	0
T78	0	49976	0	0
T101	0	501	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325781	0	0
T1	28580	24462	0	0
T2	606	203	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2	0	0
T180	849	1	0	0
T181	10099	0	0	0
T182	490	0	0	0
T183	535	0	0	0
T184	828	0	0	0
T185	502	0	0	0
T186	0	1	0	0
T221	502	0	0	0
T222	491	0	0	0
T223	523	0	0	0
T224	13059	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	142557	0	0
T2	606	121	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	47	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	62712	0	0
T39	0	47	0	0
T40	0	22	0	0
T43	0	152	0	0
T44	0	183	0	0
T77	0	39	0	0
T78	0	55962	0	0
T211	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T211	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6638265	0	0
T1	28580	24462	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6640594	0	0
T1	28580	24484	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	70	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	64	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T211	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T211	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	142470	0	0
T2	606	119	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	45	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	62710	0	0
T39	0	46	0	0
T40	0	21	0	0
T43	0	150	0	0
T44	0	181	0	0
T77	0	37	0	0
T78	0	55960	0	0
T211	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T24	810	0	0	0
T36	276096	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T70	498	0	0	0
T77	684	0	0	0
T78	106348	0	0	0
T79	467	0	0	0
T83	0	1	0	0
T118	0	1	0	0
T135	32569	0	0	0
T143	0	1	0	0
T158	728	0	0	0
T159	526	0	0	0
T193	0	1	0	0
T198	0	1	0	0
T208	0	1	0	0
T225	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T4,T1,T13
1	1	Covered	T1,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T36
0	1	Not Covered
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T36
0	1	Covered	T1,T43,T176
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T36
1	-	Covered	T1,T43,T176

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T36
DetectSt	168	Covered	T1,T11,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T36
DebounceSt->IdleSt	163	Covered	T36
DetectSt->IdleSt	186	Covered	T60
DetectSt->StableSt	191	Covered	T1,T11,T36
IdleSt->DebounceSt	148	Covered	T1,T11,T36
StableSt->IdleSt	206	Covered	T1,T40,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T36
0	1	Covered	T1,T11,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T36
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T60
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T40,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	71	0	0
CntIncr_A	7986755	179906	0	0
CntNoWrap_A	7986755	7325843	0	0
DetectStDropOut_A	7986755	0	0	0
DetectedOut_A	7986755	29533	0	0
DetectedPulseOut_A	7986755	34	0	0
DisabledIdleSt_A	7986755	6440734	0	0
DisabledNoDetection_A	7986755	6443059	0	0
EnterDebounceSt_A	7986755	36	0	0
EnterDetectSt_A	7986755	35	0	0
EnterStableSt_A	7986755	34	0	0
PulseIsPulse_A	7986755	34	0	0
StayInStableSt	7986755	29478	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6576	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	3	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T62	0	2	0	0
T83	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	179906	0	0
T1	28580	88	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	85	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	86976	0	0
T40	0	23	0	0
T41	0	61	0	0
T42	0	11	0	0
T43	0	136	0	0
T62	0	65	0	0
T83	0	59	0	0
T176	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325843	0	0
T1	28580	24460	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	29533	0	0
T1	28580	154	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	46	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	43	0	0
T40	0	24	0	0
T41	0	42	0	0
T42	0	55	0	0
T43	0	108	0	0
T62	0	56	0	0
T83	0	310	0	0
T176	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T62	0	1	0	0
T83	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6440734	0	0
T1	28580	23701	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6443059	0	0
T1	28580	23722	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	36	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T62	0	1	0	0
T83	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	35	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T62	0	1	0	0
T83	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T62	0	1	0	0
T83	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	34	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T62	0	1	0	0
T83	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	29478	0	0
T1	28580	153	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	44	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T36	0	41	0	0
T40	0	23	0	0
T41	0	40	0	0
T42	0	53	0	0
T43	0	105	0	0
T62	0	54	0	0
T83	0	308	0	0
T176	0	122	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6576	0	0
T1	28580	37	0	0
T2	606	0	0	0
T3	29349	9	0	0
T4	2408	9	0	0
T5	0	14	0	0
T12	62930	0	0	0
T13	506	6	0	0
T14	524	4	0	0
T15	5211	24	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	6	0	0
T27	0	28	0	0
T55	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	12	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T43	0	1	0	0
T162	0	1	0	0
T176	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T180,T186,T230
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T9,T44,T43
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T11
1	-	Covered	T9,T44,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T11
DetectSt	168	Covered	T2,T9,T11
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T11
DebounceSt->IdleSt	163	Covered	T231,T207,T180
DetectSt->IdleSt	186	Covered	T180,T186,T60
DetectSt->StableSt	191	Covered	T2,T9,T11
IdleSt->DebounceSt	148	Covered	T2,T9,T11
StableSt->IdleSt	206	Covered	T9,T44,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T231,T207,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T180,T186,T60
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T44,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	142	0	0
CntIncr_A	7986755	246226	0	0
CntNoWrap_A	7986755	7325772	0	0
DetectStDropOut_A	7986755	5	0	0
DetectedOut_A	7986755	240295	0	0
DetectedPulseOut_A	7986755	62	0	0
DisabledIdleSt_A	7986755	6355014	0	0
DisabledNoDetection_A	7986755	6357341	0	0
EnterDebounceSt_A	7986755	74	0	0
EnterDetectSt_A	7986755	68	0	0
EnterStableSt_A	7986755	62	0	0
PulseIsPulse_A	7986755	62	0	0
StayInStableSt	7986755	240205	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	142	0	0
T2	606	2	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	4	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T78	0	2	0	0
T126	0	2	0	0
T197	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	246226	0	0
T2	606	76	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	92	0	0
T11	0	85	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	43488	0	0
T40	0	23	0	0
T43	0	136	0	0
T44	0	87	0	0
T78	0	49976	0	0
T126	0	44960	0	0
T197	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325772	0	0
T1	28580	24462	0	0
T2	606	203	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	5	0	0
T180	849	1	0	0
T181	10099	0	0	0
T182	490	0	0	0
T183	535	0	0	0
T184	828	0	0	0
T185	502	0	0	0
T186	0	1	0	0
T221	502	0	0	0
T222	491	0	0	0
T223	523	0	0	0
T224	13059	0	0	0
T229	0	1	0	0
T230	0	1	0	0
T232	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	240295	0	0
T2	606	120	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	87	0	0
T11	0	258	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	106202	0	0
T40	0	22	0	0
T43	0	155	0	0
T44	0	43	0	0
T78	0	55963	0	0
T126	0	40	0	0
T197	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T126	0	1	0	0
T197	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6355014	0	0
T1	28580	24462	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6357341	0	0
T1	28580	24484	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	74	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T126	0	1	0	0
T197	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	68	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T126	0	1	0	0
T197	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T126	0	1	0	0
T197	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T126	0	1	0	0
T197	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	240205	0	0
T2	606	118	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T9	0	84	0	0
T11	0	256	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	106200	0	0
T40	0	21	0	0
T43	0	153	0	0
T44	0	42	0	0
T78	0	55961	0	0
T126	0	38	0	0
T197	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	33	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T111	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T194	0	1	0	0
T207	0	1	0	0
T209	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T42,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T42,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T42,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T1,T13
1	1	Covered	T1,T42,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T42,T40
0	1	Not Covered
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T42,T40
0	1	Covered	T1,T43,T198
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T42,T40
1	-	Covered	T1,T43,T198

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T42,T40
DetectSt	168	Covered	T1,T42,T40
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T42,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T42,T40
DebounceSt->IdleSt	163	Covered	T143,T196
DetectSt->IdleSt	186	Covered	T60
DetectSt->StableSt	191	Covered	T1,T42,T40
IdleSt->DebounceSt	148	Covered	T1,T42,T40
StableSt->IdleSt	206	Covered	T1,T40,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T42,T40
0	1	Covered	T1,T42,T40
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T42,T40
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T42,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T42,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T143,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T42,T40
DetectSt	-	-	-	-	1	-	-	Covered	T60
DetectSt	-	-	-	-	0	1	-	Covered	T1,T42,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T40,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T42,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	100	0	0
CntIncr_A	7986755	3029	0	0
CntNoWrap_A	7986755	7325814	0	0
DetectStDropOut_A	7986755	0	0	0
DetectedOut_A	7986755	3298	0	0
DetectedPulseOut_A	7986755	48	0	0
DisabledIdleSt_A	7986755	6721048	0	0
DisabledNoDetection_A	7986755	6723370	0	0
EnterDebounceSt_A	7986755	51	0	0
EnterDetectSt_A	7986755	49	0	0
EnterStableSt_A	7986755	48	0	0
PulseIsPulse_A	7986755	48	0	0
StayInStableSt	7986755	3223	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6180	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	100	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T118	0	2	0	0
T180	0	4	0	0
T186	0	2	0	0
T194	0	2	0	0
T198	0	4	0	0
T207	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	3029	0	0
T1	28580	176	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	23	0	0
T42	0	11	0	0
T43	0	136	0	0
T118	0	62	0	0
T180	0	190	0	0
T186	0	98	0	0
T194	0	73	0	0
T198	0	194	0	0
T207	0	150	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325814	0	0
T1	28580	24458	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	3298	0	0
T1	28580	201	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	23	0	0
T42	0	55	0	0
T43	0	105	0	0
T118	0	44	0	0
T180	0	88	0	0
T186	0	40	0	0
T194	0	181	0	0
T198	0	83	0	0
T207	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	48	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T118	0	1	0	0
T180	0	2	0	0
T186	0	1	0	0
T194	0	1	0	0
T198	0	2	0	0
T207	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6721048	0	0
T1	28580	23701	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6723370	0	0
T1	28580	23722	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	51	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T118	0	1	0	0
T180	0	2	0	0
T186	0	1	0	0
T194	0	1	0	0
T198	0	2	0	0
T207	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	49	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T118	0	1	0	0
T180	0	2	0	0
T186	0	1	0	0
T194	0	1	0	0
T198	0	2	0	0
T207	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	48	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T118	0	1	0	0
T180	0	2	0	0
T186	0	1	0	0
T194	0	1	0	0
T198	0	2	0	0
T207	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	48	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T118	0	1	0	0
T180	0	2	0	0
T186	0	1	0	0
T194	0	1	0	0
T198	0	2	0	0
T207	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	3223	0	0
T1	28580	198	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	22	0	0
T42	0	53	0	0
T43	0	102	0	0
T118	0	42	0	0
T180	0	85	0	0
T186	0	38	0	0
T194	0	179	0	0
T198	0	80	0	0
T207	0	126	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6180	0	0
T1	28580	33	0	0
T2	606	0	0	0
T3	29349	10	0	0
T4	2408	12	0	0
T5	0	15	0	0
T12	62930	0	0	0
T13	506	3	0	0
T14	524	4	0	0
T15	5211	22	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	6	0	0
T27	0	30	0	0
T55	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	20	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T43	0	1	0	0
T143	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T198	0	1	0	0
T207	0	2	0	0
T233	0	1	0	0
T234	0	1	0	0