Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T9,T36,T78
1	0	Covered	T40,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T9
1	-	Covered	T9,T36,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T9
DetectSt	168	Covered	T2,T8,T9
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T9
DebounceSt->IdleSt	163	Covered	T36,T42,T118
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T8,T9
IdleSt->DebounceSt	148	Covered	T2,T8,T9
StableSt->IdleSt	206	Covered	T9,T44,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T42,T118
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T36,T78
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	128	0	0
CntIncr_A	7986755	242840	0	0
CntNoWrap_A	7986755	7325786	0	0
DetectStDropOut_A	7986755	0	0	0
DetectedOut_A	7986755	115135	0	0
DetectedPulseOut_A	7986755	62	0	0
DisabledIdleSt_A	7986755	6800888	0	0
DisabledNoDetection_A	7986755	6803218	0	0
EnterDebounceSt_A	7986755	66	0	0
EnterDetectSt_A	7986755	62	0	0
EnterStableSt_A	7986755	62	0	0
PulseIsPulse_A	7986755	62	0	0
StayInStableSt	7986755	115040	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	128	0	0
T2	606	2	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	242840	0	0
T2	606	76	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	43	0	0
T9	0	46	0	0
T11	0	85	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	130464	0	0
T37	0	2530	0	0
T38	0	86	0	0
T42	0	11	0	0
T44	0	87	0	0
T78	0	49976	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325786	0	0
T1	28580	24462	0	0
T2	606	203	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	115135	0	0
T2	606	121	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	90	0	0
T9	0	41	0	0
T11	0	46	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	43575	0	0
T37	0	2981	0	0
T38	0	45	0	0
T40	0	23	0	0
T44	0	426	0	0
T78	0	5948	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T78	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6800888	0	0
T1	28580	24462	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6803218	0	0
T1	28580	24484	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	66	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T78	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62	0	0
T2	606	1	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T78	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	115040	0	0
T2	606	119	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T8	0	88	0	0
T9	0	40	0	0
T11	0	44	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	10569	0	0	0
T36	0	43572	0	0
T37	0	2979	0	0
T38	0	43	0	0
T40	0	22	0	0
T44	0	424	0	0
T78	0	5947	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	27	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T41	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T78	0	1	0	0
T83	0	1	0	0
T118	0	1	0	0
T176	0	1	0	0
T194	0	1	0	0
T209	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T9,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T4,T1,T13
1	1	Covered	T9,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T39,T40
0	1	Covered	T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T39,T40
0	1	Covered	T39,T143,T187
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T39,T40
1	-	Covered	T39,T143,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T39,T40
DetectSt	168	Covered	T9,T39,T40
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T9,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T39,T40
DebounceSt->IdleSt	163	Covered	T60
DetectSt->IdleSt	186	Covered	T171
DetectSt->StableSt	191	Covered	T9,T39,T40
IdleSt->DebounceSt	148	Covered	T9,T39,T40
StableSt->IdleSt	206	Covered	T39,T40,T118

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T39,T40
0	1	Covered	T9,T39,T40
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T39,T40
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T171
DetectSt	-	-	-	-	0	1	-	Covered	T9,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T40,T143
StableSt	-	-	-	-	-	-	0	Covered	T9,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	45	0	0
CntIncr_A	7986755	1249	0	0
CntNoWrap_A	7986755	7325869	0	0
DetectStDropOut_A	7986755	1	0	0
DetectedOut_A	7986755	1393	0	0
DetectedPulseOut_A	7986755	21	0	0
DisabledIdleSt_A	7986755	6918999	0	0
DisabledNoDetection_A	7986755	6921335	0	0
EnterDebounceSt_A	7986755	23	0	0
EnterDetectSt_A	7986755	22	0	0
EnterStableSt_A	7986755	21	0	0
PulseIsPulse_A	7986755	21	0	0
StayInStableSt	7986755	1360	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6163	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	45	0	0
T9	765	2	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T60	0	1	0	0
T118	0	2	0	0
T143	0	2	0	0
T186	0	2	0	0
T187	0	2	0	0
T207	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1249	0	0
T9	765	46	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	110	0	0
T40	0	23	0	0
T41	0	61	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T60	0	30	0	0
T118	0	62	0	0
T143	0	39	0	0
T186	0	98	0	0
T187	0	54	0	0
T207	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325869	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1	0	0
T171	130904	1	0	0
T235	409	0	0	0
T236	524	0	0	0
T237	715	0	0	0
T238	31437	0	0	0
T239	1069	0	0	0
T240	405	0	0	0
T241	11959	0	0	0
T242	425	0	0	0
T243	846	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1393	0	0
T9	765	43	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	85	0	0
T40	0	22	0	0
T41	0	42	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T118	0	43	0	0
T143	0	104	0	0
T186	0	40	0	0
T187	0	110	0	0
T188	0	228	0	0
T207	0	110	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	21	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T118	0	1	0	0
T143	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T207	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6918999	0	0
T1	28580	24462	0	0
T2	606	3	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6921335	0	0
T1	28580	24484	0	0
T2	606	3	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	23	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T60	0	1	0	0
T118	0	1	0	0
T143	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T207	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	22	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T118	0	1	0	0
T143	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T207	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	21	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T118	0	1	0	0
T143	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T207	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	21	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T118	0	1	0	0
T143	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T207	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1360	0	0
T9	765	41	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T39	0	82	0	0
T40	0	21	0	0
T41	0	40	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T118	0	41	0	0
T143	0	103	0	0
T186	0	38	0	0
T187	0	109	0	0
T188	0	225	0	0
T207	0	108	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6163	0	0
T1	28580	35	0	0
T2	606	0	0	0
T3	29349	11	0	0
T4	2408	14	0	0
T5	0	16	0	0
T12	62930	0	0	0
T13	506	4	0	0
T14	524	4	0	0
T15	5211	24	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	5	0	0
T27	0	27	0	0
T55	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	8	0	0
T39	741	1	0	0
T63	1867	0	0	0
T64	883	0	0	0
T143	0	1	0	0
T144	18214	0	0	0
T162	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T220	0	1	0	0
T228	0	1	0	0
T244	0	1	0	0
T245	454	0	0	0
T246	403	0	0	0
T247	522	0	0	0
T248	427	0	0	0
T249	407	0	0	0
T250	527	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T11,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T11,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T11,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T44
1	0	Covered	T4,T1,T13
1	1	Covered	T1,T11,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T44
0	1	Covered	T11,T251,T252
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T44
0	1	Covered	T1,T44,T41
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T44
1	-	Covered	T1,T44,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T44
DetectSt	168	Covered	T1,T11,T44
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T11,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T44
DebounceSt->IdleSt	163	Covered	T101,T198,T207
DetectSt->IdleSt	186	Covered	T11,T60,T251
DetectSt->StableSt	191	Covered	T1,T11,T44
IdleSt->DebounceSt	148	Covered	T1,T11,T44
StableSt->IdleSt	206	Covered	T1,T44,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T44
0	1	Covered	T1,T11,T44
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T44
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T198,T207,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T44
DetectSt	-	-	-	-	1	-	-	Covered	T11,T60,T251
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T44,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	121	0	0
CntIncr_A	7986755	105874	0	0
CntNoWrap_A	7986755	7325793	0	0
DetectStDropOut_A	7986755	3	0	0
DetectedOut_A	7986755	116315	0	0
DetectedPulseOut_A	7986755	54	0	0
DisabledIdleSt_A	7986755	6989088	0	0
DisabledNoDetection_A	7986755	6991422	0	0
EnterDebounceSt_A	7986755	65	0	0
EnterDetectSt_A	7986755	58	0	0
EnterStableSt_A	7986755	54	0	0
PulseIsPulse_A	7986755	54	0	0
StayInStableSt	7986755	116232	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	121	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T44	0	2	0	0
T117	0	2	0	0
T118	0	4	0	0
T126	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	105874	0	0
T1	28580	176	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	170	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	23	0	0
T41	0	122	0	0
T42	0	11	0	0
T44	0	87	0	0
T101	0	502	0	0
T118	0	124	0	0
T126	0	44960	0	0
T198	0	194	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325793	0	0
T1	28580	24458	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	3	0	0
T11	839	1	0	0
T25	4430	0	0	0
T33	1602	0	0	0
T34	8787	0	0	0
T53	771	0	0	0
T68	402	0	0	0
T75	521	0	0	0
T76	527	0	0	0
T191	504	0	0	0
T192	27259	0	0	0
T251	0	1	0	0
T252	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	116315	0	0
T1	28580	199	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	133	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	23	0	0
T41	0	82	0	0
T42	0	180	0	0
T44	0	157	0	0
T117	0	44	0	0
T118	0	86	0	0
T126	0	53497	0	0
T231	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	54	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T126	0	1	0	0
T231	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6989088	0	0
T1	28580	23701	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6991422	0	0
T1	28580	23722	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	65	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T101	0	1	0	0
T118	0	2	0	0
T126	0	1	0	0
T198	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	58	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T126	0	1	0	0
T231	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	54	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T126	0	1	0	0
T231	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	54	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T126	0	1	0	0
T231	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	116232	0	0
T1	28580	197	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T11	0	131	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T40	0	22	0	0
T41	0	79	0	0
T42	0	178	0	0
T44	0	156	0	0
T117	0	42	0	0
T118	0	83	0	0
T126	0	53495	0	0
T231	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	24	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T118	0	1	0	0
T143	0	1	0	0
T172	0	1	0	0
T176	0	1	0	0
T180	0	1	0	0
T208	0	1	0	0
T253	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T9,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T7,T9,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T9,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T7,T9,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T38
0	1	Covered	T7,T37,T193
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T38
1	-	Covered	T7,T37,T193

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T38
DetectSt	168	Covered	T7,T9,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T7,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T38
DebounceSt->IdleSt	163	Covered	T62,T60
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T9,T38
IdleSt->DebounceSt	148	Covered	T7,T9,T38
StableSt->IdleSt	206	Covered	T7,T37,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T38
0	1	Covered	T7,T9,T38
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T62
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T37,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	82	0	0
CntIncr_A	7986755	98192	0	0
CntNoWrap_A	7986755	7325832	0	0
DetectStDropOut_A	7986755	0	0	0
DetectedOut_A	7986755	102515	0	0
DetectedPulseOut_A	7986755	40	0	0
DisabledIdleSt_A	7986755	6876217	0	0
DisabledNoDetection_A	7986755	6878544	0	0
EnterDebounceSt_A	7986755	42	0	0
EnterDetectSt_A	7986755	40	0	0
EnterStableSt_A	7986755	40	0	0
PulseIsPulse_A	7986755	40	0	0
StayInStableSt	7986755	102456	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6187	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	82	0	0
T7	568	2	0	0
T8	543	0	0	0
T9	765	2	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T62	0	1	0	0
T111	0	2	0	0
T193	0	2	0	0
T198	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	98192	0	0
T7	568	13	0	0
T8	543	0	0	0
T9	765	46	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	5060	0	0
T38	0	86	0	0
T40	0	23	0	0
T41	0	61	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T62	0	65	0	0
T111	0	34	0	0
T193	0	35	0	0
T198	0	194	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325832	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	102515	0	0
T7	568	9	0	0
T8	543	0	0	0
T9	765	42	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	99	0	0
T38	0	45	0	0
T40	0	23	0	0
T41	0	9	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	131	0	0
T118	0	55	0	0
T193	0	92	0	0
T198	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	1	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	1	0	0
T118	0	1	0	0
T193	0	1	0	0
T198	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6876217	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6878544	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	42	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	1	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T62	0	1	0	0
T111	0	1	0	0
T193	0	1	0	0
T198	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	1	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	1	0	0
T118	0	1	0	0
T193	0	1	0	0
T198	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	1	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	1	0	0
T118	0	1	0	0
T193	0	1	0	0
T198	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	40	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	1	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	1	0	0
T118	0	1	0	0
T193	0	1	0	0
T198	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	102456	0	0
T7	568	8	0	0
T8	543	0	0	0
T9	765	40	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	96	0	0
T38	0	43	0	0
T40	0	22	0	0
T41	0	8	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	130	0	0
T118	0	53	0	0
T193	0	91	0	0
T198	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6187	0	0
T1	28580	26	0	0
T2	606	0	0	0
T3	29349	13	0	0
T4	2408	15	0	0
T5	0	11	0	0
T12	62930	0	0	0
T13	506	5	0	0
T14	524	3	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	5	0	0
T27	0	23	0	0
T55	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	20	0	0
T7	568	1	0	0
T8	543	0	0	0
T9	765	0	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T49	15198	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T61	702	0	0	0
T111	0	1	0	0
T172	0	2	0	0
T174	0	1	0	0
T193	0	1	0	0
T198	0	1	0	0
T207	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T8,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T8,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T8,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T4,T1,T2
1	1	Covered	T8,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Not Covered
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T9,T11,T44
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T11
1	-	Covered	T9,T11,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T11
DetectSt	168	Covered	T8,T9,T11
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T8,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T11
DebounceSt->IdleSt	163	Covered	T39,T203,T251
DetectSt->IdleSt	186	Covered	T60
DetectSt->StableSt	191	Covered	T8,T9,T11
IdleSt->DebounceSt	148	Covered	T8,T9,T11
StableSt->IdleSt	206	Covered	T9,T11,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T11
0	1	Covered	T8,T9,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T203,T251
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T60
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	147	0	0
CntIncr_A	7986755	149267	0	0
CntNoWrap_A	7986755	7325767	0	0
DetectStDropOut_A	7986755	0	0	0
DetectedOut_A	7986755	103699	0	0
DetectedPulseOut_A	7986755	71	0	0
DisabledIdleSt_A	7986755	6817806	0	0
DisabledNoDetection_A	7986755	6820131	0	0
EnterDebounceSt_A	7986755	75	0	0
EnterDetectSt_A	7986755	72	0	0
EnterStableSt_A	7986755	71	0	0
PulseIsPulse_A	7986755	71	0	0
StayInStableSt	7986755	103594	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	147	0	0
T8	543	2	0	0
T9	765	2	0	0
T11	0	4	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	2	0	0
T39	0	3	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	2	0	0
T254	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	149267	0	0
T8	543	43	0	0
T9	765	46	0	0
T11	0	170	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	43488	0	0
T39	0	110	0	0
T40	0	23	0	0
T42	0	11	0	0
T44	0	174	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	87	0	0
T254	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325767	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	103699	0	0
T8	543	90	0	0
T9	765	132	0	0
T11	0	172	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	43529	0	0
T39	0	49	0	0
T40	0	24	0	0
T42	0	84	0	0
T44	0	68	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	61	0	0
T254	0	17	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71	0	0
T8	543	1	0	0
T9	765	1	0	0
T11	0	2	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T254	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6817806	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6820131	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	75	0	0
T8	543	1	0	0
T9	765	1	0	0
T11	0	2	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T254	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	72	0	0
T8	543	1	0	0
T9	765	1	0	0
T11	0	2	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T254	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71	0	0
T8	543	1	0	0
T9	765	1	0	0
T11	0	2	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T254	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71	0	0
T8	543	1	0	0
T9	765	1	0	0
T11	0	2	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T254	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	103594	0	0
T8	543	88	0	0
T9	765	131	0	0
T11	0	169	0	0
T28	31308	0	0	0
T32	21593	0	0	0
T36	0	43528	0	0
T39	0	48	0	0
T40	0	23	0	0
T42	0	83	0	0
T44	0	65	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	60	0	0
T254	0	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	36	0	0
T9	765	1	0	0
T10	12081	0	0	0
T11	0	1	0	0
T32	21593	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T193	0	1	0	0
T254	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T9,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T4,T1,T12
1	1	Covered	T9,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T37
0	1	Covered	T11
1	0	Covered	T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T37
0	1	Covered	T37,T83,T174
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T36,T37
1	-	Covered	T37,T83,T174

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T36
DetectSt	168	Covered	T9,T11,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T9,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T36
DebounceSt->IdleSt	163	Covered	T195,T234
DetectSt->IdleSt	186	Covered	T11,T60
DetectSt->StableSt	191	Covered	T9,T36,T37
IdleSt->DebounceSt	148	Covered	T9,T11,T36
StableSt->IdleSt	206	Covered	T37,T40,T83

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T36
0	1	Covered	T9,T11,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T234
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T11,T60
DetectSt	-	-	-	-	0	1	-	Covered	T9,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T40,T83
StableSt	-	-	-	-	-	-	0	Covered	T9,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	79	0	0
CntIncr_A	7986755	88595	0	0
CntNoWrap_A	7986755	7325835	0	0
DetectStDropOut_A	7986755	1	0	0
DetectedOut_A	7986755	130677	0	0
DetectedPulseOut_A	7986755	37	0	0
DisabledIdleSt_A	7986755	6663382	0	0
DisabledNoDetection_A	7986755	6665710	0	0
EnterDebounceSt_A	7986755	41	0	0
EnterDetectSt_A	7986755	39	0	0
EnterStableSt_A	7986755	37	0	0
PulseIsPulse_A	7986755	37	0	0
StayInStableSt	7986755	130614	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7986755	6931	0	0
gen_low_level_sva.LowLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	79	0	0
T9	765	2	0	0
T10	12081	0	0	0
T11	0	2	0	0
T32	21593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	2	0	0
T198	0	2	0	0
T254	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	88595	0	0
T9	765	46	0	0
T10	12081	0	0	0
T11	0	85	0	0
T32	21593	0	0	0
T36	0	43488	0	0
T37	0	5060	0	0
T40	0	23	0	0
T42	0	11	0	0
T43	0	68	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	59	0	0
T198	0	97	0	0
T254	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325835	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1	0	0
T11	839	1	0	0
T25	4430	0	0	0
T33	1602	0	0	0
T34	8787	0	0	0
T53	771	0	0	0
T68	402	0	0	0
T75	521	0	0	0
T76	527	0	0	0
T191	504	0	0	0
T192	27259	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	130677	0	0
T9	765	131	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T36	0	106203	0	0
T37	0	97	0	0
T40	0	24	0	0
T42	0	107	0	0
T43	0	288	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	158	0	0
T198	0	140	0	0
T203	0	42	0	0
T254	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	37	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	1	0	0
T198	0	1	0	0
T203	0	1	0	0
T254	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6663382	0	0
T1	28580	23701	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6665710	0	0
T1	28580	23722	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	41	0	0
T9	765	1	0	0
T10	12081	0	0	0
T11	0	1	0	0
T32	21593	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	1	0	0
T198	0	1	0	0
T254	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	39	0	0
T9	765	1	0	0
T10	12081	0	0	0
T11	0	1	0	0
T32	21593	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	1	0	0
T198	0	1	0	0
T254	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	37	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	1	0	0
T198	0	1	0	0
T203	0	1	0	0
T254	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	37	0	0
T9	765	1	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	1	0	0
T198	0	1	0	0
T203	0	1	0	0
T254	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	130614	0	0
T9	765	129	0	0
T10	12081	0	0	0
T32	21593	0	0	0
T36	0	106201	0	0
T37	0	94	0	0
T40	0	23	0	0
T42	0	105	0	0
T43	0	286	0	0
T45	22078	0	0	0
T50	709	0	0	0
T51	620	0	0	0
T52	5100	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T83	0	157	0	0
T198	0	138	0	0
T203	0	40	0	0
T254	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6931	0	0
T1	28580	33	0	0
T2	606	0	0	0
T3	29349	14	0	0
T4	2408	15	0	0
T5	0	9	0	0
T12	62930	3	0	0
T13	506	5	0	0
T14	524	6	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	0	4	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	10	0	0
T37	12589	1	0	0
T42	623	0	0	0
T72	495	0	0	0
T83	0	1	0	0
T174	0	1	0	0
T187	0	1	0	0
T190	0	3	0	0
T210	0	1	0	0
T233	0	1	0	0
T254	530	0	0	0
T255	0	1	0	0
T256	505	0	0	0
T257	427	0	0	0
T258	2639	0	0	0
T259	507	0	0	0
T260	519	0	0	0
T261	608	0	0	0