Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T27,T28,T45
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T27,T28
0	1	Covered	T15,T28,T52
1	0	Covered	T28,T40,T125

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T45,T34
0	1	Covered	T27,T45,T34
1	0	Covered	T40,T112,T113

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T45,T34
1	-	Covered	T27,T45,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T27,T28
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T27,T45,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T27,T28
DebounceSt->IdleSt	163	Covered	T40,T152,T60
DetectSt->IdleSt	186	Covered	T15,T28,T52
DetectSt->StableSt	191	Covered	T27,T45,T34
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T27,T45,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T27,T28
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T152,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T28,T52
DetectSt	-	-	-	-	0	1	-	Covered	T27,T45,T34
DetectSt	-	-	-	-	0	0	-	Covered	T15,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T27,T45,T34
StableSt	-	-	-	-	-	-	0	Covered	T27,T45,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	2782	0	0
CntIncr_A	7986755	86122	0	0
CntNoWrap_A	7986755	7323132	0	0
DetectStDropOut_A	7986755	423	0	0
DetectedOut_A	7986755	69323	0	0
DetectedPulseOut_A	7986755	763	0	0
DisabledIdleSt_A	7986755	6926027	0	0
DisabledNoDetection_A	7986755	6928239	0	0
EnterDebounceSt_A	7986755	1404	0	0
EnterDetectSt_A	7986755	1379	0	0
EnterStableSt_A	7986755	763	0	0
PulseIsPulse_A	7986755	763	0	0
StayInStableSt	7986755	68476	0	0
gen_high_event_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	662	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2782	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	10	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	28	0	0
T28	0	56	0	0
T34	0	50	0	0
T45	0	22	0	0
T46	0	28	0	0
T52	0	6	0	0
T55	523	0	0	0
T56	404	0	0	0
T79	0	2	0	0
T80	0	28	0	0
T81	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	86122	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	251	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	812	0	0
T28	0	2076	0	0
T34	0	1275	0	0
T45	0	638	0	0
T46	0	770	0	0
T52	0	143	0	0
T55	523	0	0	0
T56	404	0	0	0
T79	0	21	0	0
T80	0	817	0	0
T81	0	988	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7323132	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4800	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	423	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	5	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	0	0	0
T28	0	18	0	0
T40	0	1	0	0
T52	0	3	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	14	0	0
T124	0	13	0	0
T125	0	9	0	0
T127	0	8	0	0
T128	0	22	0	0
T130	0	30	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	69323	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	2085	0	0
T34	0	1276	0	0
T40	0	425	0	0
T45	0	310	0	0
T46	0	144	0	0
T47	0	1883	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T79	0	42	0	0
T81	0	1592	0	0
T103	406	0	0	0
T262	0	877	0	0
T263	0	1514	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	763	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T34	0	25	0	0
T40	0	5	0	0
T45	0	11	0	0
T46	0	14	0	0
T47	0	19	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T79	0	1	0	0
T81	0	19	0	0
T103	406	0	0	0
T262	0	20	0	0
T263	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6926027	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	2014	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6928239	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	2014	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1404	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	5	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T28	0	28	0	0
T34	0	25	0	0
T45	0	11	0	0
T46	0	14	0	0
T52	0	3	0	0
T55	523	0	0	0
T56	404	0	0	0
T79	0	1	0	0
T80	0	14	0	0
T81	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1379	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	5	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T28	0	28	0	0
T34	0	25	0	0
T45	0	11	0	0
T46	0	14	0	0
T52	0	3	0	0
T55	523	0	0	0
T56	404	0	0	0
T79	0	1	0	0
T80	0	14	0	0
T81	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	763	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T34	0	25	0	0
T40	0	5	0	0
T45	0	11	0	0
T46	0	14	0	0
T47	0	19	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T79	0	1	0	0
T81	0	19	0	0
T103	406	0	0	0
T262	0	20	0	0
T263	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	763	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T34	0	25	0	0
T40	0	5	0	0
T45	0	11	0	0
T46	0	14	0	0
T47	0	19	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T79	0	1	0	0
T81	0	19	0	0
T103	406	0	0	0
T262	0	20	0	0
T263	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	68476	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	2070	0	0
T34	0	1250	0	0
T40	0	420	0	0
T45	0	297	0	0
T46	0	130	0	0
T47	0	1863	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T79	0	40	0	0
T81	0	1572	0	0
T103	406	0	0	0
T262	0	855	0	0
T263	0	1504	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	662	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	13	0	0
T34	0	24	0	0
T40	0	4	0	0
T45	0	9	0	0
T46	0	14	0	0
T47	0	18	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	18	0	0
T103	406	0	0	0
T262	0	18	0	0
T263	0	10	0	0
T264	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T15
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T15
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T3
1	0	Covered	T4,T1,T15
1	1	Covered	T4,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T27
0	1	Covered	T6,T35,T123
1	0	Covered	T40,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T27
0	1	Covered	T3,T5,T27
1	0	Covered	T60,T110

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T27
1	-	Covered	T3,T5,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T5
DetectSt	168	Covered	T3,T5,T27
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T5,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T27
DebounceSt->IdleSt	163	Covered	T4,T6,T32
DetectSt->IdleSt	186	Covered	T6,T35,T123
DetectSt->StableSt	191	Covered	T3,T5,T27
IdleSt->DebounceSt	148	Covered	T4,T3,T5
StableSt->IdleSt	206	Covered	T3,T5,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T3,T5
0	1	Covered	T4,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T27
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T6,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T6,T35,T123
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T27
DetectSt	-	-	-	-	0	0	-	Covered	T3,T5,T27
StableSt	-	-	-	-	-	-	1	Covered	T3,T5,T27
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	826	0	0
CntIncr_A	7986755	39833	0	0
CntNoWrap_A	7986755	7325088	0	0
DetectStDropOut_A	7986755	71	0	0
DetectedOut_A	7986755	13678	0	0
DetectedPulseOut_A	7986755	303	0	0
DisabledIdleSt_A	7986755	6951202	0	0
DisabledNoDetection_A	7986755	6952823	0	0
EnterDebounceSt_A	7986755	449	0	0
EnterDetectSt_A	7986755	378	0	0
EnterStableSt_A	7986755	303	0	0
PulseIsPulse_A	7986755	303	0	0
StayInStableSt	7986755	13352	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	826	0	0
T1	28580	0	0	0
T2	606	0	0	0
T3	29349	4	0	0
T4	2408	1	0	0
T5	0	8	0	0
T6	0	6	0	0
T10	0	6	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	6	0	0
T32	0	13	0	0
T33	0	2	0	0
T45	0	4	0	0
T49	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	39833	0	0
T1	28580	0	0	0
T2	606	0	0	0
T3	29349	192	0	0
T4	2408	20	0	0
T5	0	680	0	0
T6	0	302	0	0
T10	0	348	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	288	0	0
T32	0	627	0	0
T33	0	25	0	0
T45	0	108	0	0
T49	0	344	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325088	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28858	0	0
T4	2408	403	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71	0	0
T6	16159	2	0	0
T7	568	0	0	0
T8	543	0	0	0
T9	765	0	0	0
T28	31308	0	0	0
T35	0	4	0	0
T48	678	0	0	0
T49	15198	0	0	0
T61	702	0	0	0
T62	0	2	0	0
T74	503	0	0	0
T103	406	0	0	0
T123	0	4	0	0
T126	0	6	0	0
T129	0	6	0	0
T131	0	11	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	13678	0	0
T3	29349	128	0	0
T5	21555	35	0	0
T6	16159	0	0	0
T10	0	79	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	93	0	0
T26	522	0	0	0
T27	10569	163	0	0
T32	0	486	0	0
T33	0	3	0	0
T45	0	129	0	0
T48	678	0	0	0
T49	0	10	0	0
T55	523	0	0	0
T56	404	0	0	0
T135	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	303	0	0
T3	29349	2	0	0
T5	21555	4	0	0
T6	16159	0	0	0
T10	0	3	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	2	0	0
T26	522	0	0	0
T27	10569	3	0	0
T32	0	6	0	0
T33	0	1	0	0
T45	0	2	0	0
T48	678	0	0	0
T49	0	2	0	0
T55	523	0	0	0
T56	404	0	0	0
T135	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6951202	0	0
T1	28580	20377	0	0
T2	606	205	0	0
T3	29349	24178	0	0
T4	2408	361	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6952823	0	0
T1	28580	20390	0	0
T2	606	206	0	0
T3	29349	24178	0	0
T4	2408	364	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	449	0	0
T1	28580	0	0	0
T2	606	0	0	0
T3	29349	2	0	0
T4	2408	1	0	0
T5	0	4	0	0
T6	0	4	0	0
T10	0	3	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	3	0	0
T32	0	7	0	0
T33	0	1	0	0
T45	0	2	0	0
T49	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	378	0	0
T3	29349	2	0	0
T5	21555	4	0	0
T6	16159	2	0	0
T10	0	3	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	3	0	0
T32	0	6	0	0
T33	0	1	0	0
T35	0	4	0	0
T45	0	2	0	0
T48	678	0	0	0
T49	0	2	0	0
T55	523	0	0	0
T56	404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	303	0	0
T3	29349	2	0	0
T5	21555	4	0	0
T6	16159	0	0	0
T10	0	3	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	2	0	0
T26	522	0	0	0
T27	10569	3	0	0
T32	0	6	0	0
T33	0	1	0	0
T45	0	2	0	0
T48	678	0	0	0
T49	0	2	0	0
T55	523	0	0	0
T56	404	0	0	0
T135	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	303	0	0
T3	29349	2	0	0
T5	21555	4	0	0
T6	16159	0	0	0
T10	0	3	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	2	0	0
T26	522	0	0	0
T27	10569	3	0	0
T32	0	6	0	0
T33	0	1	0	0
T45	0	2	0	0
T48	678	0	0	0
T49	0	2	0	0
T55	523	0	0	0
T56	404	0	0	0
T135	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	13352	0	0
T3	29349	126	0	0
T5	21555	31	0	0
T6	16159	0	0	0
T10	0	76	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	91	0	0
T26	522	0	0	0
T27	10569	160	0	0
T32	0	480	0	0
T33	0	2	0	0
T45	0	125	0	0
T48	678	0	0	0
T49	0	8	0	0
T55	523	0	0	0
T56	404	0	0	0
T135	0	110	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	276	0	0
T3	29349	2	0	0
T5	21555	4	0	0
T6	16159	0	0	0
T10	0	3	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	2	0	0
T26	522	0	0	0
T27	10569	3	0	0
T32	0	6	0	0
T33	0	1	0	0
T48	678	0	0	0
T49	0	2	0	0
T55	523	0	0	0
T56	404	0	0	0
T135	0	6	0	0
T137	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T27,T28,T45
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T27,T28
0	1	Covered	T15,T52,T80
1	0	Covered	T47,T262,T40

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T45
0	1	Covered	T27,T28,T45
1	0	Covered	T40,T265,T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T28,T45
1	-	Covered	T27,T28,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T27,T28
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T27,T28,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T27,T28
DebounceSt->IdleSt	163	Covered	T40,T152,T60
DetectSt->IdleSt	186	Covered	T15,T52,T80
DetectSt->StableSt	191	Covered	T27,T28,T45
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T27,T28,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T27,T28
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T152,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T52,T80
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T45
DetectSt	-	-	-	-	0	0	-	Covered	T15,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T27,T28,T45
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	2993	0	0
CntIncr_A	7986755	93717	0	0
CntNoWrap_A	7986755	7322921	0	0
DetectStDropOut_A	7986755	502	0	0
DetectedOut_A	7986755	62745	0	0
DetectedPulseOut_A	7986755	802	0	0
DisabledIdleSt_A	7986755	6930920	0	0
DisabledNoDetection_A	7986755	6933120	0	0
EnterDebounceSt_A	7986755	1507	0	0
EnterDetectSt_A	7986755	1488	0	0
EnterStableSt_A	7986755	802	0	0
PulseIsPulse_A	7986755	802	0	0
StayInStableSt	7986755	61848	0	0
gen_high_event_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	692	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2993	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	30	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	10	0	0
T28	0	44	0	0
T34	0	24	0	0
T45	0	44	0	0
T46	0	20	0	0
T47	0	12	0	0
T52	0	28	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	52	0	0
T81	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	93717	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	762	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	415	0	0
T28	0	1298	0	0
T34	0	564	0	0
T45	0	1188	0	0
T46	0	600	0	0
T47	0	393	0	0
T52	0	669	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	1532	0	0
T81	0	552	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7322921	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4780	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	502	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	15	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	0	0	0
T40	0	1	0	0
T52	0	14	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	26	0	0
T112	0	9	0	0
T124	0	15	0	0
T127	0	9	0	0
T128	0	27	0	0
T130	0	30	0	0
T267	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	62745	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	321	0	0
T28	0	3046	0	0
T34	0	377	0	0
T40	0	471	0	0
T45	0	1697	0	0
T46	0	604	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	961	0	0
T103	406	0	0	0
T125	0	1686	0	0
T263	0	2555	0	0
T264	0	1056	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	802	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	5	0	0
T28	0	22	0	0
T34	0	12	0	0
T40	0	5	0	0
T45	0	22	0	0
T46	0	10	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	12	0	0
T103	406	0	0	0
T125	0	22	0	0
T263	0	22	0	0
T264	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6930920	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	2014	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6933120	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	2014	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1507	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	15	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	5	0	0
T28	0	22	0	0
T34	0	12	0	0
T45	0	22	0	0
T46	0	10	0	0
T47	0	6	0	0
T52	0	14	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	26	0	0
T81	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1488	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	15	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	5	0	0
T28	0	22	0	0
T34	0	12	0	0
T45	0	22	0	0
T46	0	10	0	0
T47	0	6	0	0
T52	0	14	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	26	0	0
T81	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	802	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	5	0	0
T28	0	22	0	0
T34	0	12	0	0
T40	0	5	0	0
T45	0	22	0	0
T46	0	10	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	12	0	0
T103	406	0	0	0
T125	0	22	0	0
T263	0	22	0	0
T264	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	802	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	5	0	0
T28	0	22	0	0
T34	0	12	0	0
T40	0	5	0	0
T45	0	22	0	0
T46	0	10	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	12	0	0
T103	406	0	0	0
T125	0	22	0	0
T263	0	22	0	0
T264	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	61848	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	315	0	0
T28	0	3013	0	0
T34	0	364	0	0
T40	0	466	0	0
T45	0	1670	0	0
T46	0	592	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	948	0	0
T103	406	0	0	0
T125	0	1664	0	0
T263	0	2530	0	0
T264	0	1045	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	692	0	0
T6	16159	0	0	0
T7	568	0	0	0
T26	522	0	0	0
T27	10569	4	0	0
T28	0	11	0	0
T34	0	11	0	0
T40	0	4	0	0
T45	0	17	0	0
T46	0	8	0	0
T48	678	0	0	0
T55	523	0	0	0
T56	404	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T81	0	11	0	0
T103	406	0	0	0
T125	0	22	0	0
T263	0	19	0	0
T264	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T3
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T15
1	1	Covered	T1,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T123,T268,T40
1	0	Covered	T40,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T40,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T5
1	-	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T5
DetectSt	168	Covered	T1,T3,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T5
DebounceSt->IdleSt	163	Covered	T3,T5,T6
DetectSt->IdleSt	186	Covered	T123,T268,T40
DetectSt->StableSt	191	Covered	T1,T3,T5
IdleSt->DebounceSt	148	Covered	T1,T3,T5
StableSt->IdleSt	206	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T5,T6
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T123,T268,T40
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	944	0	0
CntIncr_A	7986755	52371	0	0
CntNoWrap_A	7986755	7324970	0	0
DetectStDropOut_A	7986755	36	0	0
DetectedOut_A	7986755	16643	0	0
DetectedPulseOut_A	7986755	411	0	0
DisabledIdleSt_A	7986755	6951508	0	0
DisabledNoDetection_A	7986755	6953164	0	0
EnterDebounceSt_A	7986755	494	0	0
EnterDetectSt_A	7986755	451	0	0
EnterStableSt_A	7986755	411	0	0
PulseIsPulse_A	7986755	411	0	0
StayInStableSt	7986755	16193	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	366	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	944	0	0
T1	28580	16	0	0
T2	606	0	0	0
T3	29349	20	0	0
T5	21555	20	0	0
T6	0	7	0	0
T10	0	8	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	2	0	0
T28	0	22	0	0
T35	0	24	0	0
T45	0	6	0	0
T49	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	52371	0	0
T1	28580	1312	0	0
T2	606	0	0	0
T3	29349	873	0	0
T5	21555	1611	0	0
T6	0	240	0	0
T10	0	456	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	59	0	0
T28	0	616	0	0
T35	0	372	0	0
T45	0	204	0	0
T49	0	310	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7324970	0	0
T1	28580	24446	0	0
T2	606	205	0	0
T3	29349	28842	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	36	0	0
T38	678	0	0	0
T39	741	0	0	0
T40	0	1	0	0
T46	13686	0	0	0
T62	10530	0	0	0
T123	6470	3	0	0
T148	0	7	0	0
T201	0	4	0	0
T229	0	2	0	0
T245	454	0	0	0
T246	403	0	0	0
T247	522	0	0	0
T248	427	0	0	0
T249	407	0	0	0
T268	0	8	0	0
T269	0	6	0	0
T270	0	1	0	0
T271	0	3	0	0
T272	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	16643	0	0
T1	28580	465	0	0
T2	606	0	0	0
T3	29349	701	0	0
T5	21555	161	0	0
T6	0	111	0	0
T10	0	114	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	90	0	0
T28	0	743	0	0
T35	0	80	0	0
T45	0	274	0	0
T49	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	411	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	9	0	0
T5	21555	9	0	0
T6	0	3	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	1	0	0
T28	0	11	0	0
T35	0	12	0	0
T45	0	3	0	0
T49	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6951508	0	0
T1	28580	20377	0	0
T2	606	205	0	0
T3	29349	24178	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6953164	0	0
T1	28580	20390	0	0
T2	606	206	0	0
T3	29349	24178	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	494	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	11	0	0
T5	21555	11	0	0
T6	0	4	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	1	0	0
T28	0	11	0	0
T35	0	12	0	0
T45	0	3	0	0
T49	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	451	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	9	0	0
T5	21555	9	0	0
T6	0	3	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	1	0	0
T28	0	11	0	0
T35	0	12	0	0
T45	0	3	0	0
T49	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	411	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	9	0	0
T5	21555	9	0	0
T6	0	3	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	1	0	0
T28	0	11	0	0
T35	0	12	0	0
T45	0	3	0	0
T49	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	411	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	9	0	0
T5	21555	9	0	0
T6	0	3	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	1	0	0
T28	0	11	0	0
T35	0	12	0	0
T45	0	3	0	0
T49	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	16193	0	0
T1	28580	457	0	0
T2	606	0	0	0
T3	29349	692	0	0
T5	21555	152	0	0
T6	0	108	0	0
T10	0	110	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T27	0	88	0	0
T28	0	721	0	0
T35	0	68	0	0
T45	0	269	0	0
T49	0	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	366	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	9	0	0
T5	21555	9	0	0
T6	0	3	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T35	0	12	0	0
T45	0	1	0	0
T49	0	2	0	0
T135	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T27,T28,T45
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T27,T28
0	1	Covered	T15,T27,T52
1	0	Covered	T27,T40,T125

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T45,T34
0	1	Covered	T28,T45,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T45,T34
1	-	Covered	T28,T45,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T27,T28
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T28,T45,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T27,T28
DebounceSt->IdleSt	163	Covered	T40,T152,T60
DetectSt->IdleSt	186	Covered	T15,T27,T52
DetectSt->StableSt	191	Covered	T28,T45,T34
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T28,T45,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T27,T28
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T152,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T27,T52
DetectSt	-	-	-	-	0	1	-	Covered	T28,T45,T34
DetectSt	-	-	-	-	0	0	-	Covered	T15,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T28,T45,T34
StableSt	-	-	-	-	-	-	0	Covered	T28,T45,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	2959	0	0
CntIncr_A	7986755	90486	0	0
CntNoWrap_A	7986755	7322955	0	0
DetectStDropOut_A	7986755	451	0	0
DetectedOut_A	7986755	72270	0	0
DetectedPulseOut_A	7986755	874	0	0
DisabledIdleSt_A	7986755	6925461	0	0
DisabledNoDetection_A	7986755	6927657	0	0
EnterDebounceSt_A	7986755	1493	0	0
EnterDetectSt_A	7986755	1467	0	0
EnterStableSt_A	7986755	874	0	0
PulseIsPulse_A	7986755	874	0	0
StayInStableSt	7986755	71297	0	0
gen_high_event_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	774	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	2959	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	48	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	18	0	0
T28	0	6	0	0
T34	0	24	0	0
T45	0	56	0	0
T46	0	40	0	0
T47	0	20	0	0
T52	0	44	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	52	0	0
T81	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	90486	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	1225	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	758	0	0
T28	0	186	0	0
T34	0	552	0	0
T45	0	1232	0	0
T46	0	1120	0	0
T47	0	410	0	0
T52	0	1057	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	1532	0	0
T81	0	760	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7322955	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4762	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	451	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	24	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	4	0	0
T40	0	1	0	0
T52	0	22	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	26	0	0
T124	0	15	0	0
T128	0	7	0	0
T130	0	10	0	0
T267	0	4	0	0
T273	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	72270	0	0
T9	765	0	0	0
T10	12081	0	0	0
T28	31308	168	0	0
T32	21593	0	0	0
T34	0	389	0	0
T40	0	445	0	0
T45	22078	1799	0	0
T46	0	1943	0	0
T47	0	267	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T81	0	1068	0	0
T127	0	1826	0	0
T262	0	1392	0	0
T263	0	196	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	874	0	0
T9	765	0	0	0
T10	12081	0	0	0
T28	31308	3	0	0
T32	21593	0	0	0
T34	0	12	0	0
T40	0	5	0	0
T45	22078	28	0	0
T46	0	20	0	0
T47	0	10	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T81	0	19	0	0
T127	0	24	0	0
T262	0	27	0	0
T263	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6925461	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	2015	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6927657	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	2015	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1493	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	24	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	9	0	0
T28	0	3	0	0
T34	0	12	0	0
T45	0	28	0	0
T46	0	20	0	0
T47	0	10	0	0
T52	0	22	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	26	0	0
T81	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1467	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	24	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	9	0	0
T28	0	3	0	0
T34	0	12	0	0
T45	0	28	0	0
T46	0	20	0	0
T47	0	10	0	0
T52	0	22	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	26	0	0
T81	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	874	0	0
T9	765	0	0	0
T10	12081	0	0	0
T28	31308	3	0	0
T32	21593	0	0	0
T34	0	12	0	0
T40	0	5	0	0
T45	22078	28	0	0
T46	0	20	0	0
T47	0	10	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T81	0	19	0	0
T127	0	24	0	0
T262	0	27	0	0
T263	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	874	0	0
T9	765	0	0	0
T10	12081	0	0	0
T28	31308	3	0	0
T32	21593	0	0	0
T34	0	12	0	0
T40	0	5	0	0
T45	22078	28	0	0
T46	0	20	0	0
T47	0	10	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T81	0	19	0	0
T127	0	24	0	0
T262	0	27	0	0
T263	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71297	0	0
T9	765	0	0	0
T10	12081	0	0	0
T28	31308	164	0	0
T32	21593	0	0	0
T34	0	376	0	0
T40	0	440	0	0
T45	22078	1765	0	0
T46	0	1920	0	0
T47	0	257	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T81	0	1048	0	0
T127	0	1801	0	0
T262	0	1361	0	0
T263	0	188	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	774	0	0
T9	765	0	0	0
T10	12081	0	0	0
T28	31308	2	0	0
T32	21593	0	0	0
T34	0	11	0	0
T40	0	5	0	0
T45	22078	22	0	0
T46	0	17	0	0
T47	0	10	0	0
T50	709	0	0	0
T51	620	0	0	0
T57	423	0	0	0
T58	403	0	0	0
T59	522	0	0	0
T81	0	18	0	0
T127	0	23	0	0
T262	0	23	0	0
T263	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T3
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T15
1	1	Covered	T1,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T6,T10,T137
1	0	Covered	T40,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T40

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T5
1	-	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T5
DetectSt	168	Covered	T1,T3,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T5
DebounceSt->IdleSt	163	Covered	T5,T32,T123
DetectSt->IdleSt	186	Covered	T6,T10,T137
DetectSt->StableSt	191	Covered	T1,T3,T5
IdleSt->DebounceSt	148	Covered	T1,T3,T5
StableSt->IdleSt	206	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T32,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T6,T10,T137
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	910	0	0
CntIncr_A	7986755	55064	0	0
CntNoWrap_A	7986755	7325004	0	0
DetectStDropOut_A	7986755	90	0	0
DetectedOut_A	7986755	14858	0	0
DetectedPulseOut_A	7986755	337	0	0
DisabledIdleSt_A	7986755	6946921	0	0
DisabledNoDetection_A	7986755	6948591	0	0
EnterDebounceSt_A	7986755	479	0	0
EnterDetectSt_A	7986755	432	0	0
EnterStableSt_A	7986755	337	0	0
PulseIsPulse_A	7986755	337	0	0
StayInStableSt	7986755	14481	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	296	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	910	0	0
T1	28580	2	0	0
T2	606	0	0	0
T3	29349	2	0	0
T5	21555	9	0	0
T6	0	12	0	0
T10	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	2	0	0
T32	0	3	0	0
T34	0	2	0	0
T45	0	12	0	0
T49	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	55064	0	0
T1	28580	157	0	0
T2	606	0	0	0
T3	29349	145	0	0
T5	21555	569	0	0
T6	0	604	0	0
T10	0	142	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	61	0	0
T32	0	242	0	0
T34	0	58	0	0
T45	0	444	0	0
T49	0	198	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7325004	0	0
T1	28580	24460	0	0
T2	606	205	0	0
T3	29349	28860	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	90	0	0
T6	16159	6	0	0
T7	568	0	0	0
T8	543	0	0	0
T9	765	0	0	0
T10	0	1	0	0
T28	31308	0	0	0
T48	678	0	0	0
T49	15198	0	0	0
T61	702	0	0	0
T74	503	0	0	0
T103	406	0	0	0
T134	0	3	0	0
T137	0	1	0	0
T143	0	5	0	0
T201	0	11	0	0
T202	0	5	0	0
T274	0	11	0	0
T275	0	1	0	0
T276	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	14858	0	0
T1	28580	64	0	0
T2	606	0	0	0
T3	29349	16	0	0
T5	21555	225	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	63	0	0
T32	0	7	0	0
T34	0	42	0	0
T35	0	40	0	0
T45	0	264	0	0
T49	0	158	0	0
T192	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	337	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	1	0	0
T5	21555	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T45	0	6	0	0
T49	0	2	0	0
T192	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6946921	0	0
T1	28580	20377	0	0
T2	606	205	0	0
T3	29349	24178	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6948591	0	0
T1	28580	20390	0	0
T2	606	206	0	0
T3	29349	24178	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	479	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	1	0	0
T5	21555	5	0	0
T6	0	6	0	0
T10	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T45	0	6	0	0
T49	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	432	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	1	0	0
T5	21555	4	0	0
T6	0	6	0	0
T10	0	1	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T45	0	6	0	0
T49	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	337	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	1	0	0
T5	21555	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T45	0	6	0	0
T49	0	2	0	0
T192	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	337	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	1	0	0
T5	21555	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T45	0	6	0	0
T49	0	2	0	0
T192	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	14481	0	0
T1	28580	63	0	0
T2	606	0	0	0
T3	29349	15	0	0
T5	21555	221	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T28	0	61	0	0
T32	0	6	0	0
T34	0	41	0	0
T35	0	37	0	0
T45	0	252	0	0
T49	0	156	0	0
T192	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	296	0	0
T1	28580	1	0	0
T2	606	0	0	0
T3	29349	1	0	0
T5	21555	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	10	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T49	0	2	0	0
T135	0	7	0	0
T192	0	3	0	0