Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T28
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T28
1	0	Covered	T27,T28,T45
1	1	Covered	T15,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T27,T28
0	1	Covered	T15,T28,T52
1	0	Covered	T27,T28,T45

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T46,T47
0	1	Covered	T34,T46,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T46,T47
1	-	Covered	T34,T46,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T27,T28
DetectSt	168	Covered	T15,T27,T28
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T34,T46,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T27,T28
DebounceSt->IdleSt	163	Covered	T40,T152,T60
DetectSt->IdleSt	186	Covered	T15,T27,T28
DetectSt->StableSt	191	Covered	T34,T46,T47
IdleSt->DebounceSt	148	Covered	T15,T27,T28
StableSt->IdleSt	206	Covered	T34,T46,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T27,T28
0	1	Covered	T15,T27,T28
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T27,T28
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T15,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T152,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T27,T28
DetectSt	-	-	-	-	0	1	-	Covered	T34,T46,T47
DetectSt	-	-	-	-	0	0	-	Covered	T15,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T34,T46,T47
StableSt	-	-	-	-	-	-	0	Covered	T34,T46,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	3071	0	0
CntIncr_A	7986755	93992	0	0
CntNoWrap_A	7986755	7322843	0	0
DetectStDropOut_A	7986755	439	0	0
DetectedOut_A	7986755	71522	0	0
DetectedPulseOut_A	7986755	922	0	0
DisabledIdleSt_A	7986755	6924778	0	0
DisabledNoDetection_A	7986755	6926962	0	0
EnterDebounceSt_A	7986755	1548	0	0
EnterDetectSt_A	7986755	1525	0	0
EnterStableSt_A	7986755	922	0	0
PulseIsPulse_A	7986755	922	0	0
StayInStableSt	7986755	70489	0	0
gen_high_event_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	811	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	3071	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	46	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	28	0	0
T28	0	22	0	0
T34	0	26	0	0
T45	0	22	0	0
T46	0	22	0	0
T47	0	26	0	0
T52	0	16	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	48	0	0
T81	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	93992	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	1177	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	1184	0	0
T28	0	818	0	0
T34	0	715	0	0
T45	0	688	0	0
T46	0	583	0	0
T47	0	559	0	0
T52	0	379	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	1416	0	0
T81	0	1703	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7322843	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4764	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	439	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	0	0	0
T28	0	4	0	0
T40	0	1	0	0
T52	0	8	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	24	0	0
T81	0	12	0	0
T124	0	7	0	0
T128	0	23	0	0
T130	0	29	0	0
T267	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	71522	0	0
T22	583	0	0	0
T25	4430	0	0	0
T34	8787	176	0	0
T40	0	467	0	0
T46	0	279	0	0
T47	0	991	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T125	0	674	0	0
T127	0	180	0	0
T191	504	0	0	0
T192	27259	0	0	0
T262	0	28	0	0
T263	0	2841	0	0
T264	0	1391	0	0
T277	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	922	0	0
T22	583	0	0	0
T25	4430	0	0	0
T34	8787	13	0	0
T40	0	5	0	0
T46	0	11	0	0
T47	0	13	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T125	0	14	0	0
T127	0	9	0	0
T191	504	0	0	0
T192	27259	0	0	0
T262	0	4	0	0
T263	0	22	0	0
T264	0	10	0	0
T277	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6924778	0	0
T1	28580	24462	0	0
T2	606	205	0	0
T3	29349	28862	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	2016	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6926962	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	2016	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1548	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T28	0	11	0	0
T34	0	13	0	0
T45	0	11	0	0
T46	0	11	0	0
T47	0	13	0	0
T52	0	8	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	24	0	0
T81	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	1525	0	0
T3	29349	0	0	0
T5	21555	0	0	0
T6	16159	0	0	0
T15	5211	23	0	0
T16	409	0	0	0
T17	402	0	0	0
T26	522	0	0	0
T27	10569	14	0	0
T28	0	11	0	0
T34	0	13	0	0
T45	0	11	0	0
T46	0	11	0	0
T47	0	13	0	0
T52	0	8	0	0
T55	523	0	0	0
T56	404	0	0	0
T80	0	24	0	0
T81	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	922	0	0
T22	583	0	0	0
T25	4430	0	0	0
T34	8787	13	0	0
T40	0	5	0	0
T46	0	11	0	0
T47	0	13	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T125	0	14	0	0
T127	0	9	0	0
T191	504	0	0	0
T192	27259	0	0	0
T262	0	4	0	0
T263	0	22	0	0
T264	0	10	0	0
T277	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	922	0	0
T22	583	0	0	0
T25	4430	0	0	0
T34	8787	13	0	0
T40	0	5	0	0
T46	0	11	0	0
T47	0	13	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T125	0	14	0	0
T127	0	9	0	0
T191	504	0	0	0
T192	27259	0	0	0
T262	0	4	0	0
T263	0	22	0	0
T264	0	10	0	0
T277	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	70489	0	0
T22	583	0	0	0
T25	4430	0	0	0
T34	8787	163	0	0
T40	0	462	0	0
T46	0	267	0	0
T47	0	977	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T125	0	660	0	0
T127	0	171	0	0
T191	504	0	0	0
T192	27259	0	0	0
T262	0	24	0	0
T263	0	2816	0	0
T264	0	1379	0	0
T277	0	96	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	811	0	0
T22	583	0	0	0
T25	4430	0	0	0
T34	8787	13	0	0
T40	0	5	0	0
T46	0	10	0	0
T47	0	12	0	0
T54	696	0	0	0
T69	491	0	0	0
T86	422	0	0	0
T87	421	0	0	0
T88	522	0	0	0
T125	0	14	0	0
T127	0	9	0	0
T191	504	0	0	0
T192	27259	0	0	0
T262	0	4	0	0
T263	0	19	0	0
T264	0	8	0	0
T277	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T3
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T15
1	1	Covered	T1,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T10,T144,T126
1	0	Covered	T40,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T5
1	-	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T5
DetectSt	168	Covered	T1,T3,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T5
DebounceSt->IdleSt	163	Covered	T3,T6,T32
DetectSt->IdleSt	186	Covered	T10,T144,T40
DetectSt->StableSt	191	Covered	T1,T3,T5
IdleSt->DebounceSt	148	Covered	T1,T3,T5
StableSt->IdleSt	206	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T6,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T10,T144,T40
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7986755	934	0	0
CntIncr_A	7986755	49419	0	0
CntNoWrap_A	7986755	7324980	0	0
DetectStDropOut_A	7986755	43	0	0
DetectedOut_A	7986755	17472	0	0
DetectedPulseOut_A	7986755	398	0	0
DisabledIdleSt_A	7986755	6938427	0	0
DisabledNoDetection_A	7986755	6940063	0	0
EnterDebounceSt_A	7986755	490	0	0
EnterDetectSt_A	7986755	445	0	0
EnterStableSt_A	7986755	398	0	0
PulseIsPulse_A	7986755	398	0	0
StayInStableSt	7986755	17025	0	0
gen_high_level_sva.HighLevelEvent_A	7986755	7328300	0	0
gen_not_sticky_sva.StableStDropOut_A	7986755	348	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	934	0	0
T1	28580	8	0	0
T2	606	0	0	0
T3	29349	7	0	0
T5	21555	8	0	0
T6	0	8	0	0
T10	0	4	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	2	0	0
T32	0	1	0	0
T35	0	12	0	0
T135	0	11	0	0
T192	0	15	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	49419	0	0
T1	28580	613	0	0
T2	606	0	0	0
T3	29349	531	0	0
T5	21555	436	0	0
T6	0	381	0	0
T10	0	284	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	156	0	0
T32	0	75	0	0
T35	0	186	0	0
T135	0	913	0	0
T192	0	1059	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7324980	0	0
T1	28580	24454	0	0
T2	606	205	0	0
T3	29349	28855	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	43	0	0
T10	12081	2	0	0
T11	839	0	0	0
T33	1602	0	0	0
T34	8787	0	0	0
T52	5100	0	0	0
T53	771	0	0	0
T60	0	1	0	0
T67	402	0	0	0
T68	402	0	0	0
T75	521	0	0	0
T76	527	0	0	0
T126	0	7	0	0
T144	0	4	0	0
T148	0	1	0	0
T252	0	2	0	0
T276	0	7	0	0
T278	0	2	0	0
T279	0	10	0	0
T280	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	17472	0	0
T1	28580	234	0	0
T2	606	0	0	0
T3	29349	15	0	0
T5	21555	279	0	0
T6	0	21	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	31	0	0
T35	0	32	0	0
T123	0	5	0	0
T135	0	354	0	0
T137	0	80	0	0
T192	0	366	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	398	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	3	0	0
T5	21555	4	0	0
T6	0	3	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T35	0	6	0	0
T123	0	1	0	0
T135	0	5	0	0
T137	0	1	0	0
T192	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6938427	0	0
T1	28580	20377	0	0
T2	606	205	0	0
T3	29349	24178	0	0
T4	2408	404	0	0
T12	62930	62529	0	0
T13	506	105	0	0
T14	524	123	0	0
T15	5211	4810	0	0
T16	409	8	0	0
T17	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	6940063	0	0
T1	28580	20390	0	0
T2	606	206	0	0
T3	29349	24178	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	490	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	4	0	0
T5	21555	4	0	0
T6	0	5	0	0
T10	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T32	0	1	0	0
T35	0	6	0	0
T135	0	6	0	0
T192	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	445	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	3	0	0
T5	21555	4	0	0
T6	0	3	0	0
T10	0	2	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T35	0	6	0	0
T135	0	5	0	0
T137	0	1	0	0
T192	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	398	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	3	0	0
T5	21555	4	0	0
T6	0	3	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T35	0	6	0	0
T123	0	1	0	0
T135	0	5	0	0
T137	0	1	0	0
T192	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	398	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	3	0	0
T5	21555	4	0	0
T6	0	3	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T35	0	6	0	0
T123	0	1	0	0
T135	0	5	0	0
T137	0	1	0	0
T192	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	17025	0	0
T1	28580	230	0	0
T2	606	0	0	0
T3	29349	12	0	0
T5	21555	275	0	0
T6	0	18	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	30	0	0
T35	0	26	0	0
T123	0	4	0	0
T135	0	349	0	0
T137	0	79	0	0
T192	0	359	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	7328300	0	0
T1	28580	24484	0	0
T2	606	206	0	0
T3	29349	28874	0	0
T4	2408	408	0	0
T12	62930	62530	0	0
T13	506	106	0	0
T14	524	124	0	0
T15	5211	4811	0	0
T16	409	9	0	0
T17	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7986755	348	0	0
T1	28580	4	0	0
T2	606	0	0	0
T3	29349	3	0	0
T5	21555	4	0	0
T6	0	3	0	0
T12	62930	0	0	0
T13	506	0	0	0
T14	524	0	0	0
T15	5211	0	0	0
T16	409	0	0	0
T17	402	0	0	0
T23	0	1	0	0
T35	0	6	0	0
T123	0	1	0	0
T135	0	5	0	0
T137	0	1	0	0
T192	0	7	0	0