Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1352825984	12804	0	0
auto_block_debounce_ctl_rd_A	1352825984	1566	0	0
auto_block_out_ctl_rd_A	1352825984	2269	0	0
com_det_ctl_0_rd_A	1352825984	3371	0	0
com_det_ctl_1_rd_A	1352825984	3492	0	0
com_det_ctl_2_rd_A	1352825984	3537	0	0
com_det_ctl_3_rd_A	1352825984	3562	0	0
com_out_ctl_0_rd_A	1352825984	3964	0	0
com_out_ctl_1_rd_A	1352825984	4162	0	0
com_out_ctl_2_rd_A	1352825984	3910	0	0
com_out_ctl_3_rd_A	1352825984	4061	0	0
com_pre_det_ctl_0_rd_A	1352825984	982	0	0
com_pre_det_ctl_1_rd_A	1352825984	1015	0	0
com_pre_det_ctl_2_rd_A	1352825984	978	0	0
com_pre_det_ctl_3_rd_A	1352825984	935	0	0
com_pre_sel_ctl_0_rd_A	1352825984	4354	0	0
com_pre_sel_ctl_1_rd_A	1352825984	3991	0	0
com_pre_sel_ctl_2_rd_A	1352825984	4336	0	0
com_pre_sel_ctl_3_rd_A	1352825984	4021	0	0
com_sel_ctl_0_rd_A	1352825984	4103	0	0
com_sel_ctl_1_rd_A	1352825984	4343	0	0
com_sel_ctl_2_rd_A	1352825984	4207	0	0
com_sel_ctl_3_rd_A	1352825984	4256	0	0
ec_rst_ctl_rd_A	1352825984	2243	0	0
intr_enable_rd_A	1352825984	1529	0	0
key_intr_ctl_rd_A	1352825984	3632	0	0
key_intr_debounce_ctl_rd_A	1352825984	985	0	0
key_invert_ctl_rd_A	1352825984	5078	0	0
pin_allowed_ctl_rd_A	1352825984	5950	0	0
pin_out_ctl_rd_A	1352825984	4623	0	0
pin_out_value_rd_A	1352825984	4323	0	0
regwen_rd_A	1352825984	1048	0	0
ulp_ac_debounce_ctl_rd_A	1352825984	1137	0	0
ulp_ctl_rd_A	1352825984	1112	0	0
ulp_lid_debounce_ctl_rd_A	1352825984	1205	0	0
ulp_pwrb_debounce_ctl_rd_A	1352825984	1168	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	12804	0	0
T1	337284	7	0	0
T2	60629	0	0	0
T3	143817	0	0	0
T5	258666	0	0	0
T12	503443	0	0	0
T13	38041	0	0	0
T14	78601	0	0	0
T15	286610	0	0	0
T16	45033	0	0	0
T17	200836	0	0	0
T23	0	11	0	0
T25	0	8	0	0
T62	0	5	0	0
T83	0	5	0	0
T101	0	9	0	0
T195	0	7	0	0
T199	0	14	0	0
T200	0	13	0	0
T203	0	10	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1566	0	0
T3	143817	0	0	0
T5	258666	0	0	0
T12	503443	14	0	0
T13	38041	0	0	0
T14	78601	0	0	0
T15	286610	0	0	0
T16	45033	0	0	0
T17	200836	0	0	0
T23	0	40	0	0
T26	253521	0	0	0
T27	121555	0	0	0
T121	0	10	0	0
T176	0	37	0	0
T269	0	19	0	0
T291	0	11	0	0
T292	0	4	0	0
T293	0	14	0	0
T294	0	2	0	0
T295	0	2	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	2269	0	0
T3	143817	0	0	0
T5	258666	0	0	0
T12	503443	6	0	0
T13	38041	0	0	0
T14	78601	0	0	0
T15	286610	0	0	0
T16	45033	0	0	0
T17	200836	0	0	0
T23	0	58	0	0
T26	253521	0	0	0
T27	121555	0	0	0
T121	0	15	0	0
T176	0	41	0	0
T269	0	28	0	0
T291	0	10	0	0
T292	0	4	0	0
T293	0	17	0	0
T294	0	5	0	0
T295	0	7	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3371	0	0
T9	151823	0	0	0
T10	579873	75	0	0
T23	0	74	0	0
T28	120535	101	0	0
T32	521528	0	0	0
T35	0	80	0	0
T45	104876	33	0	0
T47	0	27	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	54	0	0
T135	0	35	0	0
T144	0	37	0	0
T192	0	61	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3492	0	0
T9	151823	0	0	0
T10	579873	84	0	0
T23	0	45	0	0
T28	120535	87	0	0
T32	521528	0	0	0
T35	0	52	0	0
T45	104876	51	0	0
T47	0	29	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	69	0	0
T135	0	62	0	0
T144	0	27	0	0
T192	0	77	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3537	0	0
T9	151823	0	0	0
T10	579873	73	0	0
T23	0	74	0	0
T28	120535	84	0	0
T32	521528	0	0	0
T35	0	99	0	0
T45	104876	47	0	0
T47	0	31	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	55	0	0
T135	0	52	0	0
T144	0	33	0	0
T192	0	87	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3562	0	0
T9	151823	0	0	0
T10	579873	58	0	0
T23	0	73	0	0
T28	120535	97	0	0
T32	521528	0	0	0
T35	0	96	0	0
T45	104876	36	0	0
T47	0	52	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	37	0	0
T135	0	32	0	0
T144	0	49	0	0
T192	0	63	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3964	0	0
T9	151823	0	0	0
T10	579873	71	0	0
T23	0	41	0	0
T28	120535	63	0	0
T32	521528	0	0	0
T35	0	64	0	0
T45	104876	46	0	0
T47	0	28	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	40	0	0
T135	0	51	0	0
T144	0	32	0	0
T192	0	63	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4162	0	0
T9	151823	0	0	0
T10	579873	72	0	0
T23	0	62	0	0
T28	120535	112	0	0
T32	521528	0	0	0
T35	0	83	0	0
T45	104876	45	0	0
T47	0	13	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	53	0	0
T135	0	20	0	0
T144	0	49	0	0
T192	0	65	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3910	0	0
T9	151823	0	0	0
T10	579873	92	0	0
T23	0	57	0	0
T28	120535	105	0	0
T32	521528	0	0	0
T35	0	60	0	0
T45	104876	36	0	0
T47	0	32	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	52	0	0
T135	0	47	0	0
T144	0	56	0	0
T192	0	62	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4061	0	0
T9	151823	0	0	0
T10	579873	67	0	0
T23	0	44	0	0
T28	120535	88	0	0
T32	521528	0	0	0
T35	0	75	0	0
T45	104876	36	0	0
T47	0	61	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	46	0	0
T135	0	50	0	0
T144	0	45	0	0
T192	0	85	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	982	0	0
T23	543324	15	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	18	0	0
T176	0	22	0	0
T190	0	11	0	0
T220	0	4	0	0
T293	0	26	0	0
T296	0	9	0	0
T297	0	16	0	0
T298	0	38	0	0
T299	0	41	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1015	0	0
T23	543324	10	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	22	0	0
T176	0	26	0	0
T190	0	19	0	0
T220	0	3	0	0
T293	0	9	0	0
T296	0	32	0	0
T297	0	5	0	0
T298	0	39	0	0
T299	0	45	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	978	0	0
T23	543324	16	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	10	0	0
T176	0	13	0	0
T190	0	14	0	0
T220	0	16	0	0
T293	0	15	0	0
T296	0	29	0	0
T297	0	5	0	0
T298	0	31	0	0
T299	0	43	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	935	0	0
T23	543324	19	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	21	0	0
T176	0	16	0	0
T190	0	26	0	0
T220	0	13	0	0
T293	0	33	0	0
T296	0	58	0	0
T298	0	27	0	0
T299	0	33	0	0
T300	0	9	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4354	0	0
T9	151823	0	0	0
T10	579873	79	0	0
T23	0	43	0	0
T28	120535	73	0	0
T32	521528	0	0	0
T35	0	74	0	0
T45	104876	38	0	0
T47	0	30	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	41	0	0
T135	0	49	0	0
T144	0	37	0	0
T192	0	82	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3991	0	0
T9	151823	0	0	0
T10	579873	67	0	0
T23	0	64	0	0
T28	120535	82	0	0
T32	521528	0	0	0
T35	0	60	0	0
T45	104876	43	0	0
T47	0	31	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	42	0	0
T135	0	48	0	0
T144	0	52	0	0
T192	0	68	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4336	0	0
T9	151823	0	0	0
T10	579873	66	0	0
T23	0	84	0	0
T28	120535	104	0	0
T32	521528	0	0	0
T35	0	66	0	0
T45	104876	35	0	0
T47	0	53	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	41	0	0
T135	0	39	0	0
T144	0	28	0	0
T192	0	51	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4021	0	0
T9	151823	0	0	0
T10	579873	83	0	0
T23	0	70	0	0
T28	120535	83	0	0
T32	521528	0	0	0
T35	0	86	0	0
T45	104876	60	0	0
T47	0	25	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	46	0	0
T135	0	45	0	0
T144	0	43	0	0
T192	0	78	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4103	0	0
T9	151823	0	0	0
T10	579873	69	0	0
T23	0	69	0	0
T28	120535	107	0	0
T32	521528	0	0	0
T35	0	68	0	0
T45	104876	37	0	0
T47	0	27	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	33	0	0
T135	0	33	0	0
T144	0	37	0	0
T192	0	70	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4343	0	0
T9	151823	0	0	0
T10	579873	80	0	0
T23	0	60	0	0
T28	120535	83	0	0
T32	521528	0	0	0
T35	0	74	0	0
T45	104876	28	0	0
T47	0	48	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	42	0	0
T135	0	42	0	0
T144	0	28	0	0
T192	0	72	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4207	0	0
T9	151823	0	0	0
T10	579873	74	0	0
T23	0	82	0	0
T28	120535	73	0	0
T32	521528	0	0	0
T35	0	85	0	0
T45	104876	24	0	0
T47	0	40	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	58	0	0
T135	0	39	0	0
T144	0	37	0	0
T192	0	64	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4256	0	0
T9	151823	0	0	0
T10	579873	72	0	0
T23	0	78	0	0
T28	120535	87	0	0
T32	521528	0	0	0
T35	0	63	0	0
T45	104876	43	0	0
T47	0	46	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T81	0	59	0	0
T135	0	53	0	0
T144	0	49	0	0
T192	0	72	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	2243	0	0
T9	151823	0	0	0
T10	579873	10	0	0
T23	0	85	0	0
T28	120535	45	0	0
T32	521528	0	0	0
T35	0	11	0	0
T45	104876	19	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T52	0	2	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T89	0	2	0	0
T135	0	33	0	0
T158	0	6	0	0
T192	0	51	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1529	0	0
T23	543324	47	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	13	0	0
T176	0	65	0	0
T190	0	56	0	0
T220	0	60	0	0
T293	0	28	0	0
T296	0	61	0	0
T297	0	40	0	0
T298	0	42	0	0
T301	0	40	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	3632	0	0
T8	53399	3	0	0
T9	151823	0	0	0
T23	0	28	0	0
T28	120535	0	0	0
T32	521528	0	0	0
T37	0	4	0	0
T45	104876	0	0	0
T50	21278	0	0	0
T51	192422	0	0	0
T57	59416	0	0	0
T58	105066	0	0	0
T59	256069	0	0	0
T176	0	22	0	0
T209	0	5	0	0
T231	0	2	0	0
T254	0	1	0	0
T293	0	11	0	0
T296	0	28	0	0
T302	0	4	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	985	0	0
T23	543324	17	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	16	0	0
T176	0	21	0	0
T190	0	26	0	0
T220	0	9	0	0
T293	0	19	0	0
T296	0	38	0	0
T297	0	5	0	0
T298	0	25	0	0
T299	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	5078	0	0
T23	543324	184	0	0
T35	242111	0	0	0
T44	453205	0	0	0
T54	299489	0	0	0
T69	245979	46	0	0
T72	0	60	0	0
T73	0	50	0	0
T87	211124	0	0	0
T88	162047	0	0	0
T89	88323	0	0	0
T90	198636	0	0	0
T150	0	74	0	0
T157	53078	0	0	0
T205	0	97	0	0
T293	0	7	0	0
T303	0	54	0	0
T304	0	52	0	0
T305	0	81	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	5950	0	0
T23	543324	21	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	17	0	0
T225	0	71	0	0
T293	0	20	0	0
T296	0	225	0	0
T306	0	61	0	0
T307	0	43	0	0
T308	0	75	0	0
T309	0	80	0	0
T310	0	42	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4623	0	0
T23	543324	14	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	21	0	0
T225	0	64	0	0
T293	0	13	0	0
T296	0	260	0	0
T306	0	76	0	0
T307	0	66	0	0
T308	0	70	0	0
T309	0	52	0	0
T310	0	40	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	4323	0	0
T23	543324	19	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	26	0	0
T225	0	69	0	0
T293	0	12	0	0
T296	0	224	0	0
T306	0	55	0	0
T307	0	24	0	0
T308	0	77	0	0
T309	0	67	0	0
T310	0	38	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1048	0	0
T23	543324	22	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T173	0	10	0	0
T176	0	13	0	0
T190	0	8	0	0
T220	0	2	0	0
T293	0	23	0	0
T296	0	23	0	0
T297	0	2	0	0
T298	0	34	0	0
T299	0	25	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1137	0	0
T23	543324	21	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T85	0	9	0	0
T138	0	6	0	0
T140	0	19	0	0
T141	0	8	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	27	0	0
T293	0	12	0	0
T296	0	32	0	0
T311	0	12	0	0
T312	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1112	0	0
T23	543324	26	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T85	0	11	0	0
T138	0	4	0	0
T140	0	18	0	0
T141	0	5	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	17	0	0
T293	0	30	0	0
T296	0	33	0	0
T311	0	9	0	0
T312	0	9	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1205	0	0
T23	543324	24	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T85	0	21	0	0
T138	0	6	0	0
T140	0	11	0	0
T141	0	7	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	23	0	0
T293	0	18	0	0
T296	0	23	0	0
T311	0	4	0	0
T312	0	11	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352825984	1168	0	0
T23	543324	17	0	0
T24	227167	0	0	0
T36	199158	0	0	0
T44	453205	0	0	0
T70	54851	0	0	0
T77	171219	0	0	0
T79	233625	0	0	0
T85	0	1	0	0
T138	0	1	0	0
T140	0	18	0	0
T141	0	10	0	0
T157	53078	0	0	0
T158	91137	0	0	0
T159	63232	0	0	0
T176	0	13	0	0
T293	0	17	0	0
T296	0	23	0	0
T311	0	7	0	0
T312	0	9	0	0