Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.56	97.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	97.56	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.56	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	2	60	96.77

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	2	29	93.55	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1985

1

T3

1

T6

5

T7

24

auto[1]

659

1

T1

5

T6

4

T23

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1965

1

T3

1

T7

24

T23

29

auto[1]

679

1

T1

5

T6

9

T23

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1975

1

T6

9

T7

23

T23

27

auto[1]

669

1

T1

5

T3

1

T7

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1958

1

T1

1

T3

1

T6

4

auto[1]

686

1

T1

4

T6

5

T7

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2307

1

T1

5

T3

1

T6

9

auto[1]

337

1

T7

2

T23

4

T24

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2429

1

T1

5

T3

1

T6

9

auto[1]

215

1

T24

1

T69

1

T196

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2397

1

T1

5

T3

1

T6

9

auto[1]

247

1

T7

6

T24

6

T30

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2452

1

T1

5

T3

1

T6

9

auto[1]

192

1

T24

11

T30

4

T68

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2418

1

T1

5

T3

1

T6

9

auto[1]

226

1

T7

2

T23

14

T24

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1984

1

T1

4

T3

1

T6

6

auto[1]

660

1

T1

1

T6

3

T7

6

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	2	29	93.55	2
Automatically Generated Cross Bins	31	2	29	93.55	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	910	1			T1	5		T3	1		T6	9
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	126	1			T23	2		T79	4		T93	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	47	1			T30	1		T196	1		T96	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	24	1			T7	2		T196	1		T337	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	51	1			T24	7		T69	1		T196	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	24	1			T338	2		T337	2		T76	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T81	1		T339	2		T216	7
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T340	4		T214	2		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	82	1			T7	6		T236	3		T93	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	49	1			T24	2		T66	5		T75	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	26	1			T80	6		T323	3		T341	7
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T342	2		T329	4		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	12	1			T24	3		T30	2		T75	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	7	1			T80	2		T343	1		T344	2
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T236	1		T345	2		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	43	1			T69	1		T196	1		T236	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	35	1			T220	10		T226	2		T219	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	45	1			T217	6		T339	2		T346	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	6	1			T226	3		T337	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T347	1		T348	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	7	1			T323	4		T341	3		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T343	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	33	1			T220	8		T341	7		T342	10
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	11	1			T217	2		T330	5		T349	4
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T236	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T350	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T80	2		T219	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T351	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T24	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

110

1

T24

1

T91

10

T75

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

110

1

T7

6

T39

1

T80

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T316

6

T236

3

T167

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

80

1

T7

1

T23

1

T69

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

59

1

T29

6

T224

5

T80

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

115

1

T39

1

T220

8

T184

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T224

2

T196

1

T317

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

126

1

T3

1

T7

1

T39

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

59

1

T31

6

T69

1

T317

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T163

4

T167

5

T315

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T29

4

T38

1

T317

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

74

1

T45

4

T91

7

T92

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T45

2

T30

1

T91

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T23

1

T31

1

T92

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T87

2

T330

5

T352

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

92

1

T24

10

T31

7

T80

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

144

1

T6

4

T91

12

T93

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T30

2

T31

2

T39

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T78

2

T87

3

T214

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

73

1

T6

2

T66

5

T114

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T196

1

T96

1

T353

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T6

3

T24

2

T316

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T316

1

T239

2

T221

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T31

7

T38

1

T239

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T224

3

T196

1

T239

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T239

2

T319

5

T354

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T1

1

T146

1

T332

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T184

1

T167

2

T280

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T1

4

T32

1

T180

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T184

1

T319

3

T98

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T29

3

T91

1

T133

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded