Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 98.73 96.73 100.00 94.87 98.23 99.23 93.68


Total tests in report: 920
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.20 68.20 85.33 85.33 76.67 76.67 87.44 87.44 31.41 31.41 86.84 86.84 72.54 72.54 37.14 37.14 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3757843485
76.69 8.50 92.07 6.74 86.02 9.35 96.80 9.36 42.31 10.90 92.38 5.55 82.85 10.31 44.42 7.28 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2294154252
82.13 5.44 94.50 2.43 88.07 2.05 97.03 0.23 58.97 16.67 94.42 2.03 89.69 6.84 52.23 7.81 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.122961797
85.16 3.03 95.95 1.46 89.76 1.69 97.03 0.00 69.23 10.26 95.60 1.18 93.26 3.56 55.31 3.08 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3216418147
87.26 2.10 95.95 0.00 89.76 0.00 97.03 0.00 69.23 0.00 95.60 0.00 93.26 0.00 69.98 14.67 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.4279922380
89.02 1.76 96.85 0.90 90.72 0.96 97.03 0.00 76.28 7.05 96.41 0.81 95.76 2.50 70.09 0.11 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2745900952
90.38 1.36 96.92 0.07 92.09 1.37 97.72 0.68 76.28 0.00 96.52 0.11 95.76 0.00 77.36 7.28 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3145251834
91.28 0.90 97.44 0.52 94.06 1.97 97.72 0.00 79.49 3.21 97.12 0.59 95.76 0.00 77.36 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.755311497
91.97 0.69 97.74 0.30 94.24 0.18 97.72 0.00 81.41 1.92 97.26 0.15 96.34 0.58 79.06 1.70 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2603759617
92.58 0.61 97.82 0.07 94.29 0.05 97.72 0.00 82.69 1.28 97.34 0.07 96.53 0.19 81.67 2.60 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1998382907
93.08 0.50 97.89 0.07 94.34 0.05 97.72 0.00 83.97 1.28 97.41 0.07 96.72 0.19 83.53 1.86 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4126362414
93.56 0.47 97.97 0.07 94.44 0.10 98.17 0.46 85.90 1.92 97.56 0.15 97.01 0.29 83.85 0.32 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.648179087
93.98 0.43 98.13 0.17 94.59 0.15 98.17 0.00 87.18 1.28 97.63 0.07 97.11 0.10 85.07 1.22 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3369335382
94.32 0.33 98.21 0.07 94.62 0.03 98.17 0.00 89.10 1.92 97.74 0.11 97.21 0.10 85.18 0.11 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1303892192
94.60 0.28 98.21 0.00 94.64 0.03 99.77 1.60 89.10 0.00 97.74 0.00 97.30 0.10 85.44 0.27 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3229950087
94.84 0.24 98.26 0.06 94.72 0.08 99.77 0.00 89.74 0.64 97.82 0.07 97.40 0.10 86.18 0.74 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1679500940
95.04 0.20 98.30 0.04 94.72 0.00 99.77 0.00 91.03 1.28 97.89 0.07 97.40 0.00 86.18 0.00 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1399040132
95.24 0.20 98.34 0.04 94.72 0.00 99.77 0.00 92.31 1.28 97.97 0.07 97.40 0.00 86.18 0.00 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.4261759473
95.42 0.18 98.34 0.00 94.72 0.00 99.77 0.00 92.31 0.00 97.97 0.00 97.40 0.00 87.46 1.28 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.515756107
95.59 0.16 98.38 0.04 95.05 0.33 99.77 0.00 92.95 0.64 98.00 0.04 97.50 0.10 87.46 0.00 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.4070050255
95.73 0.14 98.38 0.00 95.93 0.88 99.77 0.00 92.95 0.00 98.00 0.00 97.50 0.00 87.57 0.11 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2511737468
95.87 0.14 98.40 0.02 95.93 0.00 99.77 0.00 92.95 0.00 98.00 0.00 97.50 0.00 88.52 0.96 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3140409026
95.99 0.12 98.43 0.04 95.96 0.03 99.77 0.00 93.59 0.64 98.04 0.04 97.59 0.10 88.52 0.00 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.3910451154
96.11 0.12 98.47 0.04 95.98 0.03 99.77 0.00 94.23 0.64 98.08 0.04 97.69 0.10 88.52 0.00 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.575292750
96.23 0.12 98.51 0.04 96.01 0.03 99.77 0.00 94.87 0.64 98.11 0.04 97.78 0.10 88.52 0.00 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2307364691
96.34 0.12 98.53 0.02 96.01 0.00 99.77 0.00 94.87 0.00 98.11 0.00 97.78 0.00 89.32 0.80 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1058013042
96.45 0.11 98.53 0.00 96.11 0.10 99.77 0.00 94.87 0.00 98.11 0.00 98.46 0.67 89.32 0.00 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.744908517
96.54 0.09 98.56 0.04 96.16 0.05 99.77 0.00 94.87 0.00 98.11 0.00 98.75 0.29 89.59 0.27 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.883569571
96.61 0.07 98.56 0.00 96.16 0.00 99.77 0.00 94.87 0.00 98.11 0.00 98.75 0.00 90.06 0.48 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3078362741
96.67 0.06 98.58 0.02 96.23 0.08 99.77 0.00 94.87 0.00 98.11 0.00 98.94 0.19 90.17 0.11 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1066051722
96.72 0.05 98.64 0.06 96.31 0.08 100.00 0.23 94.87 0.00 98.11 0.00 98.94 0.00 90.17 0.00 /workspace/coverage/default/12.sysrst_ctrl_alert_test.1835353481
96.77 0.05 98.64 0.00 96.31 0.00 100.00 0.00 94.87 0.00 98.11 0.00 98.94 0.00 90.49 0.32 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2353801594
96.81 0.04 98.66 0.02 96.36 0.05 100.00 0.00 94.87 0.00 98.11 0.00 98.94 0.00 90.70 0.21 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1503760600
96.84 0.04 98.66 0.00 96.36 0.00 100.00 0.00 94.87 0.00 98.11 0.00 98.94 0.00 90.97 0.27 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.446240914
96.88 0.04 98.66 0.00 96.36 0.00 100.00 0.00 94.87 0.00 98.11 0.00 98.94 0.00 91.23 0.27 /workspace/coverage/default/47.sysrst_ctrl_stress_all.3918708915
96.92 0.04 98.69 0.04 96.51 0.15 100.00 0.00 94.87 0.00 98.19 0.07 98.94 0.00 91.23 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.776757360
96.95 0.03 98.69 0.00 96.51 0.00 100.00 0.00 94.87 0.00 98.19 0.00 98.94 0.00 91.45 0.21 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3664062309
96.98 0.03 98.69 0.00 96.51 0.00 100.00 0.00 94.87 0.00 98.19 0.00 98.94 0.00 91.66 0.21 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3160897877
97.01 0.03 98.69 0.00 96.51 0.00 100.00 0.00 94.87 0.00 98.19 0.00 98.94 0.00 91.87 0.21 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.757006016
97.04 0.03 98.69 0.00 96.61 0.10 100.00 0.00 94.87 0.00 98.19 0.00 99.04 0.10 91.87 0.00 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1128778634
97.06 0.02 98.69 0.00 96.64 0.03 100.00 0.00 94.87 0.00 98.19 0.00 99.13 0.10 91.92 0.05 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2472397730
97.09 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.13 0.00 92.08 0.16 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1550221789
97.11 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.13 0.00 92.24 0.16 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3339809727
97.13 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.13 0.00 92.40 0.16 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.15165415
97.16 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.13 0.00 92.56 0.16 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4238388388
97.18 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.23 0.10 92.61 0.05 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3244244340
97.19 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.23 0.00 92.72 0.11 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1926212290
97.21 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.23 0.00 92.83 0.11 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.666900209
97.22 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.23 0.00 92.93 0.11 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.4133158755
97.24 0.02 98.69 0.00 96.64 0.00 100.00 0.00 94.87 0.00 98.19 0.00 99.23 0.00 93.04 0.11 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2075864603
97.25 0.01 98.73 0.04 96.66 0.03 100.00 0.00 94.87 0.00 98.23 0.04 99.23 0.00 93.04 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2464907934
97.26 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.09 0.05 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2058943
97.27 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.15 0.05 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3353065165
97.27 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.20 0.05 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3327921363
97.28 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.25 0.05 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1077666531
97.29 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.30 0.05 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2925104279
97.30 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.36 0.05 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1304114653
97.30 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.41 0.05 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.411327193
97.31 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.46 0.05 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.26485417
97.32 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.52 0.05 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1012349110
97.33 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.57 0.05 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.788628284
97.33 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.62 0.05 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.171480308
97.34 0.01 98.73 0.00 96.66 0.00 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.68 0.05 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3369027190
97.35 0.01 98.73 0.00 96.69 0.03 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.68 0.00 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1729299719
97.35 0.01 98.73 0.00 96.71 0.03 100.00 0.00 94.87 0.00 98.23 0.00 99.23 0.00 93.68 0.00 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1862923266

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2394262454
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3445306372
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1878492940
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.305715077
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1379210673
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.558146681
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2438058188
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.896969786
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2038702431
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4213495898
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.521979186
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.645029318
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.742182928
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.191283489
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3347082507
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.74288217
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1168420759
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2581024126
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.146813534
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3505964533
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.996364591
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.291092196
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1218667999
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008830524
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.489548936
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.189881553
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3458568082
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4101294855
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.971462592
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3287797907
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.853851700
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2010082777
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1233442343
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2532631179
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2328503453
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272613612
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.859790972
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1156471873
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1472636981
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3459294690
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.475310991
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.802677385
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1346198568
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4160815371
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2359546824
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4235033853
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953799702
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3062758505
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.957221114
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1646899675
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3004524500
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4029236476
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1836580667
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1637139749
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3777624354
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.861328522
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2981548772
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1843230971
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2066067255
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.711500475
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.527640771
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3783077814
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.219650870
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187469769
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.466805871
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.275856089
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3055448946
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3957807200
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.590609723
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.651687791
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2944802991
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2225749294
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1107962267
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.140476891
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4063582568
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.985032650
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3448751350
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.731873460
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942918391
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1076120964
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1708570854
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3858455790
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3927775205
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3855805564
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3421691029
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3263807292
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2065766618
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1881509485
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/workspace/coverage/default/41.sysrst_ctrl_smoke.2996937089
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2765534106
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2270125747
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1536184012
/workspace/coverage/default/42.sysrst_ctrl_alert_test.1371344305
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1218212692
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2718049286
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3530756021
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3040105009
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3234990776
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.528048371
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2812260774
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.69064410
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2876632508
/workspace/coverage/default/42.sysrst_ctrl_smoke.2075391473
/workspace/coverage/default/42.sysrst_ctrl_stress_all.3588640678
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2792969018
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.682497256
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2728831497
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1243338985
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2888440224
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.837596433
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2209217330
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3629269096
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3011606269
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.167799270
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1980039096
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3581195810
/workspace/coverage/default/43.sysrst_ctrl_smoke.2328337548
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3509115867
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3243545372
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2756220271
/workspace/coverage/default/44.sysrst_ctrl_alert_test.394752285
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1287206113
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1367403253
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1832249058
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2427108064
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2642884751
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.582995211
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.879919718
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2772187525
/workspace/coverage/default/44.sysrst_ctrl_smoke.1976091156
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1728788956
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3195054462
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2121246435
/workspace/coverage/default/45.sysrst_ctrl_alert_test.992094066
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3323838644
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3084782844
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3819442547
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2064173717
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2029319640
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1469303238
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3461179592
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1554931444
/workspace/coverage/default/45.sysrst_ctrl_smoke.2260974565
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2678164208
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3183112266
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.509289755
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1573723330
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1420102530
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1379643490
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.167372089
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3172664632
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3354937171
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2855127620
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2067123233
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3241718171
/workspace/coverage/default/46.sysrst_ctrl_smoke.4075032656
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3764835102
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.665744072
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3982252133
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3442259913
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.999203918
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.92207865
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3004753691
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1746701604
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4086322517
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.637902298
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3001969939
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1681100070
/workspace/coverage/default/47.sysrst_ctrl_smoke.3300162396
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1932479706
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2496245165
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3922269716
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3641499061
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.22732424
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3811741777
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.4114934230
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2934664464
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2318005491
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2005164297
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1851715745
/workspace/coverage/default/48.sysrst_ctrl_smoke.3789431193
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3815472534
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1770356147
/workspace/coverage/default/49.sysrst_ctrl_alert_test.553734135
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2909665750
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3815451814
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1606517538
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2237047724
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2210585028
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1018013218
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4154941718
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.4047301810
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1063551275
/workspace/coverage/default/49.sysrst_ctrl_smoke.4036432541
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2645307681
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2923877297
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.126499906
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1943176810
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1380837083
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3099996391
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1163655273
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1495254235
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3019595886
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.4157788344
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.217070959
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.805064229
/workspace/coverage/default/5.sysrst_ctrl_smoke.3579578420
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3027533849
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3923356381
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1671964999
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1738541100
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2041927901
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.30560089
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1046694392
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.479967762
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3949520802
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2748527514
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3239089317
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.785915584
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2977599550
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1778589650
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3119637700
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2565117708
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2494158491
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2249612227
/workspace/coverage/default/6.sysrst_ctrl_smoke.3578127523
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1384013049
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1462745307
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4204603422
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3982382793
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3771184716
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1452740063
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4128080445
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1888511850
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2254605216
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.309806754
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2866804933
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1280150768
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2351132907
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1959230710
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3583381011
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2256248776
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3045670192
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1836420561
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2243913101
/workspace/coverage/default/7.sysrst_ctrl_smoke.1772844565
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1977258202
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1670056247
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3899069910
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1423562522
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3040877480
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1359291900
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.896008835
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1286690021
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4044618168
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2064415350
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1764963327
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1701745145
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3164108788
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.221801657
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3284676081
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3902103830
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1949255796
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1110067920
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1486298697
/workspace/coverage/default/8.sysrst_ctrl_smoke.3245721330
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1415486331
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.661501005
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1957286698
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3193790483
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.295948431
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.565094933
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3644392915
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.742543816
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3025278682
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3576587417
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.434596812
/workspace/coverage/default/9.sysrst_ctrl_alert_test.134250384
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1099502547
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2306255954
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.139254686
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.637640917
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3314701630
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2665530907
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3085205360
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4291706891
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.35717132
/workspace/coverage/default/9.sysrst_ctrl_smoke.1829254918
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1014336485
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.485740668
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1067987394
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2942232309
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2940594990
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2161698614
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3259068708
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.545754461
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3753445646
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1756510895



Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.401793095 Apr 28 12:22:58 PM PDT 24 Apr 28 12:23:11 PM PDT 24 2454710501 ps
T5 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3819442547 Apr 28 12:23:28 PM PDT 24 Apr 28 12:23:30 PM PDT 24 2911685184 ps
T1 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.883569571 Apr 28 12:22:41 PM PDT 24 Apr 28 12:23:14 PM PDT 24 38729261064 ps
T13 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3252189136 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:20 PM PDT 24 3187732104 ps
T14 /workspace/coverage/default/18.sysrst_ctrl_smoke.3218943490 Apr 28 12:21:25 PM PDT 24 Apr 28 12:21:32 PM PDT 24 2109421170 ps
T15 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3737202957 Apr 28 12:22:46 PM PDT 24 Apr 28 12:23:00 PM PDT 24 2028170623 ps
T2 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1679500940 Apr 28 12:22:00 PM PDT 24 Apr 28 12:23:16 PM PDT 24 959441847551 ps
T3 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1670056247 Apr 28 12:22:36 PM PDT 24 Apr 28 12:25:10 PM PDT 24 56192668543 ps
T16 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1663395513 Apr 28 12:23:58 PM PDT 24 Apr 28 12:25:14 PM PDT 24 26110942292 ps
T6 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3757843485 Apr 28 12:23:05 PM PDT 24 Apr 28 12:23:49 PM PDT 24 384874820074 ps
T17 /workspace/coverage/default/1.sysrst_ctrl_stress_all.1707047617 Apr 28 12:21:52 PM PDT 24 Apr 28 12:22:15 PM PDT 24 7055696693 ps
T18 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3880449792 Apr 28 12:20:37 PM PDT 24 Apr 28 12:20:47 PM PDT 24 3462047482 ps
T42 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1649188878 Apr 28 12:21:08 PM PDT 24 Apr 28 12:21:19 PM PDT 24 3615269083 ps
T59 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2812260774 Apr 28 12:23:12 PM PDT 24 Apr 28 12:23:17 PM PDT 24 2477491638 ps
T43 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3791395682 Apr 28 12:23:21 PM PDT 24 Apr 28 12:23:31 PM PDT 24 3480424306 ps
T44 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2971766856 Apr 28 12:21:34 PM PDT 24 Apr 28 12:21:53 PM PDT 24 29073584748 ps
T74 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.669071475 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 2275032424 ps
T7 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2294154252 Apr 28 12:22:52 PM PDT 24 Apr 28 12:28:18 PM PDT 24 117639947129 ps
T50 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.204029068 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:49 PM PDT 24 3365922521 ps
T8 /workspace/coverage/default/15.sysrst_ctrl_stress_all.3502473554 Apr 28 12:21:02 PM PDT 24 Apr 28 12:21:09 PM PDT 24 9623240068 ps
T9 /workspace/coverage/default/43.sysrst_ctrl_stress_all.3509115867 Apr 28 12:23:24 PM PDT 24 Apr 28 12:23:37 PM PDT 24 9424967103 ps
T10 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1778589650 Apr 28 12:19:20 PM PDT 24 Apr 28 12:19:24 PM PDT 24 2875532992 ps
T23 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.203140222 Apr 28 12:22:33 PM PDT 24 Apr 28 12:25:20 PM PDT 24 61966334739 ps
T51 /workspace/coverage/default/8.sysrst_ctrl_alert_test.1764963327 Apr 28 12:22:37 PM PDT 24 Apr 28 12:22:45 PM PDT 24 2032064133 ps
T24 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.171480308 Apr 28 12:23:39 PM PDT 24 Apr 28 12:28:11 PM PDT 24 100380120392 ps
T45 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1524035 Apr 28 12:23:09 PM PDT 24 Apr 28 12:24:23 PM PDT 24 64487516272 ps
T52 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3119637700 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:00 PM PDT 24 2626944718 ps
T102 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2919116885 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:06 PM PDT 24 2265750902 ps
T62 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3469812591 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 2626534226 ps
T103 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3811741777 Apr 28 12:23:49 PM PDT 24 Apr 28 12:23:58 PM PDT 24 2745449346 ps
T104 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1755700399 Apr 28 12:23:47 PM PDT 24 Apr 28 12:23:56 PM PDT 24 2255959687 ps
T60 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.637902298 Apr 28 12:23:19 PM PDT 24 Apr 28 12:23:28 PM PDT 24 2441632993 ps
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T56 /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1780769424 Apr 28 12:23:58 PM PDT 24 Apr 28 12:24:07 PM PDT 24 7861044588 ps
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T38 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.122961797 Apr 28 12:20:37 PM PDT 24 Apr 28 12:21:37 PM PDT 24 130812637640 ps
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T120 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3461881001 Apr 28 12:23:06 PM PDT 24 Apr 28 12:23:14 PM PDT 24 3595521755 ps
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T262 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3974178118 Apr 28 12:23:25 PM PDT 24 Apr 28 12:23:30 PM PDT 24 2939544756 ps
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T69 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1957286698 Apr 28 12:24:45 PM PDT 24 Apr 28 12:24:59 PM PDT 24 69348472128 ps
T264 /workspace/coverage/default/12.sysrst_ctrl_stress_all.2507819989 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:41 PM PDT 24 10162017536 ps
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T34 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.575292750 Apr 28 12:17:34 PM PDT 24 Apr 28 12:17:37 PM PDT 24 4480600019 ps
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T75 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1191189898 Apr 28 12:23:08 PM PDT 24 Apr 28 12:23:55 PM PDT 24 69537430381 ps
T195 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2071337253 Apr 28 12:22:32 PM PDT 24 Apr 28 12:22:38 PM PDT 24 2978690933 ps
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T77 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2472397730 Apr 28 12:23:33 PM PDT 24 Apr 28 12:23:38 PM PDT 24 3378621505 ps
T105 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1077666531 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:09 PM PDT 24 3722571161 ps
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T110 /workspace/coverage/default/9.sysrst_ctrl_alert_test.134250384 Apr 28 12:22:58 PM PDT 24 Apr 28 12:23:09 PM PDT 24 2158135529 ps
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T376 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.221801657 Apr 28 12:19:38 PM PDT 24 Apr 28 12:19:47 PM PDT 24 2739629220 ps
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T79 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2254605216 Apr 28 12:23:39 PM PDT 24 Apr 28 12:25:25 PM PDT 24 76548668790 ps
T80 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3353065165 Apr 28 12:22:54 PM PDT 24 Apr 28 12:24:24 PM PDT 24 61463814063 ps
T72 /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3725072896 Apr 28 12:22:55 PM PDT 24 Apr 28 12:23:12 PM PDT 24 7001088090 ps
T377 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4182308832 Apr 28 12:21:52 PM PDT 24 Apr 28 12:21:58 PM PDT 24 2616701632 ps
T275 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3462101357 Apr 28 12:22:37 PM PDT 24 Apr 28 12:22:49 PM PDT 24 2514353787 ps
T317 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1734479139 Apr 28 12:21:31 PM PDT 24 Apr 28 12:27:25 PM PDT 24 137657475796 ps
T378 /workspace/coverage/default/12.sysrst_ctrl_alert_test.1835353481 Apr 28 12:20:25 PM PDT 24 Apr 28 12:20:32 PM PDT 24 2009865802 ps
T220 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2603759617 Apr 28 12:20:21 PM PDT 24 Apr 28 12:25:24 PM PDT 24 122223609158 ps
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T379 /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4262614523 Apr 28 12:22:20 PM PDT 24 Apr 28 12:22:24 PM PDT 24 2566328287 ps
T380 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3195054462 Apr 28 12:23:18 PM PDT 24 Apr 28 12:23:55 PM PDT 24 13228798400 ps
T381 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4086322517 Apr 28 12:23:29 PM PDT 24 Apr 28 12:23:32 PM PDT 24 2631986964 ps
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T276 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3993340697 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:20 PM PDT 24 2536821616 ps
T383 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1909333903 Apr 28 12:20:40 PM PDT 24 Apr 28 12:20:50 PM PDT 24 3349169647 ps
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T385 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.516405979 Apr 28 12:21:52 PM PDT 24 Apr 28 12:22:02 PM PDT 24 2467151052 ps
T236 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3140409026 Apr 28 12:24:01 PM PDT 24 Apr 28 12:26:32 PM PDT 24 219287832758 ps
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T182 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2790296443 Apr 28 12:22:56 PM PDT 24 Apr 28 12:23:08 PM PDT 24 2105525605 ps
T35 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2270125747 Apr 28 12:23:13 PM PDT 24 Apr 28 12:24:34 PM PDT 24 29369061924 ps
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T186 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1980039096 Apr 28 12:23:27 PM PDT 24 Apr 28 12:23:29 PM PDT 24 2163629892 ps
T187 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2880306 Apr 28 12:22:39 PM PDT 24 Apr 28 12:22:52 PM PDT 24 2611640619 ps
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T189 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2426963363 Apr 28 12:22:11 PM PDT 24 Apr 28 12:25:41 PM PDT 24 1613312164359 ps
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T277 /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.149816370 Apr 28 12:22:26 PM PDT 24 Apr 28 12:22:28 PM PDT 24 2659354669 ps
T388 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2490625628 Apr 28 12:23:18 PM PDT 24 Apr 28 12:23:23 PM PDT 24 2618269469 ps
T279 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.503349507 Apr 28 12:20:01 PM PDT 24 Apr 28 12:20:08 PM PDT 24 4757292111 ps
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T390 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3159214861 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:44 PM PDT 24 2156847866 ps
T391 /workspace/coverage/default/7.sysrst_ctrl_alert_test.2866804933 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:00 PM PDT 24 2042711621 ps
T392 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1690038694 Apr 28 12:22:45 PM PDT 24 Apr 28 12:22:55 PM PDT 24 2720226706 ps
T393 /workspace/coverage/default/27.sysrst_ctrl_stress_all.2213276167 Apr 28 12:23:24 PM PDT 24 Apr 28 12:23:43 PM PDT 24 6621344069 ps
T394 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.518493238 Apr 28 12:24:18 PM PDT 24 Apr 28 12:24:29 PM PDT 24 3395831849 ps
T395 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1469303238 Apr 28 12:23:23 PM PDT 24 Apr 28 12:23:33 PM PDT 24 2455935010 ps
T41 /workspace/coverage/default/31.sysrst_ctrl_stress_all.1081752021 Apr 28 12:22:55 PM PDT 24 Apr 28 12:23:15 PM PDT 24 13175602677 ps
T396 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1747953691 Apr 28 12:23:05 PM PDT 24 Apr 28 12:23:12 PM PDT 24 2513291294 ps
T397 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.4089673109 Apr 28 12:23:42 PM PDT 24 Apr 28 12:23:49 PM PDT 24 2049487613 ps
T266 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1280150768 Apr 28 12:19:32 PM PDT 24 Apr 28 12:19:42 PM PDT 24 3171792141 ps
T398 /workspace/coverage/default/29.sysrst_ctrl_alert_test.4075924374 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 2047367757 ps
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T281 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.126499906 Apr 28 12:23:56 PM PDT 24 Apr 28 12:24:08 PM PDT 24 4574371719 ps
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T427 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2910375302 Apr 28 12:22:28 PM PDT 24 Apr 28 12:22:34 PM PDT 24 3055767095 ps
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