Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T3

9

T16

19

T6

17

auto[1]

1006

1

T3

11

T16

21

T6

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T3

4

T16

9

T6

12

from_0to1

497

1

T3

3

T16

9

T6

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T3

12

T16

22

T6

21

auto[1]

998

1

T3

8

T16

18

T6

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T3

11

T16

22

T6

28

auto[1]

1002

1

T3

9

T16

18

T6

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T6

3

T12

3

T141

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T3

2

T16

3

T6

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T6

1

T44

2

T12

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T12

2

T150

1

T274

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T3

1

T16

1

T363

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T16

1

T6

1

T12

2

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T16

4

T6

4

T12

2

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T6

1

T12

1

T57

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T16

1

T6

2

T44

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T3

1

T16

1

T6

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T3

1

T16

2

T6

2

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T16

2

T6

1

T141

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T16

2

T6

4

T44

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T3

1

T6

1

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T16

1

T6

1

T44

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T3

1

T44

1

T12

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T3

8

T16

16

T6

22

auto[1]

1008

1

T3

12

T16

24

T6

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T3

5

T16

12

T6

9

from_0to1

498

1

T3

4

T16

12

T6

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T3

17

T16

23

T6

22

auto[1]

1008

1

T3

3

T16

17

T6

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

966

1

T3

5

T16

22

T6

18

auto[1]

1063

1

T3

15

T16

18

T6

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T3

1

T16

1

T6

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T16

3

T6

2

T149

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T16

2

T6

1

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T16

1

T44

1

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T6

1

T44

2

T12

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T16

1

T6

3

T44

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T16

2

T44

1

T150

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T3

1

T12

1

T141

2

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T16

1

T141

1

T149

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T3

4

T16

3

T6

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T6

1

T44

1

T12

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T16

1

T6

3

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T3

1

T16

1

T6

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T3

1

T16

1

T6

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T16

5

T6

1

T149

2

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T3

1

T16

2

T6

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T3

5

T16

21

T6

19

auto[1]

1046

1

T3

15

T16

19

T6

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

481

1

T3

4

T16

12

T6

9

from_0to1

476

1

T3

4

T16

12

T6

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T3

9

T16

26

T6

24

auto[1]

1007

1

T3

11

T16

14

T6

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010

1

T3

7

T16

19

T6

21

auto[1]

1019

1

T3

13

T16

21

T6

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T3

1

T16

4

T6

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T3

1

T16

3

T6

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T16

1

T6

1

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T3

1

T6

2

T141

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T6

2

T274

1

T38

2

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T16

3

T44

2

T141

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T6

2

T44

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T3

1

T16

3

T6

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T3

1

T16

2

T6

2

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T6

2

T44

1

T12

2

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T16

1

T12

1

T141

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T16

1

T44

1

T12

2

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T16

4

T6

1

T44

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T16

1

T6

1

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T3

2

T16

1

T6

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T3

1

T6

2

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T3

11

T16

17

T6

18

auto[1]

1057

1

T3

9

T16

23

T6

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

503

1

T3

3

T16

13

T6

9

from_0to1

503

1

T3

4

T16

12

T6

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T3

12

T16

19

T6

21

auto[1]

996

1

T3

8

T16

21

T6

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T3

12

T16

18

T6

19

auto[1]

1033

1

T3

8

T16

22

T6

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T16

1

T12

1

T149

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T16

2

T12

1

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T16

2

T6

2

T12

3

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T3

1

T16

1

T6

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T3

1

T16

3

T12

3

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T44

1

T141

1

T149

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T3

1

T16

1

T6

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T44

1

T12

1

T141

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T3

1

T6

2

T44

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T16

3

T6

2

T44

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T3

1

T44

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T16

4

T6

1

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T3

2

T6

3

T44

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T16

2

T6

2

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T16

4

T6

2

T12

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T16

2

T12

1

T150

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992

1

T3

15

T16

23

T6

20

auto[1]

1037

1

T3

5

T16

17

T6

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T3

5

T16

10

T6

11

from_0to1

483

1

T3

5

T16

9

T6

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T3

9

T16

24

T6

18

auto[1]

1014

1

T3

11

T16

16

T6

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T3

9

T16

24

T6

22

auto[1]

999

1

T3

11

T16

16

T6

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T16

1

T12

1

T149

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T16

1

T6

1

T44

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T3

1

T16

4

T12

4

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T3

1

T16

1

T6

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T3

1

T16

1

T6

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T3

2

T6

3

T44

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T3

1

T16

1

T44

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T16

2

T6

2

T12

2

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T16

1

T6

4

T141

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T3

1

T16

2

T6

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T3

1

T6

2

T44

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T3

1

T6

2

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T16

2

T44

1

T149

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T16

1

T12

3

T141

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T3

1

T16

2

T6

4

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T6

2

T44

1

T12

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T3

11

T16

27

T6

24

auto[1]

993

1

T3

9

T16

13

T6

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

494

1

T3

4

T16

10

T6

9

from_0to1

502

1

T3

5

T16

9

T6

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T3

12

T16

23

T6

17

auto[1]

991

1

T3

8

T16

17

T6

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T3

8

T16

21

T6

23

auto[1]

999

1

T3

12

T16

19

T6

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T16

3

T6

3

T44

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T3

1

T16

1

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T16

2

T6

1

T12

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T3

1

T44

1

T141

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T3

1

T6

3

T44

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T3

2

T16

3

T6

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T16

3

T6

1

T12

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T12

1

T141

1

T149

3

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T3

1

T6

1

T12

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T16

1

T44

1

T12

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T16

1

T6

1

T12

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T3

1

T16

2

T6

3

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T3

1

T12

3

T363

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T3

1

T16

1

T6

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T16

1

T6

2

T141

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T16

1

T44

1

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T3

11

T16

22

T6

23

auto[1]

971

1

T3

9

T16

18

T6

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

492

1

T3

6

T16

10

T6

8

from_0to1

492

1

T3

6

T16

9

T6

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T3

11

T16

20

T6

19

auto[1]

971

1

T3

9

T16

20

T6

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992

1

T3

12

T16

23

T6

21

auto[1]

1037

1

T3

8

T16

17

T6

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T3

1

T6

1

T149

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T3

1

T16

2

T6

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T3

1

T16

1

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T16

3

T6

1

T274

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T3

2

T16

3

T150

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T16

1

T12

2

T141

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T16

1

T6

3

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T3

2

T6

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T16

1

T6

2

T150

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T3

1

T16

1

T6

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T3

2

T16

2

T6

2

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T12

1

T363

1

T65

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T3

1

T16

1

T12

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T16

1

T6

2

T44

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T16

1

T6

1

T44

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T3

1

T16

1

T6

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T3

11

T16

20

T6

23

auto[1]

997

1

T3

9

T16

20

T6

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

474

1

T3

6

T16

10

T6

7

from_0to1

482

1

T3

7

T16

10

T6

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T3

8

T16

21

T6

21

auto[1]

1051

1

T3

12

T16

19

T6

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T3

14

T16

21

T6

16

auto[1]

994

1

T3

6

T16

19

T6

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T16

2

T12

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T16

2

T6

3

T44

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T3

2

T16

1

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T3

1

T6

2

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T3

2

T16

1

T6

2

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T16

1

T6

2

T149

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T3

2

T16

2

T6

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T16

1

T149

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T3

1

T16

2

T12

2

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T6

1

T12

1

T141

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T3

1

T6

1

T44

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T3

1

T16

3

T12

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T3

1

T16

2

T6

1

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T3

1

T16

2

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T12

4

T149

2

T274

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T3

1

T16

1

T6

2