Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123080

1

T4

26

T5

1

T1

214

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146335	1			T4	22		T5	3		T1	388
values[0x0]	68109	1			T4	14		T5	1		T1	22
values[0x1]	69226	1			T4	9		T5	1		T1	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130100	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153570

1

T4

32

T5

1

T1

248

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1945	1			T2	1		T3	5		T6	2
valid_sources[0x01]	974	1			T2	1		T3	3		T6	20
valid_sources[0x02]	948	1			T13	1		T2	1		T3	3
valid_sources[0x03]	967	1			T3	8		T7	3		T23	3
valid_sources[0x04]	989	1			T14	1		T2	1		T3	5
valid_sources[0x05]	1152	1			T2	2		T6	4		T44	2
valid_sources[0x06]	892	1			T2	5		T6	8		T44	2
valid_sources[0x07]	1091	1			T2	1		T3	5		T6	1
valid_sources[0x08]	1239	1			T2	3		T3	6		T6	2
valid_sources[0x09]	1945	1			T2	3		T3	4		T6	7
valid_sources[0x0a]	1307	1			T2	2		T3	3		T6	8
valid_sources[0x0b]	889	1			T3	1		T6	1		T44	1
valid_sources[0x0c]	789	1			T2	2		T3	5		T44	3
valid_sources[0x0d]	922	1			T2	1		T3	3		T6	5
valid_sources[0x0e]	1070	1			T13	1		T2	1		T3	5
valid_sources[0x0f]	1108	1			T2	2		T3	3		T44	1
valid_sources[0x10]	1495	1			T1	424		T2	1		T3	5
valid_sources[0x11]	889	1			T2	2		T6	11		T44	3
valid_sources[0x12]	909	1			T3	4		T59	1		T44	2
valid_sources[0x13]	973	1			T3	1		T44	2		T74	1
valid_sources[0x14]	1534	1			T2	3		T3	3		T44	2
valid_sources[0x15]	1120	1			T3	2		T16	5		T6	3
valid_sources[0x16]	826	1			T3	4		T6	2		T44	5
valid_sources[0x17]	833	1			T2	4		T3	1		T6	14
valid_sources[0x18]	1045	1			T2	2		T3	2		T6	9
valid_sources[0x19]	2370	1			T2	1		T3	6		T6	3
valid_sources[0x1a]	935	1			T2	4		T3	2		T6	7
valid_sources[0x1b]	945	1			T3	5		T6	2		T44	2
valid_sources[0x1c]	969	1			T2	2		T6	6		T18	1
valid_sources[0x1d]	997	1			T2	1		T3	3		T6	10
valid_sources[0x1e]	793	1			T2	2		T3	8		T6	11
valid_sources[0x1f]	919	1			T2	4		T3	6		T6	10
valid_sources[0x20]	940	1			T3	1		T16	5		T6	19
valid_sources[0x21]	981	1			T2	2		T3	2		T6	11
valid_sources[0x22]	860	1			T2	2		T3	2		T18	2
valid_sources[0x23]	978	1			T3	1		T6	1		T23	1
valid_sources[0x24]	2012	1			T2	3		T3	2		T6	19
valid_sources[0x25]	929	1			T2	1		T3	4		T6	4
valid_sources[0x26]	1039	1			T2	2		T3	6		T6	17
valid_sources[0x27]	820	1			T2	1		T3	12		T7	3
valid_sources[0x28]	912	1			T2	1		T3	4		T7	2
valid_sources[0x29]	1738	1			T2	2		T3	2		T6	1
valid_sources[0x2a]	907	1			T3	3		T6	5		T44	1
valid_sources[0x2b]	943	1			T2	1		T3	2		T6	8
valid_sources[0x2c]	870	1			T2	3		T3	3		T16	20
valid_sources[0x2d]	1103	1			T2	2		T3	4		T6	5
valid_sources[0x2e]	1257	1			T2	2		T3	4		T6	2
valid_sources[0x2f]	977	1			T2	4		T3	5		T6	4
valid_sources[0x30]	936	1			T2	2		T3	4		T6	4
valid_sources[0x31]	902	1			T2	3		T3	6		T6	7
valid_sources[0x32]	1011	1			T2	2		T3	4		T6	1
valid_sources[0x33]	996	1			T2	1		T3	2		T6	1
valid_sources[0x34]	1090	1			T2	1		T3	1		T6	1
valid_sources[0x35]	945	1			T2	2		T3	3		T7	4
valid_sources[0x36]	886	1			T2	2		T3	6		T44	3
valid_sources[0x37]	1064	1			T3	4		T6	5		T44	1
valid_sources[0x38]	998	1			T2	2		T3	1		T6	15
valid_sources[0x39]	1108	1			T2	1		T3	2		T16	13
valid_sources[0x3a]	867	1			T13	1		T3	4		T6	11
valid_sources[0x3b]	1401	1			T3	3		T44	1		T7	3
valid_sources[0x3c]	1128	1			T2	1		T3	1		T44	1
valid_sources[0x3d]	1244	1			T2	2		T3	2		T6	12
valid_sources[0x3e]	1632	1			T2	3		T3	1		T17	1
valid_sources[0x3f]	937	1			T2	2		T3	4		T16	9
valid_sources[0x40]	1096	1			T2	2		T6	2		T44	2
valid_sources[0x41]	951	1			T17	18		T7	1		T23	4
valid_sources[0x42]	840	1			T5	1		T2	2		T3	9
valid_sources[0x43]	1229	1			T2	3		T3	1		T44	1
valid_sources[0x44]	942	1			T2	2		T3	1		T44	3
valid_sources[0x45]	1077	1			T2	1		T3	3		T6	2
valid_sources[0x46]	908	1			T2	2		T3	2		T16	4
valid_sources[0x47]	995	1			T2	1		T3	6		T7	3
valid_sources[0x48]	1624	1			T3	2		T44	2		T7	7
valid_sources[0x49]	933	1			T2	2		T3	3		T6	3
valid_sources[0x4a]	1706	1			T2	2		T3	7		T6	17
valid_sources[0x4b]	1047	1			T2	3		T3	3		T6	2
valid_sources[0x4c]	950	1			T2	2		T3	5		T6	30
valid_sources[0x4d]	929	1			T2	1		T3	3		T6	4
valid_sources[0x4e]	945	1			T2	2		T3	2		T6	9
valid_sources[0x4f]	1868	1			T2	2		T3	1		T44	2
valid_sources[0x50]	958	1			T2	1		T3	1		T44	2
valid_sources[0x51]	983	1			T2	1		T3	4		T44	2
valid_sources[0x52]	941	1			T2	3		T3	4		T44	3
valid_sources[0x53]	912	1			T2	1		T6	20		T44	2
valid_sources[0x54]	1783	1			T3	8		T6	17		T44	2
valid_sources[0x55]	1085	1			T2	1		T3	1		T6	4
valid_sources[0x56]	1431	1			T3	4		T6	38		T44	5
valid_sources[0x57]	1386	1			T2	1		T3	4		T44	3
valid_sources[0x58]	917	1			T3	4		T6	6		T44	6
valid_sources[0x59]	895	1			T2	1		T3	1		T6	5
valid_sources[0x5a]	999	1			T2	4		T3	3		T44	2
valid_sources[0x5b]	1036	1			T2	4		T44	1		T7	7
valid_sources[0x5c]	901	1			T2	1		T3	3		T44	3
valid_sources[0x5d]	1679	1			T3	2		T6	5		T7	1
valid_sources[0x5e]	870	1			T2	1		T3	2		T7	1
valid_sources[0x5f]	1082	1			T3	4		T59	1		T44	4
valid_sources[0x60]	1090	1			T2	4		T3	3		T7	4
valid_sources[0x61]	911	1			T2	3		T3	3		T6	3
valid_sources[0x62]	1020	1			T14	1		T2	3		T3	5
valid_sources[0x63]	879	1			T2	1		T3	3		T44	3
valid_sources[0x64]	785	1			T13	2		T2	1		T6	2
valid_sources[0x65]	2334	1			T2	1		T44	1		T7	4
valid_sources[0x66]	905	1			T2	3		T3	1		T6	3
valid_sources[0x67]	834	1			T2	1		T3	2		T16	8
valid_sources[0x68]	936	1			T13	1		T2	1		T3	3
valid_sources[0x69]	958	1			T3	3		T59	6		T44	4
valid_sources[0x6a]	997	1			T2	3		T3	3		T44	1
valid_sources[0x6b]	954	1			T2	3		T3	1		T44	3
valid_sources[0x6c]	931	1			T13	1		T2	1		T6	11
valid_sources[0x6d]	990	1			T3	3		T6	13		T17	2
valid_sources[0x6e]	953	1			T2	3		T3	2		T44	2
valid_sources[0x6f]	949	1			T2	8		T3	1		T6	12
valid_sources[0x70]	855	1			T2	1		T3	6		T7	3
valid_sources[0x71]	1040	1			T2	1		T3	1		T43	1
valid_sources[0x72]	823	1			T2	1		T3	4		T6	12
valid_sources[0x73]	849	1			T2	3		T3	4		T6	20
valid_sources[0x74]	961	1			T2	1		T3	4		T6	1
valid_sources[0x75]	869	1			T2	2		T7	1		T23	1
valid_sources[0x76]	1392	1			T3	3		T6	10		T7	8
valid_sources[0x77]	1331	1			T2	2		T3	6		T6	1
valid_sources[0x78]	815	1			T2	2		T3	1		T7	1
valid_sources[0x79]	914	1			T2	2		T3	1		T7	5
valid_sources[0x7a]	865	1			T2	2		T3	1		T6	1
valid_sources[0x7b]	845	1			T2	1		T3	15		T6	3
valid_sources[0x7c]	1003	1			T2	3		T6	8		T44	6
valid_sources[0x7d]	1206	1			T2	1		T3	9		T6	13
valid_sources[0x7e]	987	1			T2	2		T44	1		T7	4
valid_sources[0x7f]	970	1			T2	1		T3	1		T6	3
valid_sources[0x80]	1209	1			T2	1		T16	30		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66120

1

T4

14

T1

193

T13

4

values[0x0]

all_enables

biggest_size

33243

1

T4

9

T1

16

T13

3

values[0x1]

all_enables

biggest_size

23717

1

T4

3

T5

1

T1

5