Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T16,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T13,T2,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T16,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T2,T16
1	0	Covered	T4,T1,T13
1	1	Covered	T13,T2,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T6
0	1	Covered	T77
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T6
0	1	Covered	T13,T16,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T16,T6
1	-	Covered	T13,T16,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T2,T16
DetectSt	168	Covered	T13,T16,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T13,T16,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T16,T6
DebounceSt->IdleSt	163	Covered	T2,T65,T38
DetectSt->IdleSt	186	Covered	T77,T54
DetectSt->StableSt	191	Covered	T13,T16,T6
IdleSt->DebounceSt	148	Covered	T13,T2,T16
StableSt->IdleSt	206	Covered	T13,T16,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T16,T6
0	1	Covered	T13,T2,T16
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T2,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T53
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T38,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T2,T16
DetectSt	-	-	-	-	1	-	-	Covered	T77,T54
DetectSt	-	-	-	-	0	1	-	Covered	T13,T16,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T16,T6
StableSt	-	-	-	-	-	-	0	Covered	T13,T16,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	331	0	0
CntIncr_A	8343984	137833	0	0
CntNoWrap_A	8343984	7672187	0	0
DetectStDropOut_A	8343984	1	0	0
DetectedOut_A	8343984	980	0	0
DetectedPulseOut_A	8343984	153	0	0
DisabledIdleSt_A	8343984	7526665	0	0
DisabledNoDetection_A	8343984	7529053	0	0
EnterDebounceSt_A	8343984	184	0	0
EnterDetectSt_A	8343984	155	0	0
EnterStableSt_A	8343984	153	0	0
PulseIsPulse_A	8343984	153	0	0
StayInStableSt	8343984	827	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8343984	7145	0	0
gen_low_level_sva.LowLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	153	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	331	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	6	0	0
T9	0	2	0	0
T13	637	2	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	2	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	0	4	0	0
T49	0	2	0	0
T90	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	137833	0	0
T2	191888	2118	0	0
T3	11238	0	0	0
T6	76975	186	0	0
T9	0	97	0	0
T13	637	50	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	13	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	11	0	0
T43	0	15	0	0
T44	0	11	0	0
T47	0	73	0	0
T49	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672187	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69701	0	0
T13	637	234	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1009	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1	0	0
T36	744	0	0	0
T77	675	1	0	0
T105	744	0	0	0
T106	769	0	0	0
T107	441	0	0	0
T108	642	0	0	0
T109	407	0	0	0
T110	432	0	0	0
T111	504	0	0	0
T112	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	980	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	16	0	0
T9	0	6	0	0
T13	637	11	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	7	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	9	0	0
T43	0	13	0	0
T44	0	5	0	0
T47	0	17	0	0
T49	0	5	0	0
T90	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	153	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T9	0	1	0	0
T13	637	1	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T90	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7526665	0	0
T1	7746	7336	0	0
T2	191888	184333	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69367	0	0
T13	637	65	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	957	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7529053	0	0
T1	7746	7338	0	0
T2	191888	184347	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69392	0	0
T13	637	66	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	970	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	184	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T9	0	1	0	0
T13	637	1	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	155	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T9	0	1	0	0
T13	637	1	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T90	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	153	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T9	0	1	0	0
T13	637	1	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T90	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	153	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T9	0	1	0	0
T13	637	1	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T90	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	827	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	13	0	0
T9	0	5	0	0
T13	637	10	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	6	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	8	0	0
T43	0	12	0	0
T44	0	4	0	0
T47	0	15	0	0
T49	0	4	0	0
T90	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7145	0	0
T1	7746	11	0	0
T2	191888	32	0	0
T3	11238	25	0	0
T4	491	7	0	0
T5	582	0	0	0
T6	76975	63	0	0
T13	637	2	0	0
T14	422	4	0	0
T15	405	1	0	0
T16	5222	23	0	0
T17	0	15	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	153	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T9	0	1	0	0
T13	637	1	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T90	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T4,T1,T13
1	1	Covered	T6,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T55
0	1	Covered	T87,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T55
0	1	Unreachable
1	0	Covered	T8,T11,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T11
DetectSt	168	Covered	T8,T11,T55
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T55
DebounceSt->IdleSt	163	Covered	T6,T57,T114
DetectSt->IdleSt	186	Covered	T87,T88,T89
DetectSt->StableSt	191	Covered	T8,T11,T55
IdleSt->DebounceSt	148	Covered	T6,T8,T11
StableSt->IdleSt	206	Covered	T8,T11,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T55
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T57,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T87,T88,T89
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T55
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	203	0	0
CntIncr_A	8343984	224095	0	0
CntNoWrap_A	8343984	7672315	0	0
DetectStDropOut_A	8343984	7	0	0
DetectedOut_A	8343984	251959	0	0
DetectedPulseOut_A	8343984	59	0	0
DisabledIdleSt_A	8343984	6564436	0	0
DisabledNoDetection_A	8343984	6566880	0	0
EnterDebounceSt_A	8343984	139	0	0
EnterDetectSt_A	8343984	66	0	0
EnterStableSt_A	8343984	59	0	0
PulseIsPulse_A	8343984	59	0	0
StayInStableSt	8343984	251900	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8343984	7145	0	0
gen_low_level_sva.LowLevelEvent_A	8343984	7674965	0	0
gen_sticky_sva.StableStDropOut_A	8343984	287479	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	203	0	0
T6	76975	4	0	0
T7	23528	0	0	0
T8	0	2	0	0
T11	0	6	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	4	0	0
T59	495	0	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	454	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	224095	0	0
T6	76975	68	0	0
T7	23528	0	0	0
T8	0	17	0	0
T11	0	96	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	84	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	93	0	0
T56	0	21	0	0
T57	0	336	0	0
T59	495	0	0	0
T71	0	51	0	0
T72	0	118	0	0
T73	0	174	0	0
T74	454	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672315	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69703	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7	0	0
T87	64838	1	0	0
T88	2180	1	0	0
T89	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	503	0	0	0
T125	422	0	0	0
T126	406	0	0	0
T127	18930	0	0	0
T128	20101	0	0	0
T129	673	0	0	0
T130	501	0	0	0
T131	530	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	251959	0	0
T8	1925	34	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	316	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	16	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	137	0	0
T56	0	51	0	0
T62	525	0	0	0
T71	0	132	0	0
T72	0	420	0	0
T73	0	422	0	0
T102	453	0	0	0
T115	0	22	0	0
T116	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	59	0	0
T8	1925	1	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	3	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	525	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T102	453	0	0	0
T115	0	1	0	0
T116	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6564436	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69161	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6566880	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69187	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	139	0	0
T6	76975	4	0	0
T7	23528	0	0	0
T8	0	1	0	0
T11	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	4	0	0
T59	495	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	454	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	66	0	0
T8	1925	1	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	3	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	525	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T102	453	0	0	0
T115	0	1	0	0
T116	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	59	0	0
T8	1925	1	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	3	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	525	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T102	453	0	0	0
T115	0	1	0	0
T116	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	59	0	0
T8	1925	1	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	3	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	525	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T102	453	0	0	0
T115	0	1	0	0
T116	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	251900	0	0
T8	1925	33	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	313	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	15	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	136	0	0
T56	0	50	0	0
T62	525	0	0	0
T71	0	131	0	0
T72	0	418	0	0
T73	0	420	0	0
T102	453	0	0	0
T115	0	21	0	0
T116	0	52	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7145	0	0
T1	7746	11	0	0
T2	191888	32	0	0
T3	11238	25	0	0
T4	491	7	0	0
T5	582	0	0	0
T6	76975	63	0	0
T13	637	2	0	0
T14	422	4	0	0
T15	405	1	0	0
T16	5222	23	0	0
T17	0	15	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	287479	0	0
T8	1925	134	0	0
T9	1884	0	0	0
T10	575	0	0	0
T11	0	1290	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T38	0	47	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T55	0	53	0	0
T56	0	240	0	0
T62	525	0	0	0
T71	0	83	0	0
T72	0	161	0	0
T73	0	117	0	0
T102	453	0	0	0
T115	0	42	0	0
T116	0	98	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T14,T15
1	1	Covered	T4,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T4,T14,T15
1	1	Covered	T6,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T8,T73,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Unreachable
1	0	Covered	T6,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T11
DetectSt	168	Covered	T6,T8,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T11
DebounceSt->IdleSt	163	Covered	T71,T72,T73
DetectSt->IdleSt	186	Covered	T8,T73,T86
DetectSt->StableSt	191	Covered	T6,T8,T11
IdleSt->DebounceSt	148	Covered	T6,T8,T11
StableSt->IdleSt	206	Covered	T6,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T72,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T8,T73,T86
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	188	0	0
CntIncr_A	8343984	50186	0	0
CntNoWrap_A	8343984	7672330	0	0
DetectStDropOut_A	8343984	6	0	0
DetectedOut_A	8343984	232365	0	0
DetectedPulseOut_A	8343984	68	0	0
DisabledIdleSt_A	8343984	6564436	0	0
DisabledNoDetection_A	8343984	6566880	0	0
EnterDebounceSt_A	8343984	116	0	0
EnterDetectSt_A	8343984	74	0	0
EnterStableSt_A	8343984	68	0	0
PulseIsPulse_A	8343984	68	0	0
StayInStableSt	8343984	232297	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_sticky_sva.StableStDropOut_A	8343984	763255	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	188	0	0
T6	76975	2	0	0
T7	23528	0	0	0
T8	0	4	0	0
T11	0	6	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T59	495	0	0	0
T71	0	2	0	0
T72	0	6	0	0
T73	0	6	0	0
T74	454	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	50186	0	0
T6	76975	68	0	0
T7	23528	0	0	0
T8	0	98	0	0
T11	0	300	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	61	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	40	0	0
T56	0	92	0	0
T57	0	74	0	0
T59	495	0	0	0
T71	0	50	0	0
T72	0	138	0	0
T73	0	280	0	0
T74	454	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672330	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69705	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6	0	0
T8	1925	1	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T73	0	1	0	0
T86	0	1	0	0
T102	453	0	0	0
T132	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	232365	0	0
T6	76975	309	0	0
T7	23528	0	0	0
T8	0	2	0	0
T11	0	1049	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	9	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	86	0	0
T56	0	186	0	0
T57	0	248	0	0
T59	495	0	0	0
T73	0	73	0	0
T74	454	0	0	0
T114	0	150	0	0
T115	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	68	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T8	0	1	0	0
T11	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	495	0	0	0
T73	0	1	0	0
T74	454	0	0	0
T114	0	1	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6564436	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69161	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6566880	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69187	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	116	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T8	0	2	0	0
T11	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	495	0	0	0
T71	0	2	0	0
T72	0	6	0	0
T73	0	4	0	0
T74	454	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	74	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T8	0	2	0	0
T11	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	495	0	0	0
T73	0	2	0	0
T74	454	0	0	0
T114	0	1	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	68	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T8	0	1	0	0
T11	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	495	0	0	0
T73	0	1	0	0
T74	454	0	0	0
T114	0	1	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	68	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T8	0	1	0	0
T11	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	495	0	0	0
T73	0	1	0	0
T74	454	0	0	0
T114	0	1	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	232297	0	0
T6	76975	308	0	0
T7	23528	0	0	0
T8	0	1	0	0
T11	0	1046	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	8	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	85	0	0
T56	0	185	0	0
T57	0	247	0	0
T59	495	0	0	0
T73	0	72	0	0
T74	454	0	0	0
T114	0	149	0	0
T115	0	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	763255	0	0
T6	76975	157	0	0
T7	23528	0	0	0
T8	0	45	0	0
T11	0	347	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	74	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	156	0	0
T56	0	33	0	0
T57	0	265	0	0
T59	495	0	0	0
T73	0	153	0	0
T74	454	0	0	0
T114	0	557	0	0
T115	0	82	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T55,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T4,T1,T14
1	1	Covered	T6,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T56,T71
0	1	Covered	T55,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T56,T71
0	1	Unreachable
1	0	Covered	T6,T56,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T11
DetectSt	168	Covered	T6,T55,T56
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T56,T71

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T55,T56
DebounceSt->IdleSt	163	Covered	T8,T11,T55
DetectSt->IdleSt	186	Covered	T55,T82,T83
DetectSt->StableSt	191	Covered	T6,T56,T71
IdleSt->DebounceSt	148	Covered	T6,T8,T11
StableSt->IdleSt	206	Covered	T6,T56,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T55,T56
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T55,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T11,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T55,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T6,T56,T71
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T56,T71
StableSt	-	-	-	-	-	-	0	Covered	T6,T56,T71
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	212	0	0
CntIncr_A	8343984	356658	0	0
CntNoWrap_A	8343984	7672306	0	0
DetectStDropOut_A	8343984	17	0	0
DetectedOut_A	8343984	9998	0	0
DetectedPulseOut_A	8343984	57	0	0
DisabledIdleSt_A	8343984	6564436	0	0
DisabledNoDetection_A	8343984	6566880	0	0
EnterDebounceSt_A	8343984	140	0	0
EnterDetectSt_A	8343984	74	0	0
EnterStableSt_A	8343984	57	0	0
PulseIsPulse_A	8343984	57	0	0
StayInStableSt	8343984	9941	0	0
gen_high_event_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_sticky_sva.StableStDropOut_A	8343984	520436	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	212	0	0
T6	76975	2	0	0
T7	23528	0	0	0
T8	0	2	0	0
T11	0	8	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	4	0	0
T59	495	0	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	454	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	356658	0	0
T6	76975	71	0	0
T7	23528	0	0	0
T8	0	120	0	0
T11	0	672	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	64	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	176	0	0
T56	0	52	0	0
T57	0	200	0	0
T59	495	0	0	0
T71	0	46	0	0
T72	0	74	0	0
T73	0	66	0	0
T74	454	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672306	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69705	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	17	0	0
T29	21172	0	0	0
T33	784	0	0	0
T37	88465	0	0	0
T40	94204	0	0	0
T49	757	0	0	0
T55	741	1	0	0
T82	0	4	0	0
T83	0	1	0	0
T121	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	422	0	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	9998	0	0
T6	76975	232	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T56	0	97	0	0
T59	495	0	0	0
T71	0	60	0	0
T72	0	174	0	0
T73	0	115	0	0
T74	454	0	0	0
T86	0	718	0	0
T116	0	72	0	0
T117	0	519	0	0
T118	0	891	0	0
T119	0	545	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	57	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T56	0	1	0	0
T59	495	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	454	0	0	0
T86	0	2	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6564436	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69161	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6566880	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69187	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	140	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T8	0	2	0	0
T11	0	8	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	4	0	0
T59	495	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	454	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	74	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	495	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	454	0	0	0
T86	0	2	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	57	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T56	0	1	0	0
T59	495	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	454	0	0	0
T86	0	2	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	57	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T56	0	1	0	0
T59	495	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	454	0	0	0
T86	0	2	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	9941	0	0
T6	76975	231	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T56	0	96	0	0
T59	495	0	0	0
T71	0	59	0	0
T72	0	172	0	0
T73	0	113	0	0
T74	454	0	0	0
T86	0	716	0	0
T116	0	70	0	0
T117	0	518	0	0
T118	0	888	0	0
T119	0	544	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	520436	0	0
T6	76975	237	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T56	0	181	0	0
T59	495	0	0	0
T71	0	176	0	0
T72	0	466	0	0
T73	0	558	0	0
T74	454	0	0	0
T86	0	79	0	0
T116	0	75	0	0
T117	0	55	0	0
T118	0	123	0	0
T119	0	60	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T40,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T40,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T40,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T40,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T41
0	1	Covered	T39,T78,T142
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T39,T41
1	-	Covered	T39,T78,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T40,T39
DetectSt	168	Covered	T40,T39,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T40,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T39,T41
DebounceSt->IdleSt	163	Covered	T2,T36,T41
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T39,T41
IdleSt->DebounceSt	148	Covered	T2,T40,T39
StableSt->IdleSt	206	Covered	T39,T41,T143

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T40,T39
0	1	Covered	T2,T40,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T39,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T40,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T36,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T40,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T78,T142
StableSt	-	-	-	-	-	-	0	Covered	T40,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	84	0	0
CntIncr_A	8343984	134051	0	0
CntNoWrap_A	8343984	7672434	0	0
DetectStDropOut_A	8343984	0	0	0
DetectedOut_A	8343984	2645	0	0
DetectedPulseOut_A	8343984	40	0	0
DisabledIdleSt_A	8343984	7102056	0	0
DisabledNoDetection_A	8343984	7104440	0	0
EnterDebounceSt_A	8343984	44	0	0
EnterDetectSt_A	8343984	40	0	0
EnterStableSt_A	8343984	40	0	0
PulseIsPulse_A	8343984	40	0	0
StayInStableSt	8343984	2577	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	84	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	4	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	134051	0	0
T2	191888	27	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T36	0	30	0	0
T39	0	12	0	0
T40	0	39985	0	0
T41	0	102	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	60	0	0
T142	0	49794	0	0
T143	0	82	0	0
T144	0	83	0	0
T145	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672434	0	0
T1	7746	7336	0	0
T2	191888	186461	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2645	0	0
T29	21172	0	0	0
T30	8972	0	0	0
T39	0	7	0	0
T40	94204	42	0	0
T41	0	48	0	0
T58	567	0	0	0
T78	0	85	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0
T142	0	39	0	0
T143	0	134	0	0
T144	0	126	0	0
T145	0	108	0	0
T146	0	165	0	0
T147	0	116	0	0
T148	1744	0	0	0
T149	504	0	0	0
T150	504	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	40	0	0
T29	21172	0	0	0
T30	8972	0	0	0
T39	0	1	0	0
T40	94204	1	0	0
T41	0	1	0	0
T58	567	0	0	0
T78	0	2	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	1744	0	0	0
T149	504	0	0	0
T150	504	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7102056	0	0
T1	7746	7336	0	0
T2	191888	186149	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69346	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7104440	0	0
T1	7746	7338	0	0
T2	191888	186163	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69371	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	44	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	40	0	0
T29	21172	0	0	0
T30	8972	0	0	0
T39	0	1	0	0
T40	94204	1	0	0
T41	0	1	0	0
T58	567	0	0	0
T78	0	2	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	1744	0	0	0
T149	504	0	0	0
T150	504	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	40	0	0
T29	21172	0	0	0
T30	8972	0	0	0
T39	0	1	0	0
T40	94204	1	0	0
T41	0	1	0	0
T58	567	0	0	0
T78	0	2	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	1744	0	0	0
T149	504	0	0	0
T150	504	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	40	0	0
T29	21172	0	0	0
T30	8972	0	0	0
T39	0	1	0	0
T40	94204	1	0	0
T41	0	1	0	0
T58	567	0	0	0
T78	0	2	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	1744	0	0	0
T149	504	0	0	0
T150	504	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2577	0	0
T29	21172	0	0	0
T30	8972	0	0	0
T39	0	6	0	0
T40	94204	40	0	0
T41	0	46	0	0
T58	567	0	0	0
T78	0	82	0	0
T139	529	0	0	0
T140	522	0	0	0
T141	533	0	0	0
T142	0	38	0	0
T143	0	132	0	0
T144	0	124	0	0
T145	0	106	0	0
T146	0	163	0	0
T147	0	115	0	0
T148	1744	0	0	0
T149	504	0	0	0
T150	504	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	10	0	0
T39	23381	1	0	0
T78	0	1	0	0
T91	47968	0	0	0
T142	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	422	0	0	0
T158	495	0	0	0
T159	407	0	0	0
T160	8493	0	0	0
T161	724	0	0	0
T162	508	0	0	0
T163	15305	0	0	0
T164	107407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T6,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T33
1	0	Covered	T4,T1,T14
1	1	Covered	T2,T6,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T37
0	1	Covered	T78,T165
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T37
0	1	Covered	T2,T37,T34
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T37
1	-	Covered	T2,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T33
DetectSt	168	Covered	T2,T6,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T6,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T37
DebounceSt->IdleSt	163	Covered	T33,T78,T127
DetectSt->IdleSt	186	Covered	T78,T165
DetectSt->StableSt	191	Covered	T2,T6,T37
IdleSt->DebounceSt	148	Covered	T2,T6,T33
StableSt->IdleSt	206	Covered	T2,T6,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T33
0	1	Covered	T2,T6,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T78,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T33
DetectSt	-	-	-	-	1	-	-	Covered	T78,T165
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	122	0	0
CntIncr_A	8343984	72656	0	0
CntNoWrap_A	8343984	7672396	0	0
DetectStDropOut_A	8343984	3	0	0
DetectedOut_A	8343984	14184	0	0
DetectedPulseOut_A	8343984	54	0	0
DisabledIdleSt_A	8343984	7531880	0	0
DisabledNoDetection_A	8343984	7534271	0	0
EnterDebounceSt_A	8343984	65	0	0
EnterDetectSt_A	8343984	57	0	0
EnterStableSt_A	8343984	54	0	0
PulseIsPulse_A	8343984	54	0	0
StayInStableSt	8343984	14106	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8343984	2578	0	0
gen_low_level_sva.LowLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	122	0	0
T2	191888	4	0	0
T3	11238	0	0	0
T6	76975	2	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	4	0	0
T36	0	4	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	2	0	0
T78	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	72656	0	0
T2	191888	54	0	0
T3	11238	0	0	0
T6	76975	34	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	36	0	0
T34	0	110	0	0
T36	0	60	0	0
T37	0	51486	0	0
T38	0	75	0	0
T39	0	20	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	79	0	0
T78	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672396	0	0
T1	7746	7336	0	0
T2	191888	186458	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69705	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	3	0	0
T78	38528	1	0	0
T93	22978	0	0	0
T94	8403	0	0	0
T142	203797	0	0	0
T144	1063	0	0	0
T165	0	2	0	0
T166	502	0	0	0
T167	27877	0	0	0
T168	422	0	0	0
T169	857	0	0	0
T170	437	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14184	0	0
T2	191888	225	0	0
T3	11238	0	0	0
T6	76975	287	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	237	0	0
T36	0	191	0	0
T37	0	9218	0	0
T38	0	45	0	0
T39	0	66	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	44	0	0
T144	0	40	0	0
T171	0	135	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	54	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T144	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7531880	0	0
T1	7746	7336	0	0
T2	191888	186149	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69346	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7534271	0	0
T1	7746	7338	0	0
T2	191888	186163	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69371	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	65	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	57	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T78	0	1	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	54	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T144	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	54	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T144	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14106	0	0
T2	191888	222	0	0
T3	11238	0	0	0
T6	76975	285	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	234	0	0
T36	0	188	0	0
T37	0	9215	0	0
T38	0	43	0	0
T39	0	64	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T65	0	42	0	0
T144	0	39	0	0
T171	0	133	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2578	0	0
T1	7746	0	0	0
T2	191888	17	0	0
T3	11238	20	0	0
T4	491	5	0	0
T5	582	0	0	0
T6	76975	38	0	0
T13	637	0	0	0
T14	422	2	0	0
T15	405	1	0	0
T16	5222	14	0	0
T17	0	10	0	0
T44	0	22	0	0
T59	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	28	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0