Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T6,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T10
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T6,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T78,T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T173
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T12
1	-	Covered	T2,T6,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T12
DetectSt	168	Covered	T2,T6,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T6,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T12
DebounceSt->IdleSt	163	Covered	T147,T83,T152
DetectSt->IdleSt	186	Covered	T78,T156
DetectSt->StableSt	191	Covered	T2,T6,T12
IdleSt->DebounceSt	148	Covered	T2,T6,T12
StableSt->IdleSt	206	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T12
0	1	Covered	T2,T6,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T83,T152
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T12
DetectSt	-	-	-	-	1	-	-	Covered	T78,T156
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T173
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	71	0	0
CntIncr_A	8343984	234659	0	0
CntNoWrap_A	8343984	7672447	0	0
DetectStDropOut_A	8343984	2	0	0
DetectedOut_A	8343984	12643	0	0
DetectedPulseOut_A	8343984	32	0	0
DisabledIdleSt_A	8343984	6965485	0	0
DisabledNoDetection_A	8343984	6967871	0	0
EnterDebounceSt_A	8343984	37	0	0
EnterDetectSt_A	8343984	34	0	0
EnterStableSt_A	8343984	32	0	0
PulseIsPulse_A	8343984	32	0	0
StayInStableSt	8343984	12595	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	71	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	2	0	0
T12	0	2	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	2	0	0
T84	0	2	0	0
T142	0	4	0	0
T143	0	2	0	0
T145	0	2	0	0
T147	0	3	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	234659	0	0
T2	191888	27	0	0
T3	11238	0	0	0
T6	76975	34	0	0
T12	0	20	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	30	0	0
T84	0	57	0	0
T142	0	99588	0	0
T143	0	82	0	0
T145	0	33	0	0
T147	0	142	0	0
T173	0	1020	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672447	0	0
T1	7746	7336	0	0
T2	191888	186460	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69705	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2	0	0
T78	38528	1	0	0
T93	22978	0	0	0
T94	8403	0	0	0
T142	203797	0	0	0
T144	1063	0	0	0
T156	0	1	0	0
T166	502	0	0	0
T167	27877	0	0	0
T168	422	0	0	0
T169	857	0	0	0
T170	437	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	12643	0	0
T2	191888	42	0	0
T3	11238	0	0	0
T6	76975	43	0	0
T12	0	137	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	87	0	0
T84	0	47	0	0
T142	0	81	0	0
T143	0	7	0	0
T145	0	125	0	0
T147	0	91	0	0
T173	0	840	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	32	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6965485	0	0
T1	7746	7336	0	0
T2	191888	186149	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69346	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6967871	0	0
T1	7746	7338	0	0
T2	191888	186163	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69371	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	37	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	1	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T147	0	2	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	34	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T78	0	1	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	32	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	32	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	12595	0	0
T2	191888	41	0	0
T3	11238	0	0	0
T6	76975	42	0	0
T12	0	135	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	86	0	0
T84	0	45	0	0
T142	0	78	0	0
T143	0	6	0	0
T145	0	124	0	0
T147	0	89	0	0
T173	0	839	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	0	1	0	0
T154	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T33,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T33,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T33,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T33
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T33,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T39
0	1	Covered	T39,T36,T84
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T33,T39
1	-	Covered	T39,T36,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T33,T39
DetectSt	168	Covered	T3,T33,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T33,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T33,T39
DebounceSt->IdleSt	163	Covered	T154,T175,T176
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T33,T39
IdleSt->DebounceSt	148	Covered	T3,T33,T39
StableSt->IdleSt	206	Covered	T3,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T33,T39
0	1	Covered	T3,T33,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T33,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T33,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T33,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T175,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T33,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T33,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T36,T84
StableSt	-	-	-	-	-	-	0	Covered	T3,T33,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	129	0	0
CntIncr_A	8343984	123152	0	0
CntNoWrap_A	8343984	7672389	0	0
DetectStDropOut_A	8343984	0	0	0
DetectedOut_A	8343984	29134	0	0
DetectedPulseOut_A	8343984	62	0	0
DisabledIdleSt_A	8343984	7409324	0	0
DisabledNoDetection_A	8343984	7411716	0	0
EnterDebounceSt_A	8343984	67	0	0
EnterDetectSt_A	8343984	62	0	0
EnterStableSt_A	8343984	62	0	0
PulseIsPulse_A	8343984	62	0	0
StayInStableSt	8343984	29041	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8343984	2933	0	0
gen_low_level_sva.LowLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	129	0	0
T3	11238	4	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	4	0	0
T39	0	2	0	0
T41	0	4	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	2	0	0
T142	0	4	0	0
T143	0	4	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	123152	0	0
T3	11238	166	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	36	0	0
T34	0	55	0	0
T36	0	60	0	0
T39	0	12	0	0
T41	0	102	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	57	0	0
T142	0	99588	0	0
T143	0	164	0	0
T173	0	2040	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672389	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5882	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	29134	0	0
T3	11238	78	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	43	0	0
T34	0	291	0	0
T36	0	146	0	0
T39	0	73	0	0
T41	0	138	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	100	0	0
T142	0	4128	0	0
T143	0	171	0	0
T173	0	1906	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	62	0	0
T3	11238	2	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T173	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7409324	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5436	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7411716	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5447	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	67	0	0
T3	11238	2	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	62	0	0
T3	11238	2	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	62	0	0
T3	11238	2	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T173	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	62	0	0
T3	11238	2	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T173	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	29041	0	0
T3	11238	74	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	41	0	0
T34	0	289	0	0
T36	0	143	0	0
T39	0	72	0	0
T41	0	135	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	99	0	0
T142	0	4126	0	0
T143	0	168	0	0
T173	0	1903	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2933	0	0
T1	7746	0	0	0
T2	191888	23	0	0
T3	11238	28	0	0
T4	491	3	0	0
T5	582	5	0	0
T6	76975	31	0	0
T13	637	0	0	0
T14	422	1	0	0
T15	405	0	0	0
T16	5222	18	0	0
T17	0	10	0	0
T18	0	2	0	0
T59	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	29	0	0
T36	0	1	0	0
T39	23381	1	0	0
T41	0	1	0	0
T83	0	4	0	0
T84	0	1	0	0
T91	47968	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T157	422	0	0	0
T158	495	0	0	0
T159	407	0	0	0
T160	8493	0	0	0
T161	724	0	0	0
T162	508	0	0	0
T163	15305	0	0	0
T164	107407	0	0	0
T172	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T14
1	1	Covered	T4,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T1,T14
1	1	Covered	T6,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T9,T33,T34
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T10
1	-	Covered	T9,T33,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T10
DetectSt	168	Covered	T6,T9,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T10
DebounceSt->IdleSt	163	Covered	T6,T12,T34
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T9,T10
IdleSt->DebounceSt	148	Covered	T6,T9,T10
StableSt->IdleSt	206	Covered	T6,T9,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T10
0	1	Covered	T6,T9,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T12,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T33,T34
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	141	0	0
CntIncr_A	8343984	164088	0	0
CntNoWrap_A	8343984	7672377	0	0
DetectStDropOut_A	8343984	0	0	0
DetectedOut_A	8343984	95540	0	0
DetectedPulseOut_A	8343984	67	0	0
DisabledIdleSt_A	8343984	7019397	0	0
DisabledNoDetection_A	8343984	7021786	0	0
EnterDebounceSt_A	8343984	74	0	0
EnterDetectSt_A	8343984	67	0	0
EnterStableSt_A	8343984	67	0	0
PulseIsPulse_A	8343984	67	0	0
StayInStableSt	8343984	95439	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	141	0	0
T6	76975	3	0	0
T7	23528	0	0	0
T9	0	4	0	0
T10	0	2	0	0
T12	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T35	0	2	0	0
T40	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	2	0	0
T74	454	0	0	0
T108	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	164088	0	0
T6	76975	68	0	0
T7	23528	0	0	0
T9	0	76	0	0
T10	0	93	0	0
T12	0	20	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	72	0	0
T34	0	110	0	0
T35	0	10	0	0
T40	0	39985	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	79	0	0
T74	454	0	0	0
T108	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672377	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69704	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	95540	0	0
T6	76975	167	0	0
T7	23528	0	0	0
T9	0	101	0	0
T10	0	40	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	59	0	0
T34	0	190	0	0
T35	0	72	0	0
T40	0	41	0	0
T41	0	98	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	44	0	0
T74	454	0	0	0
T108	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	67	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T74	454	0	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7019397	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5743	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69346	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7021786	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5755	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69371	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	74	0	0
T6	76975	2	0	0
T7	23528	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T40	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T74	454	0	0	0
T108	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	67	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T74	454	0	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	67	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T74	454	0	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	67	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	1	0	0
T74	454	0	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	95439	0	0
T6	76975	165	0	0
T7	23528	0	0	0
T9	0	98	0	0
T10	0	38	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	57	0	0
T34	0	189	0	0
T35	0	71	0	0
T40	0	39	0	0
T41	0	94	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T65	0	42	0	0
T74	454	0	0	0
T108	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	31	0	0
T9	1884	1	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	2	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T78	0	1	0	0
T83	0	2	0	0
T102	453	0	0	0
T103	548	0	0	0
T154	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T14
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T14
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T12,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T12,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T12,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T12
1	0	Covered	T4,T1,T14
1	1	Covered	T6,T12,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T38
0	1	Covered	T6,T12,T34
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T38
1	-	Covered	T6,T12,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T12,T38
DetectSt	168	Covered	T6,T12,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T12,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T12,T38
DebounceSt->IdleSt	163	Covered	T175
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T12,T38
IdleSt->DebounceSt	148	Covered	T6,T12,T38
StableSt->IdleSt	206	Covered	T6,T12,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T12,T38
0	1	Covered	T6,T12,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T12,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T12,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T175
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T12,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T12,T34
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	75	0	0
CntIncr_A	8343984	44111	0	0
CntNoWrap_A	8343984	7672443	0	0
DetectStDropOut_A	8343984	0	0	0
DetectedOut_A	8343984	2718	0	0
DetectedPulseOut_A	8343984	37	0	0
DisabledIdleSt_A	8343984	7216725	0	0
DisabledNoDetection_A	8343984	7219119	0	0
EnterDebounceSt_A	8343984	38	0	0
EnterDetectSt_A	8343984	37	0	0
EnterStableSt_A	8343984	37	0	0
PulseIsPulse_A	8343984	37	0	0
StayInStableSt	8343984	2665	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8343984	6801	0	0
gen_low_level_sva.LowLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	75	0	0
T6	76975	2	0	0
T7	23528	0	0	0
T12	0	6	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T38	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	2	0	0
T83	0	4	0	0
T145	0	4	0	0
T146	0	2	0	0
T153	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	44111	0	0
T6	76975	34	0	0
T7	23528	0	0	0
T12	0	50	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	110	0	0
T35	0	10	0	0
T38	0	75	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	30	0	0
T83	0	122	0	0
T145	0	66	0	0
T146	0	28	0	0
T153	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672443	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69705	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2718	0	0
T6	76975	86	0	0
T7	23528	0	0	0
T12	0	219	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	85	0	0
T35	0	41	0	0
T38	0	230	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	74	0	0
T83	0	382	0	0
T145	0	148	0	0
T146	0	164	0	0
T153	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	37	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T12	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	1	0	0
T83	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T153	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7216725	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5743	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69346	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7219119	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5755	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69371	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	38	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T12	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	1	0	0
T83	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	37	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T12	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	1	0	0
T83	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T153	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	37	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T12	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	1	0	0
T83	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T153	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	37	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T12	0	3	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	1	0	0
T83	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T153	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2665	0	0
T6	76975	85	0	0
T7	23528	0	0	0
T12	0	214	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	82	0	0
T35	0	39	0	0
T38	0	228	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T78	0	72	0	0
T83	0	380	0	0
T145	0	145	0	0
T146	0	162	0	0
T153	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6801	0	0
T1	7746	14	0	0
T2	191888	20	0	0
T3	11238	26	0	0
T4	491	8	0	0
T5	582	0	0	0
T6	76975	64	0	0
T13	637	0	0	0
T14	422	2	0	0
T15	405	0	0	0
T16	5222	16	0	0
T17	0	13	0	0
T44	0	24	0	0
T59	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	19	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T12	0	1	0	0
T17	1411	0	0	0
T18	691	0	0	0
T34	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T83	0	2	0	0
T145	0	1	0	0
T153	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T14
1	1	Covered	T4,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T4,T1,T14
1	1	Covered	T3,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T12,T33,T38
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T12
1	-	Covered	T12,T33,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T12
DetectSt	168	Covered	T3,T10,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T12
DebounceSt->IdleSt	163	Covered	T39,T127,T174
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T3,T10,T12
IdleSt->DebounceSt	148	Covered	T3,T10,T12
StableSt->IdleSt	206	Covered	T3,T12,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T12
0	1	Covered	T3,T10,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T174,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T33,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	136	0	0
CntIncr_A	8343984	106463	0	0
CntNoWrap_A	8343984	7672382	0	0
DetectStDropOut_A	8343984	1	0	0
DetectedOut_A	8343984	72061	0	0
DetectedPulseOut_A	8343984	65	0	0
DisabledIdleSt_A	8343984	7205182	0	0
DisabledNoDetection_A	8343984	7207573	0	0
EnterDebounceSt_A	8343984	72	0	0
EnterDetectSt_A	8343984	66	0	0
EnterStableSt_A	8343984	65	0	0
PulseIsPulse_A	8343984	65	0	0
StayInStableSt	8343984	71967	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	136	0	0
T3	11238	2	0	0
T6	76975	0	0	0
T10	0	2	0	0
T12	0	2	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T38	0	2	0	0
T39	0	5	0	0
T41	0	2	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	4	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	106463	0	0
T3	11238	79	0	0
T6	76975	0	0	0
T10	0	93	0	0
T12	0	15	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	72	0	0
T34	0	110	0	0
T38	0	75	0	0
T39	0	44	0	0
T41	0	51	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	114	0	0
T173	0	1020	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672382	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5884	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1	0	0
T35	5873	0	0	0
T84	757	1	0	0
T182	420	0	0	0
T183	4820	0	0	0
T184	17027	0	0	0
T185	405	0	0	0
T186	432	0	0	0
T187	522	0	0	0
T188	503	0	0	0
T189	322661	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	72061	0	0
T3	11238	59	0	0
T6	76975	0	0	0
T10	0	73	0	0
T12	0	12	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	109	0	0
T34	0	223	0	0
T38	0	109	0	0
T39	0	94	0	0
T41	0	256	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	27	0	0
T173	0	805	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	65	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7205182	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5743	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7207573	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5755	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	72	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	2	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	66	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	2	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	65	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	65	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	71967	0	0
T3	11238	57	0	0
T6	76975	0	0	0
T10	0	71	0	0
T12	0	11	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T33	0	107	0	0
T34	0	220	0	0
T38	0	108	0	0
T39	0	90	0	0
T41	0	255	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T59	495	0	0	0
T74	454	0	0	0
T84	0	26	0	0
T173	0	804	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	34	0	0
T12	10358	1	0	0
T29	21172	0	0	0
T33	784	2	0	0
T34	0	1	0	0
T37	88465	0	0	0
T38	0	1	0	0
T40	94204	0	0	0
T41	0	1	0	0
T48	5317	0	0	0
T49	757	0	0	0
T55	741	0	0	0
T84	0	1	0	0
T138	422	0	0	0
T143	0	1	0	0
T146	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T190	449	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T14
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T14
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T33,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T33,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T33,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T33
1	0	Covered	T4,T1,T14
1	1	Covered	T9,T33,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T33,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T33,T37
0	1	Covered	T9,T33,T144
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T33,T37
1	-	Covered	T9,T33,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T33,T37
DetectSt	168	Covered	T9,T33,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T33,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T33,T37
DebounceSt->IdleSt	163	Covered	T144,T191,T176
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T33,T37
IdleSt->DebounceSt	148	Covered	T9,T33,T37
StableSt->IdleSt	206	Covered	T9,T33,T144

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T33,T37
0	1	Covered	T9,T33,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T33,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T33,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T33,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T191,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T33,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T33,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T33,T144
StableSt	-	-	-	-	-	-	0	Covered	T9,T33,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	71	0	0
CntIncr_A	8343984	51339	0	0
CntNoWrap_A	8343984	7672447	0	0
DetectStDropOut_A	8343984	0	0	0
DetectedOut_A	8343984	2846	0	0
DetectedPulseOut_A	8343984	34	0	0
DisabledIdleSt_A	8343984	7452774	0	0
DisabledNoDetection_A	8343984	7455173	0	0
EnterDebounceSt_A	8343984	37	0	0
EnterDetectSt_A	8343984	34	0	0
EnterStableSt_A	8343984	34	0	0
PulseIsPulse_A	8343984	34	0	0
StayInStableSt	8343984	2792	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8343984	6444	0	0
gen_low_level_sva.LowLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	71	0	0
T9	1884	4	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T151	0	2	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	51339	0	0
T9	1884	76	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	72	0	0
T36	0	30	0	0
T37	0	25743	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	166	0	0
T145	0	33	0	0
T146	0	28	0	0
T147	0	71	0	0
T151	0	30	0	0
T172	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7672447	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2846	0	0
T9	1884	85	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	119	0	0
T36	0	72	0	0
T37	0	38	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	124	0	0
T145	0	183	0	0
T146	0	165	0	0
T147	0	77	0	0
T151	0	46	0	0
T172	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	34	0	0
T9	1884	2	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7452774	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5579	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7455173	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5591	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	37	0	0
T9	1884	2	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	34	0	0
T9	1884	2	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	34	0	0
T9	1884	2	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	34	0	0
T9	1884	2	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	2792	0	0
T9	1884	82	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	116	0	0
T36	0	70	0	0
T37	0	36	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	123	0	0
T145	0	181	0	0
T146	0	163	0	0
T147	0	76	0	0
T151	0	44	0	0
T172	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	6444	0	0
T1	7746	12	0	0
T2	191888	25	0	0
T3	11238	24	0	0
T4	491	6	0	0
T5	582	0	0	0
T6	76975	53	0	0
T13	637	0	0	0
T14	422	2	0	0
T15	405	0	0	0
T16	5222	14	0	0
T17	0	10	0	0
T44	0	18	0	0
T59	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	12	0	0
T9	1884	1	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T33	0	1	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T62	525	0	0	0
T102	453	0	0	0
T103	548	0	0	0
T144	0	1	0	0
T147	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0