Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T23,T24
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T23,T24
1	0	Covered	T7,T23,T24
1	1	Covered	T7,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T46,T48,T66
1	0	Covered	T66,T79,T93

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
1	0	Covered	T53,T214,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T23,T24
1	-	Covered	T7,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T23,T24
DetectSt	168	Covered	T7,T23,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T23,T24
DebounceSt->IdleSt	163	Covered	T183,T53,T54
DetectSt->IdleSt	186	Covered	T46,T48,T66
DetectSt->StableSt	191	Covered	T7,T23,T24
IdleSt->DebounceSt	148	Covered	T7,T23,T24
StableSt->IdleSt	206	Covered	T7,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T23,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T7,T23,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T53,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T46,T48,T66
DetectSt	-	-	-	-	0	1	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	0	0	-	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	1	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T7,T23,T24
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	3393	0	0
CntIncr_A	8343984	113657	0	0
CntNoWrap_A	8343984	7669125	0	0
DetectStDropOut_A	8343984	487	0	0
DetectedOut_A	8343984	92849	0	0
DetectedPulseOut_A	8343984	1067	0	0
DisabledIdleSt_A	8343984	7165584	0	0
DisabledNoDetection_A	8343984	7167801	0	0
EnterDebounceSt_A	8343984	1703	0	0
EnterDetectSt_A	8343984	1690	0	0
EnterStableSt_A	8343984	1067	0	0
PulseIsPulse_A	8343984	1067	0	0
StayInStableSt	8343984	91649	0	0
gen_high_event_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	928	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	3393	0	0
T7	23528	26	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	50	0	0
T24	20075	18	0	0
T30	0	28	0	0
T45	12897	0	0	0
T46	0	52	0	0
T48	0	50	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	20	0	0
T67	0	2	0	0
T68	0	14	0	0
T69	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	113657	0	0
T7	23528	2171	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	1900	0	0
T24	20075	585	0	0
T30	0	938	0	0
T45	12897	0	0	0
T46	0	1538	0	0
T48	0	1347	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	510	0	0
T67	0	21	0	0
T68	0	490	0	0
T69	0	406	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7669125	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	487	0	0
T11	2230	0	0	0
T12	10358	0	0	0
T46	5599	26	0	0
T47	50219	0	0	0
T48	5317	25	0	0
T55	741	0	0	0
T63	2260	0	0	0
T64	528	0	0	0
T66	0	4	0	0
T79	0	6	0	0
T93	0	2	0	0
T94	0	4	0	0
T95	0	9	0	0
T96	0	7	0	0
T97	0	17	0	0
T101	0	22	0	0
T190	449	0	0	0
T215	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	92849	0	0
T7	23528	2245	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	2664	0	0
T24	20075	285	0	0
T30	0	439	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T67	0	75	0	0
T68	0	167	0	0
T69	0	304	0	0
T70	0	1401	0	0
T75	0	16	0	0
T196	0	2776	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1067	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	9	0	0
T30	0	14	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	7	0	0
T70	0	21	0	0
T75	0	3	0	0
T196	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7165584	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7167801	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1703	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	9	0	0
T30	0	14	0	0
T45	12897	0	0	0
T46	0	26	0	0
T48	0	25	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	10	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1690	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	9	0	0
T30	0	14	0	0
T45	12897	0	0	0
T46	0	26	0	0
T48	0	25	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	10	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1067	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	9	0	0
T30	0	14	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	7	0	0
T70	0	21	0	0
T75	0	3	0	0
T196	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1067	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	9	0	0
T30	0	14	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	7	0	0
T70	0	21	0	0
T75	0	3	0	0
T196	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	91649	0	0
T7	23528	2231	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	2639	0	0
T24	20075	274	0	0
T30	0	425	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T67	0	73	0	0
T68	0	160	0	0
T69	0	297	0	0
T70	0	1380	0	0
T75	0	13	0	0
T196	0	2750	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	928	0	0
T7	23528	12	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	7	0	0
T30	0	14	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	7	0	0
T69	0	7	0	0
T70	0	21	0	0
T75	0	3	0	0
T80	0	6	0	0
T196	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T45,T31,T32
1	0	Covered	T53,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T6
1	-	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T1,T2,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T6
DebounceSt->IdleSt	163	Covered	T2,T6,T12
DetectSt->IdleSt	186	Covered	T45,T31,T32
DetectSt->StableSt	191	Covered	T1,T2,T6
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T6,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T45,T31,T32
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	1027	0	0
CntIncr_A	8343984	51649	0	0
CntNoWrap_A	8343984	7671491	0	0
DetectStDropOut_A	8343984	102	0	0
DetectedOut_A	8343984	15290	0	0
DetectedPulseOut_A	8343984	373	0	0
DisabledIdleSt_A	8343984	7250111	0	0
DisabledNoDetection_A	8343984	7251731	0	0
EnterDebounceSt_A	8343984	553	0	0
EnterDetectSt_A	8343984	479	0	0
EnterStableSt_A	8343984	373	0	0
PulseIsPulse_A	8343984	373	0	0
StayInStableSt	8343984	14877	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	331	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1027	0	0
T1	7746	2	0	0
T2	191888	3	0	0
T3	11238	0	0	0
T6	76975	11	0	0
T7	0	2	0	0
T8	0	2	0	0
T12	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	2	0	0
T29	0	6	0	0
T45	0	14	0	0
T57	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	51649	0	0
T1	7746	122	0	0
T2	191888	45	0	0
T3	11238	0	0	0
T6	76975	536	0	0
T7	0	183	0	0
T8	0	25	0	0
T12	0	70	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	38	0	0
T29	0	489	0	0
T45	0	471	0	0
T57	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7671491	0	0
T1	7746	7334	0	0
T2	191888	186459	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69696	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	102	0	0
T11	2230	0	0	0
T31	0	2	0	0
T32	0	4	0	0
T39	0	1	0	0
T45	12897	7	0	0
T46	5599	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T63	2260	0	0	0
T78	0	4	0	0
T91	0	2	0	0
T92	0	1	0	0
T98	0	1	0	0
T99	0	4	0	0
T100	0	2	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	15290	0	0
T1	7746	12	0	0
T2	191888	3	0	0
T3	11238	0	0	0
T6	76975	37	0	0
T7	0	77	0	0
T8	0	3	0	0
T12	0	7	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	66	0	0
T29	0	15	0	0
T57	0	3	0	0
T67	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	373	0	0
T1	7746	1	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	5	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T57	0	1	0	0
T67	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7250111	0	0
T1	7746	4030	0	0
T2	191888	186333	0	0
T3	11238	5697	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	64547	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7251731	0	0
T1	7746	4030	0	0
T2	191888	186346	0	0
T3	11238	5709	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	64563	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	553	0	0
T1	7746	1	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	6	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	0	3	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T45	0	7	0	0
T57	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	479	0	0
T1	7746	1	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	5	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T45	0	7	0	0
T57	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	373	0	0
T1	7746	1	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	5	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T57	0	1	0	0
T67	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	373	0	0
T1	7746	1	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	5	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T57	0	1	0	0
T67	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14877	0	0
T1	7746	11	0	0
T2	191888	2	0	0
T3	11238	0	0	0
T6	76975	32	0	0
T7	0	75	0	0
T8	0	2	0	0
T12	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T24	0	64	0	0
T29	0	12	0	0
T57	0	2	0	0
T67	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	331	0	0
T1	7746	1	0	0
T2	191888	1	0	0
T3	11238	0	0	0
T6	76975	5	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T29	0	3	0	0
T38	0	1	0	0
T57	0	1	0	0
T67	0	1	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T23,T24
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T23,T24
1	0	Covered	T7,T23,T24
1	1	Covered	T7,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T7,T46,T48
1	0	Covered	T7,T66,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T30
0	1	Covered	T23,T24,T30
1	0	Covered	T80,T76,T216

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T24,T30
1	-	Covered	T23,T24,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T23,T24
DetectSt	168	Covered	T7,T23,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T23,T24,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T23,T24
DebounceSt->IdleSt	163	Covered	T183,T53,T54
DetectSt->IdleSt	186	Covered	T7,T46,T48
DetectSt->StableSt	191	Covered	T23,T24,T30
IdleSt->DebounceSt	148	Covered	T7,T23,T24
StableSt->IdleSt	206	Covered	T23,T24,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T23,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T7,T23,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T53,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T7,T46,T48
DetectSt	-	-	-	-	0	1	-	Covered	T23,T24,T30
DetectSt	-	-	-	-	0	0	-	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	1	Covered	T23,T24,T30
StableSt	-	-	-	-	-	-	0	Covered	T23,T24,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	3259	0	0
CntIncr_A	8343984	112836	0	0
CntNoWrap_A	8343984	7669259	0	0
DetectStDropOut_A	8343984	468	0	0
DetectedOut_A	8343984	74750	0	0
DetectedPulseOut_A	8343984	939	0	0
DisabledIdleSt_A	8343984	7171219	0	0
DisabledNoDetection_A	8343984	7173481	0	0
EnterDebounceSt_A	8343984	1634	0	0
EnterDetectSt_A	8343984	1626	0	0
EnterStableSt_A	8343984	939	0	0
PulseIsPulse_A	8343984	939	0	0
StayInStableSt	8343984	73722	0	0
gen_high_event_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	838	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	3259	0	0
T7	23528	18	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	54	0	0
T24	20075	18	0	0
T30	0	32	0	0
T45	12897	0	0	0
T46	0	30	0	0
T48	0	34	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	36	0	0
T68	0	14	0	0
T69	0	46	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	112836	0	0
T7	23528	2859	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	2484	0	0
T24	20075	567	0	0
T30	0	1504	0	0
T45	12897	0	0	0
T46	0	880	0	0
T48	0	909	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	919	0	0
T68	0	441	0	0
T69	0	2047	0	0
T70	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7669259	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	468	0	0
T7	23528	2	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	0	0	0
T24	20075	0	0	0
T45	12897	0	0	0
T46	0	15	0	0
T48	0	17	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	10	0	0
T79	0	12	0	0
T95	0	22	0	0
T96	0	13	0	0
T217	0	9	0	0
T218	0	13	0	0
T219	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	74750	0	0
T23	12392	956	0	0
T24	20075	305	0	0
T30	0	660	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T68	0	216	0	0
T69	0	1828	0	0
T70	0	10	0	0
T75	0	1753	0	0
T80	0	419	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T196	0	878	0	0
T220	0	2783	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	939	0	0
T23	12392	27	0	0
T24	20075	9	0	0
T30	0	16	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T68	0	7	0	0
T69	0	23	0	0
T70	0	1	0	0
T75	0	11	0	0
T80	0	13	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T196	0	25	0	0
T220	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7171219	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7173481	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1634	0	0
T7	23528	9	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	9	0	0
T30	0	16	0	0
T45	12897	0	0	0
T46	0	15	0	0
T48	0	17	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	18	0	0
T68	0	7	0	0
T69	0	23	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1626	0	0
T7	23528	9	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	9	0	0
T30	0	16	0	0
T45	12897	0	0	0
T46	0	15	0	0
T48	0	17	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	18	0	0
T68	0	7	0	0
T69	0	23	0	0
T70	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	939	0	0
T23	12392	27	0	0
T24	20075	9	0	0
T30	0	16	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T68	0	7	0	0
T69	0	23	0	0
T70	0	1	0	0
T75	0	11	0	0
T80	0	13	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T196	0	25	0	0
T220	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	939	0	0
T23	12392	27	0	0
T24	20075	9	0	0
T30	0	16	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T68	0	7	0	0
T69	0	23	0	0
T70	0	1	0	0
T75	0	11	0	0
T80	0	13	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T196	0	25	0	0
T220	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	73722	0	0
T23	12392	928	0	0
T24	20075	295	0	0
T30	0	644	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T68	0	209	0	0
T69	0	1804	0	0
T70	0	9	0	0
T75	0	1739	0	0
T80	0	406	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T196	0	853	0	0
T220	0	2764	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	838	0	0
T23	12392	26	0	0
T24	20075	8	0	0
T30	0	16	0	0
T45	12897	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T68	0	7	0	0
T69	0	22	0	0
T70	0	1	0	0
T75	0	8	0	0
T80	0	7	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T196	0	25	0	0
T220	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T6,T38
1	0	Covered	T53,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T45
0	1	Covered	T3,T45,T29
1	0	Covered	T53,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T23,T45
1	-	Covered	T3,T45,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T23,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T1,T6,T45
DetectSt->IdleSt	186	Covered	T1,T6,T38
DetectSt->StableSt	191	Covered	T3,T23,T45
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T3,T23,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T6,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T1,T6,T38
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T45,T29
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	909	0	0
CntIncr_A	8343984	51254	0	0
CntNoWrap_A	8343984	7671609	0	0
DetectStDropOut_A	8343984	54	0	0
DetectedOut_A	8343984	14455	0	0
DetectedPulseOut_A	8343984	371	0	0
DisabledIdleSt_A	8343984	7270619	0	0
DisabledNoDetection_A	8343984	7272358	0	0
EnterDebounceSt_A	8343984	480	0	0
EnterDetectSt_A	8343984	430	0	0
EnterStableSt_A	8343984	371	0	0
PulseIsPulse_A	8343984	371	0	0
StayInStableSt	8343984	14061	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	346	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	909	0	0
T1	7746	8	0	0
T2	191888	0	0	0
T3	11238	2	0	0
T6	76975	3	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	2	0	0
T29	0	12	0	0
T30	0	4	0	0
T31	0	16	0	0
T32	0	7	0	0
T38	0	2	0	0
T45	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	51254	0	0
T1	7746	504	0	0
T2	191888	0	0	0
T3	11238	96	0	0
T6	76975	279	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	91	0	0
T29	0	750	0	0
T30	0	128	0	0
T31	0	638	0	0
T32	0	437	0	0
T38	0	142	0	0
T45	0	318	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7671609	0	0
T1	7746	7328	0	0
T2	191888	186462	0	0
T3	11238	5884	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69704	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	54	0	0
T1	7746	3	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T38	0	1	0	0
T87	0	8	0	0
T180	0	3	0	0
T184	0	3	0	0
T205	0	11	0	0
T221	0	4	0	0
T222	0	3	0	0
T223	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14455	0	0
T3	11238	37	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	57	0	0
T29	0	262	0	0
T30	0	150	0	0
T31	0	81	0	0
T32	0	30	0	0
T39	0	181	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T45	0	33	0	0
T59	495	0	0	0
T74	454	0	0	0
T91	0	201	0	0
T224	0	189	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	371	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T39	0	6	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T45	0	4	0	0
T59	495	0	0	0
T74	454	0	0	0
T91	0	13	0	0
T224	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7270619	0	0
T1	7746	4030	0	0
T2	191888	186462	0	0
T3	11238	5697	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	66633	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7272358	0	0
T1	7746	4030	0	0
T2	191888	186477	0	0
T3	11238	5709	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	66654	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	480	0	0
T1	7746	5	0	0
T2	191888	0	0	0
T3	11238	1	0	0
T6	76975	2	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	9	0	0
T32	0	4	0	0
T38	0	1	0	0
T45	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	430	0	0
T1	7746	3	0	0
T2	191888	0	0	0
T3	11238	1	0	0
T6	76975	1	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T38	0	1	0	0
T45	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	371	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T39	0	6	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T45	0	4	0	0
T59	495	0	0	0
T74	454	0	0	0
T91	0	13	0	0
T224	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	371	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T39	0	6	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T45	0	4	0	0
T59	495	0	0	0
T74	454	0	0	0
T91	0	13	0	0
T224	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14061	0	0
T3	11238	36	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	55	0	0
T29	0	256	0	0
T30	0	148	0	0
T31	0	74	0	0
T32	0	27	0	0
T39	0	175	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T45	0	29	0	0
T59	495	0	0	0
T74	454	0	0	0
T91	0	188	0	0
T224	0	187	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	346	0	0
T3	11238	1	0	0
T6	76975	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T39	0	6	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T45	0	4	0	0
T59	495	0	0	0
T69	0	1	0	0
T74	454	0	0	0
T91	0	13	0	0
T224	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T23,T24
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T23,T24
1	0	Covered	T7,T23,T24
1	1	Covered	T7,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T46,T48,T218
1	0	Covered	T218,T225,T226

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
1	0	Covered	T227

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T23,T24
1	-	Covered	T7,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T23,T24
DetectSt	168	Covered	T7,T23,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T23,T24
DebounceSt->IdleSt	163	Covered	T183,T53,T54
DetectSt->IdleSt	186	Covered	T46,T48,T218
DetectSt->StableSt	191	Covered	T7,T23,T24
IdleSt->DebounceSt	148	Covered	T7,T23,T24
StableSt->IdleSt	206	Covered	T7,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T23,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T7,T23,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T53,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T46,T48,T218
DetectSt	-	-	-	-	0	1	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	0	0	-	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	1	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T7,T23,T24
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	3176	0	0
CntIncr_A	8343984	114478	0	0
CntNoWrap_A	8343984	7669342	0	0
DetectStDropOut_A	8343984	441	0	0
DetectedOut_A	8343984	87250	0	0
DetectedPulseOut_A	8343984	858	0	0
DisabledIdleSt_A	8343984	7169588	0	0
DisabledNoDetection_A	8343984	7171828	0	0
EnterDebounceSt_A	8343984	1595	0	0
EnterDetectSt_A	8343984	1582	0	0
EnterStableSt_A	8343984	858	0	0
PulseIsPulse_A	8343984	858	0	0
StayInStableSt	8343984	86282	0	0
gen_high_event_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	746	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	3176	0	0
T7	23528	26	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	54	0	0
T24	20075	48	0	0
T30	0	20	0	0
T45	12897	0	0	0
T46	0	34	0	0
T48	0	14	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	16	0	0
T68	0	40	0	0
T69	0	52	0	0
T70	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	114478	0	0
T7	23528	2314	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	1782	0	0
T24	20075	888	0	0
T30	0	830	0	0
T45	12897	0	0	0
T46	0	993	0	0
T48	0	372	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	352	0	0
T68	0	1000	0	0
T69	0	1482	0	0
T70	0	290	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7669342	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	441	0	0
T11	2230	0	0	0
T12	10358	0	0	0
T46	5599	17	0	0
T47	50219	0	0	0
T48	5317	7	0	0
T55	741	0	0	0
T63	2260	0	0	0
T64	528	0	0	0
T81	0	15	0	0
T95	0	27	0	0
T97	0	7	0	0
T101	0	25	0	0
T190	449	0	0	0
T215	424	0	0	0
T218	0	12	0	0
T228	0	22	0	0
T229	0	11	0	0
T230	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	87250	0	0
T7	23528	2102	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	1658	0	0
T24	20075	2471	0	0
T30	0	153	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	2015	0	0
T68	0	883	0	0
T69	0	2010	0	0
T70	0	154	0	0
T75	0	1694	0	0
T196	0	664	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	858	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	24	0	0
T30	0	10	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	8	0	0
T68	0	20	0	0
T69	0	26	0	0
T70	0	10	0	0
T75	0	17	0	0
T196	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7169588	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7171828	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1595	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	24	0	0
T30	0	10	0	0
T45	12897	0	0	0
T46	0	17	0	0
T48	0	7	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	8	0	0
T68	0	20	0	0
T69	0	26	0	0
T70	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1582	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	24	0	0
T30	0	10	0	0
T45	12897	0	0	0
T46	0	17	0	0
T48	0	7	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	8	0	0
T68	0	20	0	0
T69	0	26	0	0
T70	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	858	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	24	0	0
T30	0	10	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	8	0	0
T68	0	20	0	0
T69	0	26	0	0
T70	0	10	0	0
T75	0	17	0	0
T196	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	858	0	0
T7	23528	13	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	27	0	0
T24	20075	24	0	0
T30	0	10	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	8	0	0
T68	0	20	0	0
T69	0	26	0	0
T70	0	10	0	0
T75	0	17	0	0
T196	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	86282	0	0
T7	23528	2088	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	1630	0	0
T24	20075	2441	0	0
T30	0	143	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	2002	0	0
T68	0	863	0	0
T69	0	1983	0	0
T70	0	144	0	0
T75	0	1675	0	0
T196	0	647	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	746	0	0
T7	23528	12	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	26	0	0
T24	20075	18	0	0
T30	0	10	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	3	0	0
T68	0	20	0	0
T69	0	25	0	0
T70	0	10	0	0
T75	0	15	0	0
T196	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T6,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T23
0	1	Covered	T45,T29,T31
1	0	Covered	T53,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T23
0	1	Covered	T1,T6,T31
1	0	Covered	T75,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T23
1	-	Covered	T1,T6,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T23
DetectSt	168	Covered	T1,T6,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T6,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T23
DebounceSt->IdleSt	163	Covered	T6,T66,T31
DetectSt->IdleSt	186	Covered	T45,T29,T31
DetectSt->StableSt	191	Covered	T1,T6,T23
IdleSt->DebounceSt	148	Covered	T1,T6,T23
StableSt->IdleSt	206	Covered	T1,T6,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T23
0	1	Covered	T1,T6,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T66,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T23
DetectSt	-	-	-	-	1	-	-	Covered	T45,T29,T31
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T23
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T23
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	820	0	0
CntIncr_A	8343984	45020	0	0
CntNoWrap_A	8343984	7671698	0	0
DetectStDropOut_A	8343984	48	0	0
DetectedOut_A	8343984	14799	0	0
DetectedPulseOut_A	8343984	335	0	0
DisabledIdleSt_A	8343984	7261113	0	0
DisabledNoDetection_A	8343984	7262823	0	0
EnterDebounceSt_A	8343984	433	0	0
EnterDetectSt_A	8343984	387	0	0
EnterStableSt_A	8343984	335	0	0
PulseIsPulse_A	8343984	335	0	0
StayInStableSt	8343984	14424	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	820	0	0
T1	7746	4	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	9	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	2	0	0
T24	0	10	0	0
T29	0	10	0	0
T31	0	16	0	0
T32	0	2	0	0
T38	0	4	0	0
T45	0	4	0	0
T66	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	45020	0	0
T1	7746	226	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	574	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	79	0	0
T24	0	315	0	0
T29	0	842	0	0
T31	0	827	0	0
T32	0	119	0	0
T38	0	251	0	0
T45	0	132	0	0
T66	0	411	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7671698	0	0
T1	7746	7332	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69698	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	48	0	0
T11	2230	0	0	0
T29	0	5	0	0
T31	0	5	0	0
T38	0	1	0	0
T45	12897	2	0	0
T46	5599	0	0	0
T52	525	0	0	0
T60	488	0	0	0
T62	525	0	0	0
T63	2260	0	0	0
T87	0	7	0	0
T102	453	0	0	0
T103	548	0	0	0
T104	450	0	0	0
T175	0	1	0	0
T231	0	2	0	0
T232	0	2	0	0
T233	0	4	0	0
T234	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14799	0	0
T1	7746	43	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	251	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	69	0	0
T24	0	207	0	0
T31	0	49	0	0
T32	0	4	0	0
T38	0	6	0	0
T39	0	34	0	0
T66	0	248	0	0
T224	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	335	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	4	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T31	0	2	0	0
T32	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T66	0	5	0	0
T224	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7261113	0	0
T1	7746	4030	0	0
T2	191888	186462	0	0
T3	11238	5697	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	66633	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7262823	0	0
T1	7746	4030	0	0
T2	191888	186477	0	0
T3	11238	5709	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	66654	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	433	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T29	0	5	0	0
T31	0	9	0	0
T32	0	1	0	0
T38	0	2	0	0
T45	0	2	0	0
T66	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	387	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	4	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T29	0	5	0	0
T31	0	7	0	0
T32	0	1	0	0
T38	0	2	0	0
T45	0	2	0	0
T66	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	335	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	4	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T31	0	2	0	0
T32	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T66	0	5	0	0
T224	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	335	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	4	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T31	0	2	0	0
T32	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T66	0	5	0	0
T224	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14424	0	0
T1	7746	41	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	247	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	67	0	0
T24	0	197	0	0
T31	0	47	0	0
T32	0	3	0	0
T38	0	5	0	0
T39	0	33	0	0
T66	0	238	0	0
T224	0	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	292	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	4	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T75	0	1	0	0
T91	0	11	0	0
T163	0	4	0	0
T224	0	3	0	0